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add back the optimization that Nate added for shl X, (zext_inreg y)

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llvm-svn: 21273
This commit is contained in:
Chris Lattner 2005-04-13 02:58:13 +00:00
parent 759afe07d7
commit 63450e87d9
1 changed files with 23 additions and 2 deletions
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25
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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@ -943,8 +943,18 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
case ISD::SHL: case ISD::SHL:
case ISD::SRL: case ISD::SRL:
case ISD::SRA: case ISD::SRA:
if (N2.getOpcode() == ISD::SIGN_EXTEND_INREG) if (N2.getOpcode() == ISD::SIGN_EXTEND_INREG &&
cast<MVTSDNode>(N2)->getExtraValueType() != MVT::i1)
return getNode(Opcode, VT, N1, N2.getOperand(0)); return getNode(Opcode, VT, N1, N2.getOperand(0));
else if (N2.getOpcode() == ISD::AND)
if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N2.getOperand(1))) {
// If the and is only masking out bits that cannot effect the shift,
// eliminate the and.
unsigned NumBits = MVT::getSizeInBits(VT);
if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1)
return getNode(Opcode, VT, N1, N2.getOperand(0));
}
break; break;
} }
@ -1040,8 +1050,19 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
case ISD::SRA_PARTS: case ISD::SRA_PARTS:
case ISD::SRL_PARTS: case ISD::SRL_PARTS:
case ISD::SHL_PARTS: case ISD::SHL_PARTS:
if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG) if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG &&
cast<MVTSDNode>(N3)->getExtraValueType() != MVT::i1)
return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); return getNode(Opcode, VT, N1, N2, N3.getOperand(0));
else if (N3.getOpcode() == ISD::AND)
if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) {
// If the and is only masking out bits that cannot effect the shift,
// eliminate the and.
unsigned NumBits = MVT::getSizeInBits(VT)*2;
if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1)
return getNode(Opcode, VT, N1, N2, N3.getOperand(0));
}
break; break;
} }