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PR7503: uxtb16 is not available for ARMv7-M. Patch by Brian G. Lucas.

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llvm-svn: 107122
This commit is contained in:
Evan Cheng 2010-06-29 05:38:36 +00:00
parent 9883684f03
commit 6349fa5ec4
2 changed files with 70 additions and 27 deletions
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4
lib/Target/ARM/ARMInstrThumb2.td
View File

@ -1349,9 +1349,9 @@ defm t2UXTB16 : T2I_unary_rrot_uxtb16<0b011, "uxtb16",
UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
def : T2Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
(t2UXTB16r_rot GPR:$Src, 24)>;
(t2UXTB16r_rot GPR:$Src, 24)>, Requires<[HasT2ExtractPack]>;
def : T2Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
(t2UXTB16r_rot GPR:$Src, 8)>;
(t2UXTB16r_rot GPR:$Src, 8)>, Requires<[HasT2ExtractPack]>;
defm t2UXTAB : T2I_bin_rrot<0b101, "uxtab",
BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;

93
test/CodeGen/Thumb2/thumb2-uxtb.ll
View File

@ -1,47 +1,72 @@
; RUN: llc < %s -march=thumb -mattr=+thumb2,+t2xtpk | FileCheck %s
; RUN: llc < %s -march=thumb -mcpu=cortex-a8 | FileCheck %s -check-prefix=ARMv7A
; RUN: llc < %s -march=thumb -mcpu=cortex-m3 | FileCheck %s -check-prefix=ARMv7M
define i32 @test1(i32 %x) {
; CHECK: test1
; CHECK: uxtb16 r0, r0
; ARMv7A: test1
; ARMv7A: uxtb16 r0, r0
; ARMv7M: test1
; ARMv7M: and r0, r0, #16711935
%tmp1 = and i32 %x, 16711935 ; <i32> [#uses=1]
ret i32 %tmp1
}
; PR7503
define i32 @test2(i32 %x) {
; CHECK: test2
; CHECK: uxtb16 r0, r0, ror #8
; ARMv7A: test2
; ARMv7A: uxtb16 r0, r0, ror #8
; ARMv7M: test2
; ARMv7M: mov.w r1, #16711935
; ARMv7M: and.w r0, r1, r0, lsr #8
%tmp1 = lshr i32 %x, 8 ; <i32> [#uses=1]
%tmp2 = and i32 %tmp1, 16711935 ; <i32> [#uses=1]
ret i32 %tmp2
}
define i32 @test3(i32 %x) {
; CHECK: test3
; CHECK: uxtb16 r0, r0, ror #8
; ARMv7A: test3
; ARMv7A: uxtb16 r0, r0, ror #8
; ARMv7M: test3
; ARMv7M: mov.w r1, #16711935
; ARMv7M: and.w r0, r1, r0, lsr #8
%tmp1 = lshr i32 %x, 8 ; <i32> [#uses=1]
%tmp2 = and i32 %tmp1, 16711935 ; <i32> [#uses=1]
ret i32 %tmp2
}
define i32 @test4(i32 %x) {
; CHECK: test4
; CHECK: uxtb16 r0, r0, ror #8
; ARMv7A: test4
; ARMv7A: uxtb16 r0, r0, ror #8
; ARMv7M: test4
; ARMv7M: mov.w r1, #16711935
; ARMv7M: and.w r0, r1, r0, lsr #8
%tmp1 = lshr i32 %x, 8 ; <i32> [#uses=1]
%tmp6 = and i32 %tmp1, 16711935 ; <i32> [#uses=1]
ret i32 %tmp6
}
define i32 @test5(i32 %x) {
; CHECK: test5
; CHECK: uxtb16 r0, r0, ror #8
; ARMv7A: test5
; ARMv7A: uxtb16 r0, r0, ror #8
; ARMv7M: test5
; ARMv7M: mov.w r1, #16711935
; ARMv7M: and.w r0, r1, r0, lsr #8
%tmp1 = lshr i32 %x, 8 ; <i32> [#uses=1]
%tmp2 = and i32 %tmp1, 16711935 ; <i32> [#uses=1]
ret i32 %tmp2
}
define i32 @test6(i32 %x) {
; CHECK: test6
; CHECK: uxtb16 r0, r0, ror #16
; ARMv7A: test6
; ARMv7A: uxtb16 r0, r0, ror #16
; ARMv7M: test6
; ARMv7M: mov.w r1, #16711935
; ARMv7M: and.w r0, r1, r0, ror #16
%tmp1 = lshr i32 %x, 16 ; <i32> [#uses=1]
%tmp2 = and i32 %tmp1, 255 ; <i32> [#uses=1]
%tmp4 = shl i32 %x, 16 ; <i32> [#uses=1]
@ -51,8 +76,12 @@ define i32 @test6(i32 %x) {
}
define i32 @test7(i32 %x) {
; CHECK: test7
; CHECK: uxtb16 r0, r0, ror #16
; ARMv7A: test7
; ARMv7A: uxtb16 r0, r0, ror #16
; ARMv7M: test7
; ARMv7M: mov.w r1, #16711935
; ARMv7M: and.w r0, r1, r0, ror #16
%tmp1 = lshr i32 %x, 16 ; <i32> [#uses=1]
%tmp2 = and i32 %tmp1, 255 ; <i32> [#uses=1]
%tmp4 = shl i32 %x, 16 ; <i32> [#uses=1]
@ -62,8 +91,12 @@ define i32 @test7(i32 %x) {
}
define i32 @test8(i32 %x) {
; CHECK: test8
; CHECK: uxtb16 r0, r0, ror #24
; ARMv7A: test8
; ARMv7A: uxtb16 r0, r0, ror #24
; ARMv7M: test8
; ARMv7M: mov.w r1, #16711935
; ARMv7M: and.w r0, r1, r0, ror #24
%tmp1 = shl i32 %x, 8 ; <i32> [#uses=1]
%tmp2 = and i32 %tmp1, 16711680 ; <i32> [#uses=1]
%tmp5 = lshr i32 %x, 24 ; <i32> [#uses=1]
@ -72,8 +105,12 @@ define i32 @test8(i32 %x) {
}
define i32 @test9(i32 %x) {
; CHECK: test9
; CHECK: uxtb16 r0, r0, ror #24
; ARMv7A: test9
; ARMv7A: uxtb16 r0, r0, ror #24
; ARMv7M: test9
; ARMv7M: mov.w r1, #16711935
; ARMv7M: and.w r0, r1, r0, ror #24
%tmp1 = lshr i32 %x, 24 ; <i32> [#uses=1]
%tmp4 = shl i32 %x, 8 ; <i32> [#uses=1]
%tmp5 = and i32 %tmp4, 16711680 ; <i32> [#uses=1]
@ -82,13 +119,19 @@ define i32 @test9(i32 %x) {
}
define i32 @test10(i32 %p0) {
; CHECK: test10
; CHECK: mov.w r1, #16253176
; CHECK: and.w r0, r1, r0, lsr #7
; CHECK: lsrs r1, r0, #5
; CHECK: uxtb16 r1, r1
; CHECK: orrs r0, r1
; ARMv7A: test10
; ARMv7A: mov.w r1, #16253176
; ARMv7A: and.w r0, r1, r0, lsr #7
; ARMv7A: lsrs r1, r0, #5
; ARMv7A: uxtb16 r1, r1
; ARMv7A: orrs r0, r1
; ARMv7M: test10
; ARMv7M: mov.w r1, #16253176
; ARMv7M: and.w r0, r1, r0, lsr #7
; ARMv7M: mov.w r1, #458759
; ARMv7M: and.w r1, r1, r0, lsr #5
; ARMv7M: orrs r0, r1
%tmp1 = lshr i32 %p0, 7 ; <i32> [#uses=1]
%tmp2 = and i32 %tmp1, 16253176 ; <i32> [#uses=2]
%tmp4 = lshr i32 %tmp2, 5 ; <i32> [#uses=1]