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[ARM] Add and adjust saturation tests for upcoming qadd changes. NFC
llvm-svn: 375401
This commit is contained in:
David Green
parent
d0124d17f9
commit
636ecacbfc
328
test/CodeGen/ARM/qdadd.ll
Normal file
328
test/CodeGen/ARM/qdadd.ll
Normal file
@ -0,0 +1,328 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2NODSP
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; RUN: llc < %s -mtriple=thumbv7em-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2DSP
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; RUN: llc < %s -mtriple=armv5te-none-none-eabi | FileCheck %s --check-prefix=CHECK-ARM --check-prefix=CHECK-ARM6
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; RUN: llc < %s -mtriple=armv8a-none-eabi | FileCheck %s --check-prefix=CHECK-ARM --check-prefix=CHECK-ARM8
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define i32 @qdadd(i32 %x, i32 %y) nounwind {
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; CHECK-T2-LABEL: qdadd:
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; CHECK-T2: @ %bb.0:
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; CHECK-T2-NEXT: .save {r7, lr}
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; CHECK-T2-NEXT: push {r7, lr}
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; CHECK-T2-NEXT: movs r3, #0
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; CHECK-T2-NEXT: adds.w r12, r0, r0
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; CHECK-T2-NEXT: it mi
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; CHECK-T2-NEXT: movmi r3, #1
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; CHECK-T2-NEXT: cmp r3, #0
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; CHECK-T2-NEXT: mov.w r3, #-2147483648
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; CHECK-T2-NEXT: mov.w lr, #0
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; CHECK-T2-NEXT: it ne
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; CHECK-T2-NEXT: mvnne r3, #-2147483648
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; CHECK-T2-NEXT: cmp r12, r0
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; CHECK-T2-NEXT: it vc
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; CHECK-T2-NEXT: movvc r3, r12
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; CHECK-T2-NEXT: adds r0, r3, r1
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; CHECK-T2-NEXT: mov.w r2, #-2147483648
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; CHECK-T2-NEXT: it mi
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; CHECK-T2-NEXT: movmi.w lr, #1
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; CHECK-T2-NEXT: cmp.w lr, #0
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; CHECK-T2-NEXT: it ne
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; CHECK-T2-NEXT: mvnne r2, #-2147483648
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; CHECK-T2-NEXT: cmp r0, r3
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; CHECK-T2-NEXT: it vc
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; CHECK-T2-NEXT: movvc r2, r0
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; CHECK-T2-NEXT: mov r0, r2
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; CHECK-T2-NEXT: pop {r7, pc}
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;
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; CHECK-ARM6-LABEL: qdadd:
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; CHECK-ARM6: @ %bb.0:
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; CHECK-ARM6-NEXT: .save {r11, lr}
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; CHECK-ARM6-NEXT: push {r11, lr}
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; CHECK-ARM6-NEXT: adds r12, r0, r0
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; CHECK-ARM6-NEXT: mov r3, #0
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; CHECK-ARM6-NEXT: movmi r3, #1
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; CHECK-ARM6-NEXT: cmp r3, #0
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; CHECK-ARM6-NEXT: mov r3, #-2147483648
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; CHECK-ARM6-NEXT: mov lr, #0
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; CHECK-ARM6-NEXT: mvnne r3, #-2147483648
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; CHECK-ARM6-NEXT: cmp r12, r0
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; CHECK-ARM6-NEXT: movvc r3, r12
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; CHECK-ARM6-NEXT: adds r0, r3, r1
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; CHECK-ARM6-NEXT: movmi lr, #1
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; CHECK-ARM6-NEXT: mov r2, #-2147483648
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; CHECK-ARM6-NEXT: cmp lr, #0
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; CHECK-ARM6-NEXT: mvnne r2, #-2147483648
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; CHECK-ARM6-NEXT: cmp r0, r3
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; CHECK-ARM6-NEXT: movvc r2, r0
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; CHECK-ARM6-NEXT: mov r0, r2
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; CHECK-ARM6-NEXT: pop {r11, pc}
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;
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; CHECK-ARM8-LABEL: qdadd:
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; CHECK-ARM8: @ %bb.0:
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; CHECK-ARM8-NEXT: .save {r11, lr}
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; CHECK-ARM8-NEXT: push {r11, lr}
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; CHECK-ARM8-NEXT: adds r12, r0, r0
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; CHECK-ARM8-NEXT: mov r3, #0
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; CHECK-ARM8-NEXT: movwmi r3, #1
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; CHECK-ARM8-NEXT: cmp r3, #0
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; CHECK-ARM8-NEXT: mov r3, #-2147483648
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; CHECK-ARM8-NEXT: mov lr, #0
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; CHECK-ARM8-NEXT: mvnne r3, #-2147483648
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; CHECK-ARM8-NEXT: cmp r12, r0
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; CHECK-ARM8-NEXT: movvc r3, r12
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; CHECK-ARM8-NEXT: adds r0, r3, r1
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; CHECK-ARM8-NEXT: movwmi lr, #1
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; CHECK-ARM8-NEXT: mov r2, #-2147483648
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; CHECK-ARM8-NEXT: cmp lr, #0
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; CHECK-ARM8-NEXT: mvnne r2, #-2147483648
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; CHECK-ARM8-NEXT: cmp r0, r3
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; CHECK-ARM8-NEXT: movvc r2, r0
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; CHECK-ARM8-NEXT: mov r0, r2
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; CHECK-ARM8-NEXT: pop {r11, pc}
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%z = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %x)
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%tmp = call i32 @llvm.sadd.sat.i32(i32 %z, i32 %y)
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ret i32 %tmp
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}
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define i32 @qdadd_c(i32 %x, i32 %y) nounwind {
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; CHECK-T2-LABEL: qdadd_c:
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; CHECK-T2: @ %bb.0:
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; CHECK-T2-NEXT: .save {r7, lr}
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; CHECK-T2-NEXT: push {r7, lr}
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; CHECK-T2-NEXT: movs r3, #0
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; CHECK-T2-NEXT: adds.w r12, r0, r0
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; CHECK-T2-NEXT: it mi
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; CHECK-T2-NEXT: movmi r3, #1
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; CHECK-T2-NEXT: cmp r3, #0
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; CHECK-T2-NEXT: mov.w r3, #-2147483648
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; CHECK-T2-NEXT: mov.w lr, #0
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; CHECK-T2-NEXT: it ne
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; CHECK-T2-NEXT: mvnne r3, #-2147483648
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; CHECK-T2-NEXT: cmp r12, r0
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; CHECK-T2-NEXT: it vc
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; CHECK-T2-NEXT: movvc r3, r12
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; CHECK-T2-NEXT: adds r0, r1, r3
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; CHECK-T2-NEXT: mov.w r2, #-2147483648
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; CHECK-T2-NEXT: it mi
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; CHECK-T2-NEXT: movmi.w lr, #1
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; CHECK-T2-NEXT: cmp.w lr, #0
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; CHECK-T2-NEXT: it ne
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; CHECK-T2-NEXT: mvnne r2, #-2147483648
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; CHECK-T2-NEXT: cmp r0, r1
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; CHECK-T2-NEXT: it vc
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; CHECK-T2-NEXT: movvc r2, r0
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; CHECK-T2-NEXT: mov r0, r2
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; CHECK-T2-NEXT: pop {r7, pc}
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;
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; CHECK-ARM6-LABEL: qdadd_c:
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; CHECK-ARM6: @ %bb.0:
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; CHECK-ARM6-NEXT: .save {r11, lr}
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; CHECK-ARM6-NEXT: push {r11, lr}
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; CHECK-ARM6-NEXT: adds r12, r0, r0
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; CHECK-ARM6-NEXT: mov r3, #0
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; CHECK-ARM6-NEXT: movmi r3, #1
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; CHECK-ARM6-NEXT: cmp r3, #0
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; CHECK-ARM6-NEXT: mov r3, #-2147483648
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; CHECK-ARM6-NEXT: mov lr, #0
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; CHECK-ARM6-NEXT: mvnne r3, #-2147483648
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; CHECK-ARM6-NEXT: cmp r12, r0
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; CHECK-ARM6-NEXT: movvc r3, r12
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; CHECK-ARM6-NEXT: adds r0, r1, r3
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; CHECK-ARM6-NEXT: movmi lr, #1
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; CHECK-ARM6-NEXT: mov r2, #-2147483648
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; CHECK-ARM6-NEXT: cmp lr, #0
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; CHECK-ARM6-NEXT: mvnne r2, #-2147483648
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; CHECK-ARM6-NEXT: cmp r0, r1
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; CHECK-ARM6-NEXT: movvc r2, r0
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; CHECK-ARM6-NEXT: mov r0, r2
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; CHECK-ARM6-NEXT: pop {r11, pc}
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;
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; CHECK-ARM8-LABEL: qdadd_c:
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; CHECK-ARM8: @ %bb.0:
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; CHECK-ARM8-NEXT: .save {r11, lr}
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; CHECK-ARM8-NEXT: push {r11, lr}
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; CHECK-ARM8-NEXT: adds r12, r0, r0
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; CHECK-ARM8-NEXT: mov r3, #0
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; CHECK-ARM8-NEXT: movwmi r3, #1
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; CHECK-ARM8-NEXT: cmp r3, #0
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; CHECK-ARM8-NEXT: mov r3, #-2147483648
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; CHECK-ARM8-NEXT: mov lr, #0
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; CHECK-ARM8-NEXT: mvnne r3, #-2147483648
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; CHECK-ARM8-NEXT: cmp r12, r0
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; CHECK-ARM8-NEXT: movvc r3, r12
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; CHECK-ARM8-NEXT: adds r0, r1, r3
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; CHECK-ARM8-NEXT: movwmi lr, #1
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; CHECK-ARM8-NEXT: mov r2, #-2147483648
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; CHECK-ARM8-NEXT: cmp lr, #0
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; CHECK-ARM8-NEXT: mvnne r2, #-2147483648
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; CHECK-ARM8-NEXT: cmp r0, r1
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; CHECK-ARM8-NEXT: movvc r2, r0
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; CHECK-ARM8-NEXT: mov r0, r2
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; CHECK-ARM8-NEXT: pop {r11, pc}
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%z = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %x)
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%tmp = call i32 @llvm.sadd.sat.i32(i32 %y, i32 %z)
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ret i32 %tmp
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}
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define i32 @qdsub(i32 %x, i32 %y) nounwind {
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; CHECK-T2-LABEL: qdsub:
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; CHECK-T2: @ %bb.0:
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; CHECK-T2-NEXT: .save {r7, lr}
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; CHECK-T2-NEXT: push {r7, lr}
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; CHECK-T2-NEXT: movs r3, #0
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; CHECK-T2-NEXT: adds.w r12, r0, r0
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; CHECK-T2-NEXT: it mi
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; CHECK-T2-NEXT: movmi r3, #1
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; CHECK-T2-NEXT: cmp r3, #0
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; CHECK-T2-NEXT: mov.w r3, #-2147483648
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; CHECK-T2-NEXT: mov.w lr, #0
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; CHECK-T2-NEXT: it ne
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; CHECK-T2-NEXT: mvnne r3, #-2147483648
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; CHECK-T2-NEXT: cmp r12, r0
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; CHECK-T2-NEXT: it vc
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; CHECK-T2-NEXT: movvc r3, r12
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; CHECK-T2-NEXT: subs r0, r1, r3
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; CHECK-T2-NEXT: mov.w r2, #-2147483648
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; CHECK-T2-NEXT: it mi
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; CHECK-T2-NEXT: movmi.w lr, #1
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; CHECK-T2-NEXT: cmp.w lr, #0
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; CHECK-T2-NEXT: it ne
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; CHECK-T2-NEXT: mvnne r2, #-2147483648
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; CHECK-T2-NEXT: cmp r1, r3
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; CHECK-T2-NEXT: it vc
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; CHECK-T2-NEXT: movvc r2, r0
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; CHECK-T2-NEXT: mov r0, r2
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; CHECK-T2-NEXT: pop {r7, pc}
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;
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; CHECK-ARM6-LABEL: qdsub:
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; CHECK-ARM6: @ %bb.0:
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; CHECK-ARM6-NEXT: .save {r11, lr}
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; CHECK-ARM6-NEXT: push {r11, lr}
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; CHECK-ARM6-NEXT: adds r12, r0, r0
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; CHECK-ARM6-NEXT: mov r3, #0
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; CHECK-ARM6-NEXT: movmi r3, #1
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; CHECK-ARM6-NEXT: cmp r3, #0
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; CHECK-ARM6-NEXT: mov r3, #-2147483648
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; CHECK-ARM6-NEXT: mov lr, #0
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; CHECK-ARM6-NEXT: mvnne r3, #-2147483648
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; CHECK-ARM6-NEXT: cmp r12, r0
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; CHECK-ARM6-NEXT: movvc r3, r12
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; CHECK-ARM6-NEXT: subs r0, r1, r3
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; CHECK-ARM6-NEXT: movmi lr, #1
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; CHECK-ARM6-NEXT: mov r2, #-2147483648
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; CHECK-ARM6-NEXT: cmp lr, #0
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; CHECK-ARM6-NEXT: mvnne r2, #-2147483648
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; CHECK-ARM6-NEXT: cmp r1, r3
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; CHECK-ARM6-NEXT: movvc r2, r0
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; CHECK-ARM6-NEXT: mov r0, r2
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; CHECK-ARM6-NEXT: pop {r11, pc}
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;
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; CHECK-ARM8-LABEL: qdsub:
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; CHECK-ARM8: @ %bb.0:
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; CHECK-ARM8-NEXT: .save {r11, lr}
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; CHECK-ARM8-NEXT: push {r11, lr}
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; CHECK-ARM8-NEXT: adds r12, r0, r0
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; CHECK-ARM8-NEXT: mov r3, #0
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; CHECK-ARM8-NEXT: movwmi r3, #1
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; CHECK-ARM8-NEXT: cmp r3, #0
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; CHECK-ARM8-NEXT: mov r3, #-2147483648
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; CHECK-ARM8-NEXT: mov lr, #0
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; CHECK-ARM8-NEXT: mvnne r3, #-2147483648
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; CHECK-ARM8-NEXT: cmp r12, r0
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; CHECK-ARM8-NEXT: movvc r3, r12
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; CHECK-ARM8-NEXT: subs r0, r1, r3
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; CHECK-ARM8-NEXT: movwmi lr, #1
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; CHECK-ARM8-NEXT: mov r2, #-2147483648
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; CHECK-ARM8-NEXT: cmp lr, #0
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; CHECK-ARM8-NEXT: mvnne r2, #-2147483648
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; CHECK-ARM8-NEXT: cmp r1, r3
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; CHECK-ARM8-NEXT: movvc r2, r0
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; CHECK-ARM8-NEXT: mov r0, r2
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; CHECK-ARM8-NEXT: pop {r11, pc}
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%z = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %x)
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%tmp = call i32 @llvm.ssub.sat.i32(i32 %y, i32 %z)
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ret i32 %tmp
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}
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define i32 @qdsub_c(i32 %x, i32 %y) nounwind {
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; CHECK-T2-LABEL: qdsub_c:
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; CHECK-T2: @ %bb.0:
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; CHECK-T2-NEXT: .save {r7, lr}
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; CHECK-T2-NEXT: push {r7, lr}
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; CHECK-T2-NEXT: movs r3, #0
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; CHECK-T2-NEXT: adds.w r12, r0, r0
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; CHECK-T2-NEXT: it mi
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; CHECK-T2-NEXT: movmi r3, #1
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; CHECK-T2-NEXT: cmp r3, #0
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; CHECK-T2-NEXT: mov.w r3, #-2147483648
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; CHECK-T2-NEXT: mov.w lr, #0
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; CHECK-T2-NEXT: it ne
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; CHECK-T2-NEXT: mvnne r3, #-2147483648
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; CHECK-T2-NEXT: cmp r12, r0
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; CHECK-T2-NEXT: it vc
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; CHECK-T2-NEXT: movvc r3, r12
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; CHECK-T2-NEXT: subs r0, r3, r1
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; CHECK-T2-NEXT: mov.w r2, #-2147483648
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; CHECK-T2-NEXT: it mi
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; CHECK-T2-NEXT: movmi.w lr, #1
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; CHECK-T2-NEXT: cmp.w lr, #0
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; CHECK-T2-NEXT: it ne
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; CHECK-T2-NEXT: mvnne r2, #-2147483648
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; CHECK-T2-NEXT: cmp r3, r1
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; CHECK-T2-NEXT: it vc
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; CHECK-T2-NEXT: movvc r2, r0
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; CHECK-T2-NEXT: mov r0, r2
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; CHECK-T2-NEXT: pop {r7, pc}
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;
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; CHECK-ARM6-LABEL: qdsub_c:
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; CHECK-ARM6: @ %bb.0:
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; CHECK-ARM6-NEXT: .save {r11, lr}
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; CHECK-ARM6-NEXT: push {r11, lr}
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; CHECK-ARM6-NEXT: adds r12, r0, r0
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; CHECK-ARM6-NEXT: mov r3, #0
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; CHECK-ARM6-NEXT: movmi r3, #1
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; CHECK-ARM6-NEXT: cmp r3, #0
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; CHECK-ARM6-NEXT: mov r3, #-2147483648
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; CHECK-ARM6-NEXT: mov lr, #0
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; CHECK-ARM6-NEXT: mvnne r3, #-2147483648
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; CHECK-ARM6-NEXT: cmp r12, r0
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; CHECK-ARM6-NEXT: movvc r3, r12
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; CHECK-ARM6-NEXT: subs r0, r3, r1
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; CHECK-ARM6-NEXT: movmi lr, #1
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; CHECK-ARM6-NEXT: mov r2, #-2147483648
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; CHECK-ARM6-NEXT: cmp lr, #0
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; CHECK-ARM6-NEXT: mvnne r2, #-2147483648
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; CHECK-ARM6-NEXT: cmp r3, r1
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; CHECK-ARM6-NEXT: movvc r2, r0
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; CHECK-ARM6-NEXT: mov r0, r2
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; CHECK-ARM6-NEXT: pop {r11, pc}
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;
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; CHECK-ARM8-LABEL: qdsub_c:
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; CHECK-ARM8: @ %bb.0:
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; CHECK-ARM8-NEXT: .save {r11, lr}
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; CHECK-ARM8-NEXT: push {r11, lr}
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; CHECK-ARM8-NEXT: adds r12, r0, r0
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; CHECK-ARM8-NEXT: mov r3, #0
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; CHECK-ARM8-NEXT: movwmi r3, #1
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; CHECK-ARM8-NEXT: cmp r3, #0
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; CHECK-ARM8-NEXT: mov r3, #-2147483648
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; CHECK-ARM8-NEXT: mov lr, #0
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; CHECK-ARM8-NEXT: mvnne r3, #-2147483648
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; CHECK-ARM8-NEXT: cmp r12, r0
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; CHECK-ARM8-NEXT: movvc r3, r12
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; CHECK-ARM8-NEXT: subs r0, r3, r1
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; CHECK-ARM8-NEXT: movwmi lr, #1
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; CHECK-ARM8-NEXT: mov r2, #-2147483648
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; CHECK-ARM8-NEXT: cmp lr, #0
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; CHECK-ARM8-NEXT: mvnne r2, #-2147483648
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; CHECK-ARM8-NEXT: cmp r3, r1
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; CHECK-ARM8-NEXT: movvc r2, r0
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; CHECK-ARM8-NEXT: mov r0, r2
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; CHECK-ARM8-NEXT: pop {r11, pc}
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%z = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %x)
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%tmp = call i32 @llvm.ssub.sat.i32(i32 %z, i32 %y)
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ret i32 %tmp
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}
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declare i32 @llvm.sadd.sat.i32(i32, i32)
|
||||
declare i32 @llvm.ssub.sat.i32(i32, i32)
|
||||
@ -2,7 +2,9 @@
|
||||
; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s --check-prefix=CHECK-T1
|
||||
; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2NODSP
|
||||
; RUN: llc < %s -mtriple=thumbv7em-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2DSP
|
||||
; RUN: llc < %s -mtriple=armv8a-none-eabi | FileCheck %s --check-prefix=CHECK-ARM
|
||||
; RUN: llc < %s -mtriple=armv5t-none-eabi | FileCheck %s --check-prefix=CHECK-ARM --check-prefix=CHECK-ARMNODPS
|
||||
; RUN: llc < %s -mtriple=armv5te-none-eabi | FileCheck %s --check-prefix=CHECK-ARM --check-prefix=CHECK-ARMBASEDSP
|
||||
; RUN: llc < %s -mtriple=armv6-none-eabi | FileCheck %s --check-prefix=CHECK-ARM --check-prefix=CHECK-ARMDSP
|
||||
|
||||
declare i4 @llvm.sadd.sat.i4(i4, i4)
|
||||
declare i8 @llvm.sadd.sat.i8(i8, i8)
|
||||
@ -61,7 +63,7 @@ define i32 @func(i32 %x, i32 %y) nounwind {
|
||||
; CHECK-ARM: @ %bb.0:
|
||||
; CHECK-ARM-NEXT: adds r2, r0, r1
|
||||
; CHECK-ARM-NEXT: mov r3, #0
|
||||
; CHECK-ARM-NEXT: movwmi r3, #1
|
||||
; CHECK-ARM-NEXT: movmi r3, #1
|
||||
; CHECK-ARM-NEXT: mov r1, #-2147483648
|
||||
; CHECK-ARM-NEXT: cmp r3, #0
|
||||
; CHECK-ARM-NEXT: mvnne r1, #-2147483648
|
||||
@ -179,29 +181,29 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
|
||||
; CHECK-ARM: @ %bb.0:
|
||||
; CHECK-ARM-NEXT: .save {r11, lr}
|
||||
; CHECK-ARM-NEXT: push {r11, lr}
|
||||
; CHECK-ARM-NEXT: adds r0, r0, r2
|
||||
; CHECK-ARM-NEXT: mov r2, #0
|
||||
; CHECK-ARM-NEXT: adc r12, r1, r3
|
||||
; CHECK-ARM-NEXT: cmn r1, #1
|
||||
; CHECK-ARM-NEXT: mov r1, #0
|
||||
; CHECK-ARM-NEXT: mov lr, #0
|
||||
; CHECK-ARM-NEXT: movwgt r1, #1
|
||||
; CHECK-ARM-NEXT: cmn r12, #1
|
||||
; CHECK-ARM-NEXT: movwgt r2, #1
|
||||
; CHECK-ARM-NEXT: subs r2, r1, r2
|
||||
; CHECK-ARM-NEXT: movwne r2, #1
|
||||
; CHECK-ARM-NEXT: movgt lr, #1
|
||||
; CHECK-ARM-NEXT: adds r0, r0, r2
|
||||
; CHECK-ARM-NEXT: adc r2, r1, r3
|
||||
; CHECK-ARM-NEXT: mov r1, #0
|
||||
; CHECK-ARM-NEXT: cmn r2, #1
|
||||
; CHECK-ARM-NEXT: mov r12, #0
|
||||
; CHECK-ARM-NEXT: movgt r1, #1
|
||||
; CHECK-ARM-NEXT: subs r1, lr, r1
|
||||
; CHECK-ARM-NEXT: movne r1, #1
|
||||
; CHECK-ARM-NEXT: cmn r3, #1
|
||||
; CHECK-ARM-NEXT: movwgt lr, #1
|
||||
; CHECK-ARM-NEXT: sub r1, r1, lr
|
||||
; CHECK-ARM-NEXT: clz r1, r1
|
||||
; CHECK-ARM-NEXT: lsr r1, r1, #5
|
||||
; CHECK-ARM-NEXT: ands r2, r1, r2
|
||||
; CHECK-ARM-NEXT: asrne r0, r12, #31
|
||||
; CHECK-ARM-NEXT: movgt r12, #1
|
||||
; CHECK-ARM-NEXT: sub r3, lr, r12
|
||||
; CHECK-ARM-NEXT: clz r3, r3
|
||||
; CHECK-ARM-NEXT: lsr r3, r3, #5
|
||||
; CHECK-ARM-NEXT: ands r3, r3, r1
|
||||
; CHECK-ARM-NEXT: mov r1, #-2147483648
|
||||
; CHECK-ARM-NEXT: cmp r12, #0
|
||||
; CHECK-ARM-NEXT: mvnmi r1, #-2147483648
|
||||
; CHECK-ARM-NEXT: asrne r0, r2, #31
|
||||
; CHECK-ARM-NEXT: cmp r2, #0
|
||||
; CHECK-ARM-NEXT: moveq r1, r12
|
||||
; CHECK-ARM-NEXT: mvnmi r1, #-2147483648
|
||||
; CHECK-ARM-NEXT: cmp r3, #0
|
||||
; CHECK-ARM-NEXT: moveq r1, r2
|
||||
; CHECK-ARM-NEXT: pop {r11, pc}
|
||||
%tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %y)
|
||||
ret i64 %tmp
|
||||
@ -248,14 +250,18 @@ define signext i16 @func16(i16 signext %x, i16 signext %y) nounwind {
|
||||
; CHECK-ARM-LABEL: func16:
|
||||
; CHECK-ARM: @ %bb.0:
|
||||
; CHECK-ARM-NEXT: add r0, r0, r1
|
||||
; CHECK-ARM-NEXT: movw r1, #32767
|
||||
; CHECK-ARM-NEXT: mov r1, #255
|
||||
; CHECK-ARM-NEXT: orr r1, r1, #32512
|
||||
; CHECK-ARM-NEXT: cmp r0, r1
|
||||
; CHECK-ARM-NEXT: movlt r1, r0
|
||||
; CHECK-ARM-NEXT: movw r0, #32768
|
||||
; CHECK-ARM-NEXT: movt r0, #65535
|
||||
; CHECK-ARM-NEXT: ldr r0, .LCPI2_0
|
||||
; CHECK-ARM-NEXT: cmn r1, #32768
|
||||
; CHECK-ARM-NEXT: movgt r0, r1
|
||||
; CHECK-ARM-NEXT: bx lr
|
||||
; CHECK-ARM-NEXT: .p2align 2
|
||||
; CHECK-ARM-NEXT: @ %bb.1:
|
||||
; CHECK-ARM-NEXT: .LCPI2_0:
|
||||
; CHECK-ARM-NEXT: .long 4294934528 @ 0xffff8000
|
||||
%tmp = call i16 @llvm.sadd.sat.i16(i16 %x, i16 %y)
|
||||
ret i16 %tmp
|
||||
}
|
||||
|
||||
@ -2,7 +2,9 @@
|
||||
; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s --check-prefix=CHECK-T1
|
||||
; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2NODSP
|
||||
; RUN: llc < %s -mtriple=thumbv7em-none-eabi | FileCheck %s --check-prefix=CHECK-T2 --check-prefix=CHECK-T2DSP
|
||||
; RUN: llc < %s -mtriple=armv8a-none-eabi | FileCheck %s --check-prefix=CHECK-ARM
|
||||
; RUN: llc < %s -mtriple=armv5t-none-eabi | FileCheck %s --check-prefix=CHECK-ARM --check-prefix=CHECK-ARMNODPS
|
||||
; RUN: llc < %s -mtriple=armv5te-none-eabi | FileCheck %s --check-prefix=CHECK-ARM --check-prefix=CHECK-ARMBASEDSP
|
||||
; RUN: llc < %s -mtriple=armv6-none-eabi | FileCheck %s --check-prefix=CHECK-ARM --check-prefix=CHECK-ARMDSP
|
||||
|
||||
declare i4 @llvm.ssub.sat.i4(i4, i4)
|
||||
declare i8 @llvm.ssub.sat.i8(i8, i8)
|
||||
@ -64,7 +66,7 @@ define i32 @func(i32 %x, i32 %y) nounwind {
|
||||
; CHECK-ARM: @ %bb.0:
|
||||
; CHECK-ARM-NEXT: subs r12, r0, r1
|
||||
; CHECK-ARM-NEXT: mov r3, #0
|
||||
; CHECK-ARM-NEXT: movwmi r3, #1
|
||||
; CHECK-ARM-NEXT: movmi r3, #1
|
||||
; CHECK-ARM-NEXT: mov r2, #-2147483648
|
||||
; CHECK-ARM-NEXT: cmp r3, #0
|
||||
; CHECK-ARM-NEXT: mvnne r2, #-2147483648
|
||||
@ -184,19 +186,19 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
|
||||
; CHECK-ARM-NEXT: push {r4, lr}
|
||||
; CHECK-ARM-NEXT: cmn r3, #1
|
||||
; CHECK-ARM-NEXT: mov lr, #0
|
||||
; CHECK-ARM-NEXT: movwgt lr, #1
|
||||
; CHECK-ARM-NEXT: movgt lr, #1
|
||||
; CHECK-ARM-NEXT: cmn r1, #1
|
||||
; CHECK-ARM-NEXT: mov r4, #0
|
||||
; CHECK-ARM-NEXT: mov r12, #0
|
||||
; CHECK-ARM-NEXT: movwgt r4, #1
|
||||
; CHECK-ARM-NEXT: movgt r4, #1
|
||||
; CHECK-ARM-NEXT: subs lr, r4, lr
|
||||
; CHECK-ARM-NEXT: movwne lr, #1
|
||||
; CHECK-ARM-NEXT: movne lr, #1
|
||||
; CHECK-ARM-NEXT: subs r0, r0, r2
|
||||
; CHECK-ARM-NEXT: sbc r2, r1, r3
|
||||
; CHECK-ARM-NEXT: cmn r2, #1
|
||||
; CHECK-ARM-NEXT: movwgt r12, #1
|
||||
; CHECK-ARM-NEXT: movgt r12, #1
|
||||
; CHECK-ARM-NEXT: subs r1, r4, r12
|
||||
; CHECK-ARM-NEXT: movwne r1, #1
|
||||
; CHECK-ARM-NEXT: movne r1, #1
|
||||
; CHECK-ARM-NEXT: ands r3, lr, r1
|
||||
; CHECK-ARM-NEXT: asrne r0, r2, #31
|
||||
; CHECK-ARM-NEXT: mov r1, #-2147483648
|
||||
@ -250,14 +252,18 @@ define signext i16 @func16(i16 signext %x, i16 signext %y) nounwind {
|
||||
; CHECK-ARM-LABEL: func16:
|
||||
; CHECK-ARM: @ %bb.0:
|
||||
; CHECK-ARM-NEXT: sub r0, r0, r1
|
||||
; CHECK-ARM-NEXT: movw r1, #32767
|
||||
; CHECK-ARM-NEXT: mov r1, #255
|
||||
; CHECK-ARM-NEXT: orr r1, r1, #32512
|
||||
; CHECK-ARM-NEXT: cmp r0, r1
|
||||
; CHECK-ARM-NEXT: movlt r1, r0
|
||||
; CHECK-ARM-NEXT: movw r0, #32768
|
||||
; CHECK-ARM-NEXT: movt r0, #65535
|
||||
; CHECK-ARM-NEXT: ldr r0, .LCPI2_0
|
||||
; CHECK-ARM-NEXT: cmn r1, #32768
|
||||
; CHECK-ARM-NEXT: movgt r0, r1
|
||||
; CHECK-ARM-NEXT: bx lr
|
||||
; CHECK-ARM-NEXT: .p2align 2
|
||||
; CHECK-ARM-NEXT: @ %bb.1:
|
||||
; CHECK-ARM-NEXT: .LCPI2_0:
|
||||
; CHECK-ARM-NEXT: .long 4294934528 @ 0xffff8000
|
||||
%tmp = call i16 @llvm.ssub.sat.i16(i16 %x, i16 %y)
|
||||
ret i16 %tmp
|
||||
}
|
||||
@ -509,22 +515,49 @@ define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind {
|
||||
;
|
||||
; CHECK-ARM-LABEL: vec:
|
||||
; CHECK-ARM: @ %bb.0:
|
||||
; CHECK-ARM-NEXT: vmov d17, r2, r3
|
||||
; CHECK-ARM-NEXT: mov r12, sp
|
||||
; CHECK-ARM-NEXT: vld1.64 {d18, d19}, [r12]
|
||||
; CHECK-ARM-NEXT: vmov d16, r0, r1
|
||||
; CHECK-ARM-NEXT: vmvn.i32 q11, #0x80000000
|
||||
; CHECK-ARM-NEXT: vsub.i32 q10, q8, q9
|
||||
; CHECK-ARM-NEXT: vcgt.s32 q9, q9, #0
|
||||
; CHECK-ARM-NEXT: vclt.s32 q12, q10, #0
|
||||
; CHECK-ARM-NEXT: vmvn q13, q12
|
||||
; CHECK-ARM-NEXT: vcgt.s32 q8, q8, q10
|
||||
; CHECK-ARM-NEXT: vbsl q11, q12, q13
|
||||
; CHECK-ARM-NEXT: veor q8, q9, q8
|
||||
; CHECK-ARM-NEXT: vbsl q8, q11, q10
|
||||
; CHECK-ARM-NEXT: vmov r0, r1, d16
|
||||
; CHECK-ARM-NEXT: vmov r2, r3, d17
|
||||
; CHECK-ARM-NEXT: bx lr
|
||||
; CHECK-ARM-NEXT: .save {r4, r5, r6, r7, r11, lr}
|
||||
; CHECK-ARM-NEXT: push {r4, r5, r6, r7, r11, lr}
|
||||
; CHECK-ARM-NEXT: ldr r4, [sp, #24]
|
||||
; CHECK-ARM-NEXT: mov lr, r0
|
||||
; CHECK-ARM-NEXT: ldr r7, [sp, #28]
|
||||
; CHECK-ARM-NEXT: mov r5, #0
|
||||
; CHECK-ARM-NEXT: subs r6, r0, r4
|
||||
; CHECK-ARM-NEXT: mov r0, #0
|
||||
; CHECK-ARM-NEXT: movmi r0, #1
|
||||
; CHECK-ARM-NEXT: cmp r0, #0
|
||||
; CHECK-ARM-NEXT: mov r0, #-2147483648
|
||||
; CHECK-ARM-NEXT: mov r12, #-2147483648
|
||||
; CHECK-ARM-NEXT: mvnne r0, #-2147483648
|
||||
; CHECK-ARM-NEXT: cmp lr, r4
|
||||
; CHECK-ARM-NEXT: movvc r0, r6
|
||||
; CHECK-ARM-NEXT: subs r6, r1, r7
|
||||
; CHECK-ARM-NEXT: mov r4, #0
|
||||
; CHECK-ARM-NEXT: mov lr, #-2147483648
|
||||
; CHECK-ARM-NEXT: movmi r4, #1
|
||||
; CHECK-ARM-NEXT: cmp r4, #0
|
||||
; CHECK-ARM-NEXT: mvnne lr, #-2147483648
|
||||
; CHECK-ARM-NEXT: cmp r1, r7
|
||||
; CHECK-ARM-NEXT: ldr r1, [sp, #32]
|
||||
; CHECK-ARM-NEXT: movvc lr, r6
|
||||
; CHECK-ARM-NEXT: mov r4, #0
|
||||
; CHECK-ARM-NEXT: subs r6, r2, r1
|
||||
; CHECK-ARM-NEXT: movmi r4, #1
|
||||
; CHECK-ARM-NEXT: cmp r4, #0
|
||||
; CHECK-ARM-NEXT: mov r4, #-2147483648
|
||||
; CHECK-ARM-NEXT: mvnne r4, #-2147483648
|
||||
; CHECK-ARM-NEXT: cmp r2, r1
|
||||
; CHECK-ARM-NEXT: ldr r1, [sp, #36]
|
||||
; CHECK-ARM-NEXT: movvc r4, r6
|
||||
; CHECK-ARM-NEXT: subs r2, r3, r1
|
||||
; CHECK-ARM-NEXT: movmi r5, #1
|
||||
; CHECK-ARM-NEXT: cmp r5, #0
|
||||
; CHECK-ARM-NEXT: mvnne r12, #-2147483648
|
||||
; CHECK-ARM-NEXT: cmp r3, r1
|
||||
; CHECK-ARM-NEXT: movvc r12, r2
|
||||
; CHECK-ARM-NEXT: mov r1, lr
|
||||
; CHECK-ARM-NEXT: mov r2, r4
|
||||
; CHECK-ARM-NEXT: mov r3, r12
|
||||
; CHECK-ARM-NEXT: pop {r4, r5, r6, r7, r11, pc}
|
||||
%tmp = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %x, <4 x i32> %y)
|
||||
ret <4 x i32> %tmp
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user