From 6390e091a8fa7e78d7568baae5efad96a255bd2d Mon Sep 17 00:00:00 2001 From: Adrian Prantl Date: Thu, 16 Mar 2017 16:38:22 +0000 Subject: [PATCH] Revert "PR32288: More efficient encoding for DWARF expr subregister access." This reverts commit 2bf453116889a576956892ea9683db4fcd96e30e while investigating buildbot breakage. llvm-svn: 297962 --- lib/CodeGen/AsmPrinter/DwarfExpression.cpp | 31 ++----------------- lib/CodeGen/AsmPrinter/DwarfExpression.h | 7 +---- test/DebugInfo/ARM/s-super-register.ll | 4 ++- test/DebugInfo/X86/PR26148.ll | 2 +- test/DebugInfo/X86/dbg-value-const-byref.ll | 4 +-- .../X86/dbg-value-regmask-clobber.ll | 6 ++-- test/DebugInfo/X86/dw_op_minus_direct.ll | 4 +-- test/DebugInfo/X86/fission-ranges.ll | 8 ++--- test/DebugInfo/X86/single-dbg_value.ll | 4 +-- test/DebugInfo/X86/subreg.ll | 5 ++- test/DebugInfo/X86/subregisters.ll | 6 ++-- 11 files changed, 26 insertions(+), 55 deletions(-) diff --git a/lib/CodeGen/AsmPrinter/DwarfExpression.cpp b/lib/CodeGen/AsmPrinter/DwarfExpression.cpp index caf0bc0f258..43c98442d8b 100644 --- a/lib/CodeGen/AsmPrinter/DwarfExpression.cpp +++ b/lib/CodeGen/AsmPrinter/DwarfExpression.cpp @@ -66,12 +66,6 @@ void DwarfExpression::AddShr(unsigned ShiftBy) { EmitOp(dwarf::DW_OP_shr); } -void DwarfExpression::AddAnd(unsigned Mask) { - EmitOp(dwarf::DW_OP_constu); - EmitUnsigned(Mask); - EmitOp(dwarf::DW_OP_and); -} - bool DwarfExpression::AddMachineRegIndirect(const TargetRegisterInfo &TRI, unsigned MachineReg, int Offset) { if (isFrameRegister(TRI, MachineReg)) { @@ -236,12 +230,6 @@ void DwarfExpression::AddExpression(DIExpressionCursor &&ExprCursor, unsigned FragmentOffsetInBits) { while (ExprCursor) { auto Op = ExprCursor.take(); - - // If we need to mask out a subregister, do it now, unless the next - // operation would emit an OpPiece anyway. - if (SubRegisterSizeInBits && Op->getOp() != dwarf::DW_OP_LLVM_fragment) - maskSubRegister(); - switch (Op->getOp()) { case dwarf::DW_OP_LLVM_fragment: { unsigned SizeInBits = Op->getArg(1); @@ -297,24 +285,9 @@ void DwarfExpression::AddExpression(DIExpressionCursor &&ExprCursor, } } -/// Add masking operations to stencil out a subregister. -void DwarfExpression::maskSubRegister() { - assert(SubRegisterSizeInBits && "no subregister was registered"); - if (SubRegisterOffsetInBits > 0) - AddShr(SubRegisterOffsetInBits); - uint64_t Mask = (1UL << SubRegisterSizeInBits) - 1; - AddAnd(Mask); -} - - void DwarfExpression::finalize() { - // Emit any outstanding DW_OP_piece operations to mask out subregisters. - if (SubRegisterSizeInBits == 0) - return; - // Don't emit a DW_OP_piece for a subregister at offset 0. - if (SubRegisterOffsetInBits == 0) - return; - AddOpPiece(SubRegisterSizeInBits, SubRegisterOffsetInBits); + if (SubRegisterSizeInBits) + AddOpPiece(SubRegisterSizeInBits, SubRegisterOffsetInBits); } void DwarfExpression::addFragmentOffset(const DIExpression *Expr) { diff --git a/lib/CodeGen/AsmPrinter/DwarfExpression.h b/lib/CodeGen/AsmPrinter/DwarfExpression.h index 2f5a701499d..01f66fa7eac 100644 --- a/lib/CodeGen/AsmPrinter/DwarfExpression.h +++ b/lib/CodeGen/AsmPrinter/DwarfExpression.h @@ -99,9 +99,6 @@ protected: SubRegisterOffsetInBits = OffsetInBits; } - /// Add masking operations to stencil out a subregister. - void maskSubRegister(); - public: DwarfExpression(unsigned DwarfVersion) : DwarfVersion(DwarfVersion) {} virtual ~DwarfExpression() {}; @@ -129,10 +126,8 @@ public: /// is at the top of the DWARF stack. void AddOpPiece(unsigned SizeInBits, unsigned OffsetInBits = 0); - /// Emit a shift-right dwarf operation. + /// Emit a shift-right dwarf expression. void AddShr(unsigned ShiftBy); - /// Emit a bitwise and dwarf operation. - void AddAnd(unsigned Mask); /// Emit a DW_OP_stack_value, if supported. /// diff --git a/test/DebugInfo/ARM/s-super-register.ll b/test/DebugInfo/ARM/s-super-register.ll index de0284a9a55..ef2bc9ac1ec 100644 --- a/test/DebugInfo/ARM/s-super-register.ll +++ b/test/DebugInfo/ARM/s-super-register.ll @@ -5,7 +5,9 @@ target triple = "thumbv7-apple-macosx10.6.7" ; The S registers on ARM are expressed as pieces of their super-registers in DWARF. ; ; 0x90 DW_OP_regx of super-register -; CHECK: Location description: 90 +; 0x93 DW_OP_piece +; 0x9d DW_OP_bit_piece +; CHECK: Location description: 90 {{.. .. ((93 ..)|(9d .. ..)) $}} define void @_Z3foov() optsize ssp !dbg !1 { entry: diff --git a/test/DebugInfo/X86/PR26148.ll b/test/DebugInfo/X86/PR26148.ll index 69e7bbd213b..1f66b7599fa 100644 --- a/test/DebugInfo/X86/PR26148.ll +++ b/test/DebugInfo/X86/PR26148.ll @@ -19,7 +19,7 @@ ; AS in 26163, we expect two ranges (as opposed to one), the first one being zero sized ; ; -; CHECK: Beginning address offset: 0x0000000000000004 +; CHECK: 0x00000025: Beginning address offset: 0x0000000000000004 ; CHECK: Ending address offset: 0x0000000000000004 ; CHECK: Location description: 10 03 93 04 55 93 02 ; constu 0x00000003, piece 0x00000004, rdi, piece 0x00000002 diff --git a/test/DebugInfo/X86/dbg-value-const-byref.ll b/test/DebugInfo/X86/dbg-value-const-byref.ll index 77e243702a8..40b9f726f31 100644 --- a/test/DebugInfo/X86/dbg-value-const-byref.ll +++ b/test/DebugInfo/X86/dbg-value-const-byref.ll @@ -34,10 +34,10 @@ ; CHECK: Beginning address offset: [[C1]] ; CHECK: Ending address offset: [[C2:.*]] ; CHECK: Location description: 11 07 -; rax +; rax, piece 0x00000004 ; CHECK: Beginning address offset: [[C2]] ; CHECK: Ending address offset: [[R1:.*]] -; CHECK: Location description: 50 +; CHECK: Location description: 50 93 04 ; rdi+0 ; CHECK: Beginning address offset: [[R1]] ; CHECK: Ending address offset: [[R2:.*]] diff --git a/test/DebugInfo/X86/dbg-value-regmask-clobber.ll b/test/DebugInfo/X86/dbg-value-regmask-clobber.ll index b958f080d02..93543e5ed94 100644 --- a/test/DebugInfo/X86/dbg-value-regmask-clobber.ll +++ b/test/DebugInfo/X86/dbg-value-regmask-clobber.ll @@ -16,8 +16,10 @@ ; ASM: .Ldebug_loc1: ; ASM-NEXT: .quad .Lfunc_begin0-.Lfunc_begin0 ; ASM-NEXT: .quad [[argc_range_end]]-.Lfunc_begin0 -; ASM-NEXT: .short 1 # Loc expr size +; ASM-NEXT: .short 3 # Loc expr size ; ASM-NEXT: .byte 82 # super-register DW_OP_reg2 +; ASM-NEXT: .byte 147 # DW_OP_piece +; ASM-NEXT: .byte 4 # 4 ; argc is the first formal parameter. ; DWARF: .debug_info contents: @@ -28,7 +30,7 @@ ; DWARF: .debug_loc contents: ; DWARF: [[argc_loc_offset]]: Beginning address offset: 0x0000000000000000 ; DWARF-NEXT: Ending address offset: 0x0000000000000013 -; DWARF-NEXT: Location description: 52 +; DWARF-NEXT: Location description: 52 93 04 ; ModuleID = 't.cpp' source_filename = "test/DebugInfo/X86/dbg-value-regmask-clobber.ll" diff --git a/test/DebugInfo/X86/dw_op_minus_direct.ll b/test/DebugInfo/X86/dw_op_minus_direct.ll index 29e07213abb..a84c506b90a 100644 --- a/test/DebugInfo/X86/dw_op_minus_direct.ll +++ b/test/DebugInfo/X86/dw_op_minus_direct.ll @@ -8,8 +8,8 @@ ; CHECK: Beginning address offset: 0x0000000000000000 ; CHECK: Ending address offset: 0x0000000000000004 -; CHECK: Location description: 50 10 ff ff ff ff 0f 1a 10 01 1c -; rax, constu 0xffffffff, and, constu 0x00000001, minus +; CHECK: Location description: 50 10 01 1c 93 04 +; rax, constu 0x00000001, minus, piece 0x00000004 source_filename = "minus.c" target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.12.0" diff --git a/test/DebugInfo/X86/fission-ranges.ll b/test/DebugInfo/X86/fission-ranges.ll index 60d0f1777a4..0dfb13ab66b 100644 --- a/test/DebugInfo/X86/fission-ranges.ll +++ b/test/DebugInfo/X86/fission-ranges.ll @@ -30,16 +30,16 @@ ; CHECK-NEXT: {{^$}} ; CHECK-NEXT: Beginning address index: 3 ; CHECK-NEXT: Length: 25 -; CHECK-NEXT: Location description: 50 +; CHECK-NEXT: Location description: 50 93 04 ; CHECK: [[E]]: Beginning address index: 4 ; CHECK-NEXT: Length: 19 -; CHECK-NEXT: Location description: 50 +; CHECK-NEXT: Location description: 50 93 04 ; CHECK: [[B]]: Beginning address index: 5 ; CHECK-NEXT: Length: 17 -; CHECK-NEXT: Location description: 50 +; CHECK-NEXT: Location description: 50 93 04 ; CHECK: [[D]]: Beginning address index: 6 ; CHECK-NEXT: Length: 17 -; CHECK-NEXT: Location description: 50 +; CHECK-NEXT: Location description: 50 93 04 ; Make sure we don't produce any relocations in any .dwo section (though in particular, debug_info.dwo) ; HDR-NOT: .rela.{{.*}}.dwo diff --git a/test/DebugInfo/X86/single-dbg_value.ll b/test/DebugInfo/X86/single-dbg_value.ll index 7f77e61092d..0275c37d24e 100644 --- a/test/DebugInfo/X86/single-dbg_value.ll +++ b/test/DebugInfo/X86/single-dbg_value.ll @@ -8,8 +8,8 @@ ; CHECK-NEXT: DW_AT_location [DW_FORM_data4] ; CHECK-NEXT: DW_AT_name{{.*}}"a" ; CHECK: .debug_loc contents: -; rax -; CHECK: Location description: 50 +; rax, piece 0x00000004 +; CHECK: Location description: 50 93 04 ; SANITY: DBG_VALUE ; SANITY-NOT: DBG_VALUE ; ModuleID = 'test.ll' diff --git a/test/DebugInfo/X86/subreg.ll b/test/DebugInfo/X86/subreg.ll index 30c672396e4..5e837edfd2b 100644 --- a/test/DebugInfo/X86/subreg.ll +++ b/test/DebugInfo/X86/subreg.ll @@ -4,9 +4,8 @@ ; being in its superregister. ; CHECK: .byte 80 # super-register DW_OP_reg0 -; No need to a piece at offset 0. -; CHECK-NOT: DW_OP_piece -; CHECK-NOT: DW_OP_bit_piece +; CHECK-NEXT: .byte 147 # DW_OP_piece +; CHECK-NEXT: .byte 2 # 2 define i16 @f(i16 signext %zzz) nounwind !dbg !1 { entry: diff --git a/test/DebugInfo/X86/subregisters.ll b/test/DebugInfo/X86/subregisters.ll index 99f7a10e443..d40be0d9e3c 100644 --- a/test/DebugInfo/X86/subregisters.ll +++ b/test/DebugInfo/X86/subregisters.ll @@ -2,7 +2,7 @@ ; RUN: llvm-dwarfdump %t.o | FileCheck %s ; ; Test that on x86_64, the 32-bit subregister esi is emitted as -; subregister of the 64-bit rsi. +; DW_OP_piece 32 of the 64-bit rsi. ; ; rdar://problem/16015314 ; @@ -11,8 +11,8 @@ ; CHECK-NEXT: DW_AT_location [DW_FORM_data4] (0x00000000) ; CHECK-NEXT: DW_AT_name [DW_FORM_strp]{{.*}} "a" ; CHECK: .debug_loc contents: -; rsi -; CHECK: Location description: 54 +; rsi, piece 0x00000004 +; CHECK: Location description: 54 93 04 ; ; struct bar { ; int a;