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[X86] Regenerate double shift tests
llvm-svn: 322444
This commit is contained in:
Simon Pilgrim
parent
ae40514007
commit
63b5238468
@ -1,6 +1,8 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=bdver1 | FileCheck %s
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; Verify that for the architectures that are known to have poor latency
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; double precision shift instructions we generate alternative sequence
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; double precision shift instructions we generate alternative sequence
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; of instructions with lower latencies instead of shld instruction.
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;uint64_t lshift1(uint64_t a, uint64_t b)
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@ -8,11 +10,12 @@
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; return (a << 1) | (b >> 63);
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;}
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; CHECK-LABEL: lshift1:
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; CHECK: shrq $63, %rsi
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; CHECK-NEXT: leaq (%rsi,%rdi,2), %rax
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define i64 @lshift1(i64 %a, i64 %b) nounwind readnone uwtable {
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; CHECK-LABEL: lshift1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: shrq $63, %rsi
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; CHECK-NEXT: leaq (%rsi,%rdi,2), %rax
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; CHECK-NEXT: retq
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entry:
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%shl = shl i64 %a, 1
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%shr = lshr i64 %b, 63
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@ -25,11 +28,12 @@ entry:
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; return (a << 2) | (b >> 62);
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;}
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; CHECK-LABEL: lshift2:
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; CHECK: shrq $62, %rsi
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; CHECK-NEXT: leaq (%rsi,%rdi,4), %rax
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define i64 @lshift2(i64 %a, i64 %b) nounwind readnone uwtable {
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; CHECK-LABEL: lshift2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: shrq $62, %rsi
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; CHECK-NEXT: leaq (%rsi,%rdi,4), %rax
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; CHECK-NEXT: retq
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entry:
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%shl = shl i64 %a, 2
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%shr = lshr i64 %b, 62
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@ -42,12 +46,13 @@ entry:
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; return (a << 7) | (b >> 57);
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;}
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; CHECK: lshift7:
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; CHECK: shlq $7, {{.*}}
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; CHECK-NEXT: shrq $57, {{.*}}
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; CHECK-NEXT: leaq ({{.*}},{{.*}}), {{.*}}
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define i64 @lshift7(i64 %a, i64 %b) nounwind readnone uwtable {
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; CHECK-LABEL: lshift7:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: shlq $7, %rdi
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; CHECK-NEXT: shrq $57, %rsi
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; CHECK-NEXT: leaq (%rsi,%rdi), %rax
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; CHECK-NEXT: retq
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entry:
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%shl = shl i64 %a, 7
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%shr = lshr i64 %b, 57
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@ -60,12 +65,13 @@ entry:
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; return (a << 63) | (b >> 1);
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;}
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; CHECK: lshift63:
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; CHECK: shlq $63, {{.*}}
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; CHECK-NEXT: shrq {{.*}}
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; CHECK-NEXT: leaq ({{.*}},{{.*}}), {{.*}}
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define i64 @lshift63(i64 %a, i64 %b) nounwind readnone uwtable {
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; CHECK-LABEL: lshift63:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: shlq $63, %rdi
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; CHECK-NEXT: shrq %rsi
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; CHECK-NEXT: leaq (%rsi,%rdi), %rax
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; CHECK-NEXT: retq
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entry:
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%shl = shl i64 %a, 63
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%shr = lshr i64 %b, 1
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@ -1,6 +1,8 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=bdver1 | FileCheck %s
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; Verify that for the architectures that are known to have poor latency
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; double precision shift instructions we generate alternative sequence
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; double precision shift instructions we generate alternative sequence
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; of instructions with lower latencies instead of shrd instruction.
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;uint64_t rshift1(uint64_t a, uint64_t b)
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@ -8,12 +10,13 @@
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; return (a >> 1) | (b << 63);
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;}
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; CHECK: rshift1:
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; CHECK: shrq {{.*}}
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; CHECK-NEXT: shlq $63, {{.*}}
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; CHECK-NEXT: leaq ({{.*}},{{.*}}), {{.*}}
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define i64 @rshift1(i64 %a, i64 %b) nounwind readnone uwtable {
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; CHECK-LABEL: rshift1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: shrq %rdi
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; CHECK-NEXT: shlq $63, %rsi
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; CHECK-NEXT: leaq (%rsi,%rdi), %rax
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; CHECK-NEXT: retq
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%1 = lshr i64 %a, 1
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%2 = shl i64 %b, 63
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%3 = or i64 %2, %1
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@ -25,13 +28,13 @@ define i64 @rshift1(i64 %a, i64 %b) nounwind readnone uwtable {
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; return (a >> 2) | (b << 62);
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;}
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; CHECK: rshift2:
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; CHECK: shrq $2, {{.*}}
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; CHECK-NEXT: shlq $62, {{.*}}
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; CHECK-NEXT: leaq ({{.*}},{{.*}}), {{.*}}
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define i64 @rshift2(i64 %a, i64 %b) nounwind readnone uwtable {
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; CHECK-LABEL: rshift2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: shrq $2, %rdi
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; CHECK-NEXT: shlq $62, %rsi
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; CHECK-NEXT: leaq (%rsi,%rdi), %rax
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; CHECK-NEXT: retq
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%1 = lshr i64 %a, 2
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%2 = shl i64 %b, 62
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%3 = or i64 %2, %1
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@ -43,13 +46,13 @@ define i64 @rshift2(i64 %a, i64 %b) nounwind readnone uwtable {
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; return (a >> 7) | (b << 57);
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;}
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; CHECK: rshift7:
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; CHECK: shrq $7, {{.*}}
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; CHECK-NEXT: shlq $57, {{.*}}
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; CHECK-NEXT: leaq ({{.*}},{{.*}}), {{.*}}
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define i64 @rshift7(i64 %a, i64 %b) nounwind readnone uwtable {
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; CHECK-LABEL: rshift7:
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; CHECK: # %bb.0:
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; CHECK-NEXT: shrq $7, %rdi
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; CHECK-NEXT: shlq $57, %rsi
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; CHECK-NEXT: leaq (%rsi,%rdi), %rax
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; CHECK-NEXT: retq
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%1 = lshr i64 %a, 7
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%2 = shl i64 %b, 57
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%3 = or i64 %2, %1
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@ -61,11 +64,12 @@ define i64 @rshift7(i64 %a, i64 %b) nounwind readnone uwtable {
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; return (a >> 63) | (b << 1);
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;}
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; CHECK-LABEL: rshift63:
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; CHECK: shrq $63, %rdi
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; CHECK-NEXT: leaq (%rdi,%rsi,2), %rax
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define i64 @rshift63(i64 %a, i64 %b) nounwind readnone uwtable {
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; CHECK-LABEL: rshift63:
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; CHECK: # %bb.0:
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; CHECK-NEXT: shrq $63, %rdi
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; CHECK-NEXT: leaq (%rdi,%rsi,2), %rax
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; CHECK-NEXT: retq
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%1 = lshr i64 %a, 63
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%2 = shl i64 %b, 1
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%3 = or i64 %2, %1
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@ -1,8 +1,9 @@
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; RUN: llc < %s -mtriple=x86_64-- -mcpu=bdver1 | FileCheck %s
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=bdver1 | FileCheck %s
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; clang -Oz -c test1.cpp -emit-llvm -S -o
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; Verify that we generate shld insruction when we are optimizing for size,
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; even for X86_64 processors that are known to have poor latency double
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; even for X86_64 processors that are known to have poor latency double
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; precision shift instructions.
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; uint64_t lshift10(uint64_t a, uint64_t b)
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; {
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@ -11,8 +12,12 @@
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; Function Attrs: minsize nounwind readnone uwtable
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define i64 @_Z8lshift10mm(i64 %a, i64 %b) #0 {
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; CHECK-LABEL: _Z8lshift10mm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: shldq $10, %rsi, %rdi
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: retq
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entry:
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; CHECK: shldq $10
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%shl = shl i64 %a, 10
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%shr = lshr i64 %b, 54
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%or = or i64 %shr, %shl
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@ -33,8 +38,12 @@ attributes #0 = { minsize nounwind readnone uwtable "less-precise-fpmad"="false"
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; Function Attrs: nounwind optsize readnone uwtable
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define i64 @_Z8lshift11mm(i64 %a, i64 %b) #1 {
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; CHECK-LABEL: _Z8lshift11mm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: shldq $11, %rsi, %rdi
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: retq
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entry:
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; CHECK: shldq $11
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%shl = shl i64 %a, 11
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%shr = lshr i64 %b, 53
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%or = or i64 %shr, %shl
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@ -54,9 +63,13 @@ attributes #1 = { nounwind optsize readnone uwtable "less-precise-fpmad"="false"
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; Function Attrs: nounwind optsize readnone uwtable
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define i64 @_Z8lshift12mm(i64 %a, i64 %b) #2 {
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; CHECK-LABEL: _Z8lshift12mm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: shlq $12, %rdi
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; CHECK-NEXT: shrq $52, %rsi
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; CHECK-NEXT: leaq (%rsi,%rdi), %rax
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; CHECK-NEXT: retq
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entry:
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; CHECK: shlq $12
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; CHECK-NEXT: shrq $52
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%shl = shl i64 %a, 12
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%shr = lshr i64 %b, 52
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%or = or i64 %shr, %shl
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