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https://github.com/RPCS3/llvm-mirror.git
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Implemented aarch64 neon intrinsic vcopy_lane with float type.
llvm-svn: 194041
This commit is contained in:
Kevin Qin
parent
2ca00e3a3d
commit
63fa5c1ef6
@ -3756,9 +3756,12 @@ AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
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// Any value type smaller than i32 is illegal in AArch64, and this lower
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// function is called after legalize pass, so we need to legalize
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// the result here.
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EVT EltVT = MVT::i32;
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if(EltSize == 64)
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EltVT = MVT::i64;
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EVT EltVT;
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if (VT.getVectorElementType().isFloatingPoint())
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EltVT = (EltSize == 64) ? MVT::f64 : MVT::f32;
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else
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EltVT = (EltSize == 64) ? MVT::i64 : MVT::i32;
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PassN = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, ExtV,
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DAG.getConstant(Mask, MVT::i64));
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PassN = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, InsV, PassN,
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@ -5045,19 +5045,12 @@ def INSsw_pattern : Neon_INS_main_pattern<v2i32, v4i32, GPR32, i32,
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def INSdx_pattern : Neon_INS_main_pattern<v1i64, v2i64, GPR64, i64,
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neon_uimm0_bare, INSdx>;
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class NeonI_INS_element<string asmop, string Res, ValueType ResTy,
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Operand ResImm, ValueType MidTy>
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class NeonI_INS_element<string asmop, string Res, Operand ResImm>
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: NeonI_insert<0b1, 0b1,
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(outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn,
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ResImm:$Immd, ResImm:$Immn),
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asmop # "\t$Rd." # Res # "[$Immd], $Rn." # Res # "[$Immn]",
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[(set (ResTy VPR128:$Rd),
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(ResTy (vector_insert
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(ResTy VPR128:$src),
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(MidTy (vector_extract
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(ResTy VPR128:$Rn),
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(ResImm:$Immn))),
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(ResImm:$Immd))))],
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[],
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NoItinerary> {
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let Constraints = "$src = $Rd";
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bits<4> Immd;
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@ -5065,39 +5058,92 @@ class NeonI_INS_element<string asmop, string Res, ValueType ResTy,
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}
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//Insert element (vector, from element)
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def INSELb : NeonI_INS_element<"ins", "b", v16i8, neon_uimm4_bare, i32> {
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def INSELb : NeonI_INS_element<"ins", "b", neon_uimm4_bare> {
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let Inst{20-16} = {Immd{3}, Immd{2}, Immd{1}, Immd{0}, 0b1};
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let Inst{14-11} = {Immn{3}, Immn{2}, Immn{1}, Immn{0}};
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}
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def INSELh : NeonI_INS_element<"ins", "h", v8i16, neon_uimm3_bare, i32> {
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def INSELh : NeonI_INS_element<"ins", "h", neon_uimm3_bare> {
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let Inst{20-16} = {Immd{2}, Immd{1}, Immd{0}, 0b1, 0b0};
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let Inst{14-12} = {Immn{2}, Immn{1}, Immn{0}};
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// bit 11 is unspecified.
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}
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def INSELs : NeonI_INS_element<"ins", "s", v4i32, neon_uimm2_bare, i32> {
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def INSELs : NeonI_INS_element<"ins", "s", neon_uimm2_bare> {
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let Inst{20-16} = {Immd{1}, Immd{0}, 0b1, 0b0, 0b0};
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let Inst{14-13} = {Immn{1}, Immn{0}};
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// bits 11-12 are unspecified.
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}
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def INSELd : NeonI_INS_element<"ins", "d", v2i64, neon_uimm1_bare, i64> {
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def INSELd : NeonI_INS_element<"ins", "d", neon_uimm1_bare> {
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let Inst{20-16} = {Immd, 0b1, 0b0, 0b0, 0b0};
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let Inst{14} = Immn{0};
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// bits 11-13 are unspecified.
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}
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multiclass Neon_INS_elt_pattern<ValueType ResTy, ValueType NaTy,
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ValueType MidTy, Operand StImm, Operand NaImm,
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Instruction INS> {
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def : Pat<(ResTy (vector_insert
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(ResTy VPR128:$src),
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(MidTy (vector_extract
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(ResTy VPR128:$Rn),
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(StImm:$Immn))),
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(StImm:$Immd))),
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(INS (ResTy VPR128:$src), (ResTy VPR128:$Rn),
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StImm:$Immd, StImm:$Immn)>;
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def : Pat <(ResTy (vector_insert
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(ResTy VPR128:$src),
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(MidTy (vector_extract
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(NaTy VPR64:$Rn),
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(NaImm:$Immn))),
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(StImm:$Immd))),
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(INS (ResTy VPR128:$src),
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(ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$Rn), sub_64)),
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StImm:$Immd, NaImm:$Immn)>;
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def : Pat <(NaTy (vector_insert
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(NaTy VPR64:$src),
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(MidTy (vector_extract
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(ResTy VPR128:$Rn),
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(StImm:$Immn))),
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(NaImm:$Immd))),
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(NaTy (EXTRACT_SUBREG
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(ResTy (INS
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(ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
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(ResTy VPR128:$Rn),
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NaImm:$Immd, StImm:$Immn)),
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sub_64))>;
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def : Pat <(NaTy (vector_insert
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(NaTy VPR64:$src),
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(MidTy (vector_extract
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(NaTy VPR64:$Rn),
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(NaImm:$Immn))),
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(NaImm:$Immd))),
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(NaTy (EXTRACT_SUBREG
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(ResTy (INS
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(ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
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(ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$Rn), sub_64)),
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NaImm:$Immd, NaImm:$Immn)),
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sub_64))>;
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}
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defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, neon_uimm2_bare,
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neon_uimm1_bare, INSELs>;
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defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, neon_uimm1_bare,
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neon_uimm0_bare, INSELd>;
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defm : Neon_INS_elt_pattern<v16i8, v8i8, i32, neon_uimm4_bare,
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neon_uimm3_bare, INSELb>;
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defm : Neon_INS_elt_pattern<v8i16, v4i16, i32, neon_uimm3_bare,
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neon_uimm2_bare, INSELh>;
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defm : Neon_INS_elt_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
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neon_uimm1_bare, INSELs>;
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defm : Neon_INS_elt_pattern<v2i64, v1i64, i64, neon_uimm1_bare,
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neon_uimm0_bare, INSELd>;
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multiclass Neon_INS_elt_float_pattern<ValueType ResTy, ValueType NaTy,
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ValueType MidTy,
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RegisterClass OpFPR, Operand ResImm,
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SubRegIndex SubIndex, Instruction INS> {
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def : Pat<(ResTy (vector_insert
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(ResTy VPR128:$src),
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(MidTy (vector_extract
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(ResTy VPR128:$Rn),
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(ResImm:$Immn))),
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(ResImm:$Immd))),
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(INS (ResTy VPR128:$src), (ResTy VPR128:$Rn),
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ResImm:$Immd, ResImm:$Immn)>;
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def : Pat <(ResTy (vector_insert
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(ResTy VPR128:$src),
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(MidTy OpFPR:$Rn),
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@ -5125,60 +5171,6 @@ defm : Neon_INS_elt_float_pattern<v4f32, v2f32, f32, FPR32, neon_uimm2_bare,
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defm : Neon_INS_elt_float_pattern<v2f64, v1f64, f64, FPR64, neon_uimm1_bare,
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sub_64, INSELd>;
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multiclass Neon_INS_elt_pattern <ValueType NaTy, Operand NaImm,
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ValueType MidTy, ValueType StTy,
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Operand StImm, Instruction INS> {
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def : Pat<(NaTy (vector_insert
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(NaTy VPR64:$src),
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(MidTy (vector_extract
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(StTy VPR128:$Rn),
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(StImm:$Immn))),
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(NaImm:$Immd))),
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(NaTy (EXTRACT_SUBREG
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(StTy (INS
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(StTy (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
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(StTy VPR128:$Rn),
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NaImm:$Immd,
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StImm:$Immn)),
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sub_64))>;
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def : Pat<(StTy (vector_insert
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(StTy VPR128:$src),
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(MidTy (vector_extract
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(NaTy VPR64:$Rn),
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(NaImm:$Immn))),
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(StImm:$Immd))),
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(StTy (INS
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(StTy VPR128:$src),
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(StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
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StImm:$Immd,
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NaImm:$Immn))>;
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def : Pat<(NaTy (vector_insert
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(NaTy VPR64:$src),
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(MidTy (vector_extract
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(NaTy VPR64:$Rn),
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(NaImm:$Immn))),
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(NaImm:$Immd))),
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(NaTy (EXTRACT_SUBREG
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(StTy (INS
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(StTy (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
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(StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
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NaImm:$Immd,
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NaImm:$Immn)),
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sub_64))>;
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}
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defm : Neon_INS_elt_pattern<v8i8, neon_uimm3_bare, i32,
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v16i8, neon_uimm4_bare, INSELb>;
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defm : Neon_INS_elt_pattern<v4i16, neon_uimm2_bare, i32,
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v8i16, neon_uimm3_bare, INSELh>;
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defm : Neon_INS_elt_pattern<v2i32, neon_uimm1_bare, i32,
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v4i32, neon_uimm2_bare, INSELs>;
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defm : Neon_INS_elt_pattern<v1i64, neon_uimm0_bare, i64,
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v2i64, neon_uimm1_bare, INSELd>;
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class NeonI_SMOV<string asmop, string Res, bit Q,
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ValueType OpTy, ValueType eleTy,
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Operand OpImm, RegisterClass ResGPR, ValueType ResTy>
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@ -5408,8 +5400,7 @@ def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$src))),
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(f64 FPR64:$src), sub_64)>;
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class NeonI_DUP_Elt<bit Q, string asmop, string rdlane, string rnlane,
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RegisterOperand ResVPR, ValueType ResTy,
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ValueType OpTy, Operand OpImm>
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RegisterOperand ResVPR, Operand OpImm>
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: NeonI_copy<Q, 0b0, 0b0000, (outs ResVPR:$Rd),
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(ins VPR128:$Rn, OpImm:$Imm),
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asmop # "\t$Rd" # rdlane # ", $Rn" # rnlane # "[$Imm]",
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@ -5418,37 +5409,37 @@ class NeonI_DUP_Elt<bit Q, string asmop, string rdlane, string rnlane,
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bits<4> Imm;
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}
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def DUPELT16b : NeonI_DUP_Elt<0b1, "dup", ".16b", ".b", VPR128, v16i8, v16i8,
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def DUPELT16b : NeonI_DUP_Elt<0b1, "dup", ".16b", ".b", VPR128,
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neon_uimm4_bare> {
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let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
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}
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def DUPELT8h : NeonI_DUP_Elt<0b1, "dup", ".8h", ".h", VPR128, v8i16, v8i16,
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def DUPELT8h : NeonI_DUP_Elt<0b1, "dup", ".8h", ".h", VPR128,
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neon_uimm3_bare> {
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let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
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}
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def DUPELT4s : NeonI_DUP_Elt<0b1, "dup", ".4s", ".s", VPR128, v4i32, v4i32,
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def DUPELT4s : NeonI_DUP_Elt<0b1, "dup", ".4s", ".s", VPR128,
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neon_uimm2_bare> {
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let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
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}
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def DUPELT2d : NeonI_DUP_Elt<0b1, "dup", ".2d", ".d", VPR128, v2i64, v2i64,
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def DUPELT2d : NeonI_DUP_Elt<0b1, "dup", ".2d", ".d", VPR128,
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neon_uimm1_bare> {
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let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
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}
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def DUPELT8b : NeonI_DUP_Elt<0b0, "dup", ".8b", ".b", VPR64, v8i8, v16i8,
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def DUPELT8b : NeonI_DUP_Elt<0b0, "dup", ".8b", ".b", VPR64,
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neon_uimm4_bare> {
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let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
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}
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def DUPELT4h : NeonI_DUP_Elt<0b0, "dup", ".4h", ".h", VPR64, v4i16, v8i16,
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def DUPELT4h : NeonI_DUP_Elt<0b0, "dup", ".4h", ".h", VPR64,
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neon_uimm3_bare> {
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let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
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}
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def DUPELT2s : NeonI_DUP_Elt<0b0, "dup", ".2s", ".s", VPR64, v2i32, v4i32,
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def DUPELT2s : NeonI_DUP_Elt<0b0, "dup", ".2s", ".s", VPR64,
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neon_uimm2_bare> {
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let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
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}
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@ -71,6 +71,104 @@ define <2 x i64> @ins2d2(<2 x i64> %tmp1, <2 x i64> %tmp2) {
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ret <2 x i64> %tmp4
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}
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define <4 x float> @ins4f4(<4 x float> %tmp1, <4 x float> %tmp2) {
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;CHECK: ins {{v[0-31]+}}.s[1], {{v[0-31]+}}.s[2]
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%tmp3 = extractelement <4 x float> %tmp1, i32 2
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%tmp4 = insertelement <4 x float> %tmp2, float %tmp3, i32 1
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ret <4 x float> %tmp4
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}
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define <2 x double> @ins2df2(<2 x double> %tmp1, <2 x double> %tmp2) {
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;CHECK: ins {{v[0-31]+}}.d[1], {{v[0-31]+}}.d[0]
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%tmp3 = extractelement <2 x double> %tmp1, i32 0
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%tmp4 = insertelement <2 x double> %tmp2, double %tmp3, i32 1
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ret <2 x double> %tmp4
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}
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define <16 x i8> @ins8b16(<8 x i8> %tmp1, <16 x i8> %tmp2) {
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;CHECK: ins {{v[0-31]+}}.b[15], {{v[0-31]+}}.b[2]
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%tmp3 = extractelement <8 x i8> %tmp1, i32 2
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%tmp4 = insertelement <16 x i8> %tmp2, i8 %tmp3, i32 15
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ret <16 x i8> %tmp4
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}
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define <8 x i16> @ins4h8(<4 x i16> %tmp1, <8 x i16> %tmp2) {
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;CHECK: ins {{v[0-31]+}}.h[7], {{v[0-31]+}}.h[2]
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%tmp3 = extractelement <4 x i16> %tmp1, i32 2
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%tmp4 = insertelement <8 x i16> %tmp2, i16 %tmp3, i32 7
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ret <8 x i16> %tmp4
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}
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define <4 x i32> @ins2s4(<2 x i32> %tmp1, <4 x i32> %tmp2) {
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;CHECK: ins {{v[0-31]+}}.s[1], {{v[0-31]+}}.s[1]
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%tmp3 = extractelement <2 x i32> %tmp1, i32 1
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%tmp4 = insertelement <4 x i32> %tmp2, i32 %tmp3, i32 1
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ret <4 x i32> %tmp4
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}
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define <2 x i64> @ins1d2(<1 x i64> %tmp1, <2 x i64> %tmp2) {
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;CHECK: ins {{v[0-31]+}}.d[1], {{v[0-31]+}}.d[0]
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%tmp3 = extractelement <1 x i64> %tmp1, i32 0
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%tmp4 = insertelement <2 x i64> %tmp2, i64 %tmp3, i32 1
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ret <2 x i64> %tmp4
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}
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define <4 x float> @ins2f4(<2 x float> %tmp1, <4 x float> %tmp2) {
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;CHECK: ins {{v[0-31]+}}.s[1], {{v[0-31]+}}.s[1]
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%tmp3 = extractelement <2 x float> %tmp1, i32 1
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%tmp4 = insertelement <4 x float> %tmp2, float %tmp3, i32 1
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ret <4 x float> %tmp4
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}
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define <2 x double> @ins1f2(<1 x double> %tmp1, <2 x double> %tmp2) {
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;CHECK: ins {{v[0-31]+}}.d[1], {{v[0-31]+}}.d[0]
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%tmp3 = extractelement <1 x double> %tmp1, i32 0
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%tmp4 = insertelement <2 x double> %tmp2, double %tmp3, i32 1
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ret <2 x double> %tmp4
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}
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define <8 x i8> @ins16b8(<16 x i8> %tmp1, <8 x i8> %tmp2) {
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;CHECK: ins {{v[0-31]+}}.b[7], {{v[0-31]+}}.b[2]
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%tmp3 = extractelement <16 x i8> %tmp1, i32 2
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%tmp4 = insertelement <8 x i8> %tmp2, i8 %tmp3, i32 7
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ret <8 x i8> %tmp4
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}
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define <4 x i16> @ins8h4(<8 x i16> %tmp1, <4 x i16> %tmp2) {
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;CHECK: ins {{v[0-31]+}}.h[3], {{v[0-31]+}}.h[2]
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%tmp3 = extractelement <8 x i16> %tmp1, i32 2
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%tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 3
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ret <4 x i16> %tmp4
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}
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define <2 x i32> @ins4s2(<4 x i32> %tmp1, <2 x i32> %tmp2) {
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;CHECK: ins {{v[0-31]+}}.s[1], {{v[0-31]+}}.s[2]
|
||||
%tmp3 = extractelement <4 x i32> %tmp1, i32 2
|
||||
%tmp4 = insertelement <2 x i32> %tmp2, i32 %tmp3, i32 1
|
||||
ret <2 x i32> %tmp4
|
||||
}
|
||||
|
||||
define <1 x i64> @ins2d1(<2 x i64> %tmp1, <1 x i64> %tmp2) {
|
||||
;CHECK: ins {{v[0-31]+}}.d[0], {{v[0-31]+}}.d[0]
|
||||
%tmp3 = extractelement <2 x i64> %tmp1, i32 0
|
||||
%tmp4 = insertelement <1 x i64> %tmp2, i64 %tmp3, i32 0
|
||||
ret <1 x i64> %tmp4
|
||||
}
|
||||
|
||||
define <2 x float> @ins4f2(<4 x float> %tmp1, <2 x float> %tmp2) {
|
||||
;CHECK: ins {{v[0-31]+}}.s[1], {{v[0-31]+}}.s[2]
|
||||
%tmp3 = extractelement <4 x float> %tmp1, i32 2
|
||||
%tmp4 = insertelement <2 x float> %tmp2, float %tmp3, i32 1
|
||||
ret <2 x float> %tmp4
|
||||
}
|
||||
|
||||
define <1 x double> @ins2f1(<2 x double> %tmp1, <1 x double> %tmp2) {
|
||||
;CHECK: ins {{v[0-31]+}}.d[0], {{v[0-31]+}}.d[0]
|
||||
%tmp3 = extractelement <2 x double> %tmp1, i32 0
|
||||
%tmp4 = insertelement <1 x double> %tmp2, double %tmp3, i32 0
|
||||
ret <1 x double> %tmp4
|
||||
}
|
||||
|
||||
define <8 x i8> @ins8b8(<8 x i8> %tmp1, <8 x i8> %tmp2) {
|
||||
;CHECK: ins {{v[0-31]+}}.b[4], {{v[0-31]+}}.b[2]
|
||||
%tmp3 = extractelement <8 x i8> %tmp1, i32 2
|
||||
@ -99,6 +197,20 @@ define <1 x i64> @ins1d1(<1 x i64> %tmp1, <1 x i64> %tmp2) {
|
||||
ret <1 x i64> %tmp4
|
||||
}
|
||||
|
||||
define <2 x float> @ins2f2(<2 x float> %tmp1, <2 x float> %tmp2) {
|
||||
;CHECK: ins {{v[0-31]+}}.s[1], {{v[0-31]+}}.s[0]
|
||||
%tmp3 = extractelement <2 x float> %tmp1, i32 0
|
||||
%tmp4 = insertelement <2 x float> %tmp2, float %tmp3, i32 1
|
||||
ret <2 x float> %tmp4
|
||||
}
|
||||
|
||||
define <1 x double> @ins1df1(<1 x double> %tmp1, <1 x double> %tmp2) {
|
||||
;CHECK: ins {{v[0-31]+}}.d[0], {{v[0-31]+}}.d[0]
|
||||
%tmp3 = extractelement <1 x double> %tmp1, i32 0
|
||||
%tmp4 = insertelement <1 x double> %tmp2, double %tmp3, i32 0
|
||||
ret <1 x double> %tmp4
|
||||
}
|
||||
|
||||
define i32 @umovw16b(<16 x i8> %tmp1) {
|
||||
;CHECK: umov {{w[0-31]+}}, {{v[0-31]+}}.b[8]
|
||||
%tmp3 = extractelement <16 x i8> %tmp1, i32 8
|
||||
|
||||
Loading…
Reference in New Issue
Block a user