From 641730af4af51d868363df40b627caacf413f79e Mon Sep 17 00:00:00 2001 From: Benjamin Kramer Date: Tue, 18 Oct 2016 19:39:31 +0000 Subject: [PATCH] Reduce global namespace pollution. NFC. llvm-svn: 284521 --- lib/LTO/LTOBackend.cpp | 2 +- lib/Support/Host.cpp | 4 ++-- lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp | 5 +++-- lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp | 6 ++++-- lib/Target/X86/X86ISelLowering.cpp | 3 ++- lib/Target/X86/X86InstrFMA3Info.cpp | 1 + lib/Target/X86/X86InstrFMA3Info.h | 4 ++-- 7 files changed, 15 insertions(+), 10 deletions(-) diff --git a/lib/LTO/LTOBackend.cpp b/lib/LTO/LTOBackend.cpp index c2fff4a684a..b00c37f7254 100644 --- a/lib/LTO/LTOBackend.cpp +++ b/lib/LTO/LTOBackend.cpp @@ -41,7 +41,7 @@ using namespace llvm; using namespace lto; -LLVM_ATTRIBUTE_NORETURN void reportOpenError(StringRef Path, Twine Msg) { +LLVM_ATTRIBUTE_NORETURN static void reportOpenError(StringRef Path, Twine Msg) { errs() << "failed to open " << Path << ": " << Msg << '\n'; errs().flush(); exit(1); diff --git a/lib/Support/Host.cpp b/lib/Support/Host.cpp index fa3cd9a0966..e4a9b504a76 100644 --- a/lib/Support/Host.cpp +++ b/lib/Support/Host.cpp @@ -1194,7 +1194,7 @@ StringRef sys::getHostCPUName() { return "generic"; } // On Linux, the number of physical cores can be computed from /proc/cpuinfo, // using the number of unique physical/core id pairs. The following // implementation reads the /proc/cpuinfo format on an x86_64 system. -int computeHostNumPhysicalCores() { +static int computeHostNumPhysicalCores() { // Read /proc/cpuinfo as a stream (until EOF reached). It cannot be // mmapped because it appears to have 0 size. llvm::ErrorOr> Text = @@ -1236,7 +1236,7 @@ int computeHostNumPhysicalCores() { } #else // On other systems, return -1 to indicate unknown. -int computeHostNumPhysicalCores() { return -1; } +static int computeHostNumPhysicalCores() { return -1; } #endif int sys::getHostNumPhysicalCores() { diff --git a/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp b/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp index c93ac60e896..82ef48e216e 100644 --- a/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp +++ b/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp @@ -47,8 +47,9 @@ LanaiDisassembler::LanaiDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) // Forward declare because the autogenerated code will reference this. // Definition is further down. -DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); +static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); static DecodeStatus decodeRiMemoryValue(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); diff --git a/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp b/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp index f53bfed7fa6..c2f8c0f7ad5 100644 --- a/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp +++ b/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp @@ -73,11 +73,12 @@ static MCInstPrinter *createLanaiMCInstPrinter(const Triple & /*T*/, return 0; } -MCRelocationInfo *createLanaiElfRelocation(const Triple &TheTriple, - MCContext &Ctx) { +static MCRelocationInfo *createLanaiElfRelocation(const Triple &TheTriple, + MCContext &Ctx) { return createMCRelocationInfo(TheTriple, Ctx); } +namespace { class LanaiMCInstrAnalysis : public MCInstrAnalysis { public: explicit LanaiMCInstrAnalysis(const MCInstrInfo *Info) @@ -106,6 +107,7 @@ public: } } }; +} // end anonymous namespace static MCInstrAnalysis *createLanaiInstrAnalysis(const MCInstrInfo *Info) { return new LanaiMCInstrAnalysis(Info); diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index c1b6a2204cd..3fa7db24380 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -29151,7 +29151,8 @@ static SDValue combineLogicBlendIntoPBLENDV(SDNode *N, SelectionDAG &DAG, // into: // srl(ctlz x), log2(bitsize(x)) // Input pattern is checked by caller. -SDValue lowerX86CmpEqZeroToCtlzSrl(SDValue Op, EVT ExtTy, SelectionDAG &DAG) { +static SDValue lowerX86CmpEqZeroToCtlzSrl(SDValue Op, EVT ExtTy, + SelectionDAG &DAG) { SDValue Cmp = Op.getOperand(1); EVT VT = Cmp.getOperand(0).getValueType(); unsigned Log2b = Log2_32(VT.getSizeInBits()); diff --git a/lib/Target/X86/X86InstrFMA3Info.cpp b/lib/Target/X86/X86InstrFMA3Info.cpp index 7bd8415e9e4..db83497ee69 100644 --- a/lib/Target/X86/X86InstrFMA3Info.cpp +++ b/lib/Target/X86/X86InstrFMA3Info.cpp @@ -16,6 +16,7 @@ #include "X86InstrInfo.h" #include "llvm/Support/ManagedStatic.h" #include "llvm/Support/Threading.h" +using namespace llvm; /// This flag is used in the method llvm::call_once() used below to make the /// initialization of the map 'OpcodeToGroup' thread safe. diff --git a/lib/Target/X86/X86InstrFMA3Info.h b/lib/Target/X86/X86InstrFMA3Info.h index 987ff9e30e5..025cee3b2b9 100644 --- a/lib/Target/X86/X86InstrFMA3Info.h +++ b/lib/Target/X86/X86InstrFMA3Info.h @@ -20,8 +20,7 @@ #include #include -using namespace llvm; - +namespace llvm { /// This class is used to group {132, 213, 231} forms of FMA opcodes together. /// Each of the groups has either 3 register opcodes, 3 memory opcodes, /// or 6 register and memory opcodes. Also, each group has an attrubutes field @@ -311,5 +310,6 @@ public: return rm_iterator(getX86InstrFMA3Info()->OpcodeToGroup.end()); } }; +} // namespace llvm #endif