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[X86] Fix SQRTSS/SQRTSD/RCPSS/RCPSD intrinsics to use sse_load_f32/sse_load_f64 to increase load folding opportunities.
llvm-svn: 318016
This commit is contained in:
Craig Topper
parent
a400aaf166
commit
64463b58e5
@ -7588,11 +7588,10 @@ multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
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(_.VT _.RC:$src2),
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(i32 FROUND_CURRENT))>;
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defm m_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
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(ins _.RC:$src1, _.IntScalarMemOp:$src2), OpcodeStr,
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"$src2, $src1", "$src1, $src2",
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(X86fsqrtRnds (_.VT _.RC:$src1),
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(_.VT (scalar_to_vector
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(_.ScalarLdFrag addr:$src2))),
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_.ScalarIntMemCPat:$src2,
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(i32 FROUND_CURRENT))>;
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defm rb_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
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@ -7630,7 +7629,7 @@ let Predicates = [HasAVX512, OptForSize] in {
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(!cast<Instruction>(NAME#SUFF#Zm)
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(_.EltVT (IMPLICIT_DEF)), addr:$src)>;
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def : Pat<(Intr (scalar_to_vector (_.EltVT (load addr:$src2)))),
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def : Pat<(Intr _.ScalarIntMemCPat:$src2),
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(!cast<Instruction>(NAME#SUFF#Zm_Int)
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(_.VT (IMPLICIT_DEF)), addr:$src2)>;
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}
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@ -3040,6 +3040,7 @@ def SSE_RCPS : OpndItins<
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multiclass sse_fp_unop_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
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ValueType vt, ValueType ScalarVT,
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X86MemOperand x86memop,
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Operand intmemop, ComplexPattern int_cpat,
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Intrinsic Intr,
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SDNode OpNode, Domain d, OpndItins itins,
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Predicate target, string Suffix> {
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@ -3060,7 +3061,7 @@ multiclass sse_fp_unop_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[]>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
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let mayLoad = 1 in
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def m_Int : I<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, x86memop:$src2),
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def m_Int : I<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, intmemop:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[]>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
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}
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@ -3080,7 +3081,7 @@ multiclass sse_fp_unop_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
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// which has a clobber before the rcp, vs.
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// rcpss mem, %xmm0
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let Predicates = [target, OptForSize] in {
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def : Pat<(Intr (scalar_to_vector (ScalarVT (load addr:$src2)))),
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def : Pat<(Intr int_cpat:$src2),
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(!cast<Instruction>(NAME#Suffix##m_Int)
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(vt (IMPLICIT_DEF)), addr:$src2)>;
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}
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@ -3089,6 +3090,7 @@ multiclass sse_fp_unop_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
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multiclass avx_fp_unop_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
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ValueType vt, ValueType ScalarVT,
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X86MemOperand x86memop,
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Operand intmemop, ComplexPattern int_cpat,
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Intrinsic Intr, SDNode OpNode, Domain d,
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OpndItins itins, Predicate target, string Suffix> {
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let hasSideEffects = 0 in {
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@ -3106,7 +3108,7 @@ multiclass avx_fp_unop_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
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[]>, Sched<[itins.Sched.Folded]>;
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let mayLoad = 1 in
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def m_Int : I<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, x86memop:$src2),
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(ins VR128:$src1, intmemop:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
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}
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@ -3129,7 +3131,7 @@ multiclass avx_fp_unop_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
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VR128:$src)>;
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}
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let Predicates = [target, OptForSize] in {
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def : Pat<(Intr (scalar_to_vector (ScalarVT (load addr:$src2)))),
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def : Pat<(Intr int_cpat:$src2),
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(!cast<Instruction>("V"#NAME#Suffix##m_Int)
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(vt (IMPLICIT_DEF)), addr:$src2)>;
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def : Pat<(ScalarVT (OpNode (load addr:$src))),
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@ -3213,10 +3215,11 @@ let Predicates = [HasAVX, NoVLX] in {
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multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
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OpndItins itins, Predicate AVXTarget> {
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defm SS : sse_fp_unop_s<opc, OpcodeStr##ss, FR32, v4f32, f32, f32mem,
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ssmem, sse_load_f32,
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!cast<Intrinsic>("int_x86_sse_"##OpcodeStr##_ss), OpNode,
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SSEPackedSingle, itins, UseSSE1, "SS">, XS;
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defm V#NAME#SS : avx_fp_unop_s<opc, "v"#OpcodeStr##ss, FR32, v4f32, f32,
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f32mem,
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f32mem, ssmem, sse_load_f32,
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!cast<Intrinsic>("int_x86_sse_"##OpcodeStr##_ss), OpNode,
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SSEPackedSingle, itins, AVXTarget, "SS">, XS, VEX_4V,
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VEX_LIG, VEX_WIG, NotMemoryFoldable;
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@ -3225,10 +3228,11 @@ multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
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multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
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OpndItins itins, Predicate AVXTarget> {
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defm SD : sse_fp_unop_s<opc, OpcodeStr##sd, FR64, v2f64, f64, f64mem,
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sdmem, sse_load_f64,
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!cast<Intrinsic>("int_x86_sse2_"##OpcodeStr##_sd),
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OpNode, SSEPackedDouble, itins, UseSSE2, "SD">, XD;
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defm V#NAME#SD : avx_fp_unop_s<opc, "v"#OpcodeStr##sd, FR64, v2f64, f64,
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f64mem,
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f64mem, sdmem, sse_load_f64,
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!cast<Intrinsic>("int_x86_sse2_"##OpcodeStr##_sd),
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OpNode, SSEPackedDouble, itins, AVXTarget, "SD">,
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XD, VEX_4V, VEX_LIG, VEX_WIG, NotMemoryFoldable;
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@ -101,14 +101,12 @@ define float @rcpss_size(float* %a) optsize {
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define <4 x float> @rcpss_full_size(<4 x float>* %a) optsize {
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; SSE-LABEL: rcpss_full_size:
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; SSE: # BB#0:
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; SSE-NEXT: movaps (%rdi), %xmm0
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; SSE-NEXT: rcpss %xmm0, %xmm0
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; SSE-NEXT: rcpss (%rdi), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: rcpss_full_size:
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; AVX: # BB#0:
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; AVX-NEXT: vmovaps (%rdi), %xmm0
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; AVX-NEXT: vrcpss %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vrcpss (%rdi), %xmm0, %xmm0
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; AVX-NEXT: retq
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%ld = load <4 x float>, <4 x float>* %a
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%res = tail call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %ld)
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@ -135,14 +133,12 @@ define float @rsqrtss_size(float* %a) optsize {
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define <4 x float> @rsqrtss_full_size(<4 x float>* %a) optsize {
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; SSE-LABEL: rsqrtss_full_size:
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; SSE: # BB#0:
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; SSE-NEXT: movaps (%rdi), %xmm0
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; SSE-NEXT: rsqrtss %xmm0, %xmm0
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; SSE-NEXT: rsqrtss (%rdi), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: rsqrtss_full_size:
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; AVX: # BB#0:
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; AVX-NEXT: vmovaps (%rdi), %xmm0
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; AVX-NEXT: vrsqrtss %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vrsqrtss (%rdi), %xmm0, %xmm0
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; AVX-NEXT: retq
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%ld = load <4 x float>, <4 x float>* %a
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%res = tail call <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float> %ld)
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@ -169,14 +165,12 @@ define float @sqrtss_size(float* %a) optsize{
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define <4 x float> @sqrtss_full_size(<4 x float>* %a) optsize{
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; SSE-LABEL: sqrtss_full_size:
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; SSE: # BB#0:
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; SSE-NEXT: movaps (%rdi), %xmm0
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; SSE-NEXT: sqrtss %xmm0, %xmm0
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; SSE-NEXT: sqrtss (%rdi), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: sqrtss_full_size:
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; AVX: # BB#0:
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; AVX-NEXT: vmovaps (%rdi), %xmm0
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; AVX-NEXT: vsqrtss %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vsqrtss (%rdi), %xmm0, %xmm0
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; AVX-NEXT: retq
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%ld = load <4 x float>, <4 x float>* %a
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%res = tail call <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float> %ld)
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@ -203,14 +197,12 @@ define double @sqrtsd_size(double* %a) optsize {
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define <2 x double> @sqrtsd_full_size(<2 x double>* %a) optsize {
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; SSE-LABEL: sqrtsd_full_size:
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; SSE: # BB#0:
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; SSE-NEXT: movapd (%rdi), %xmm0
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; SSE-NEXT: sqrtsd %xmm0, %xmm0
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; SSE-NEXT: sqrtsd (%rdi), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: sqrtsd_full_size:
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; AVX: # BB#0:
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; AVX-NEXT: vmovapd (%rdi), %xmm0
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; AVX-NEXT: vsqrtsd %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vsqrtsd (%rdi), %xmm0, %xmm0
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; AVX-NEXT: retq
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%ld = load <2 x double>, <2 x double>* %a
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%res = tail call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %ld)
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