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One more spot where the new arm mode LDR instruction representation

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doesn't need the additional addrmode2 register operand. Missed it the first
time around.

llvm-svn: 117421
This commit is contained in:
Jim Grosbach 2010-10-27 00:38:16 +00:00
parent 854507453a
commit 6453c7cdf9
1 changed files with 3 additions and 3 deletions
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6
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
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@ -860,7 +860,9 @@ static void InsertLDR_STR(MachineBasicBlock &MBB,
ARMCC::CondCodes Pred, unsigned PredReg,
const TargetInstrInfo *TII, bool isT2) {
int Offset = OffImm;
if (!isT2) {
// FIXME: This fancy offset encoding stuff goes away when we're done
// removing addrmode2.
if (!isT2 && !isDef) {
if (OffImm < 0)
Offset = ARM_AM::getAM2Opc(ARM_AM::sub, -OffImm, ARM_AM::no_shift);
else
@ -871,8 +873,6 @@ static void InsertLDR_STR(MachineBasicBlock &MBB,
TII->get(NewOpc))
.addReg(Reg, getDefRegState(true) | getDeadRegState(RegDeadKill))
.addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));
if (!isT2)
MIB.addReg(OffReg, getKillRegState(OffKill)|getUndefRegState(OffUndef));
MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
} else {
MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MBBI->getDebugLoc(),