RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-01-31 20:51:52 +01:00
Code Issues Projects Releases Wiki Activity

Fix typo in CodeGenerator doc

Browse Source 
llvm-svn: 167137
This commit is contained in:
Eli Bendersky 2012-10-31 16:41:07 +00:00
parent ed81d2236e
commit 6454200600
1 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
docs/CodeGenerator.rst
View File

@ -256,10 +256,10 @@ The ``TargetRegisterInfo`` class
The ``TargetRegisterInfo`` class is used to describe the register file of the
target and any interactions between the registers.
Registers in the code generator are represented in the code generator by
unsigned integers. Physical registers (those that actually exist in the target
description) are unique small numbers, and virtual registers are generally
large. Note that register ``#0`` is reserved as a flag value.
Registers are represented in the code generator by unsigned integers. Physical
registers (those that actually exist in the target description) are unique
small numbers, and virtual registers are generally large. Note that
register ``#0`` is reserved as a flag value.
Each register in the processor description has an associated
``TargetRegisterDesc`` entry, which provides a textual name for the register