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[PowerPC]: e500 target can't use lwsync, use msync instead

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The e500 core has a silicon bug that triggers an illegal instruction
program trap on any sync other than msync.  Other cores will typically
ignore illegal sync types, and the documentation even implies that the
'illegal' bits are ignored.

Address this hardware deficiency by only using msync, like the PPC440.

Differential Revision:  https://reviews.llvm.org/D76614
This commit is contained in:
Justin Hibbits 2020-03-23 09:44:39 -05:00
parent d31a976026
commit 6457993f9d
2 changed files with 2 additions and 1 deletions
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2
lib/Target/PowerPC/PPC.td
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@ -463,7 +463,7 @@ def : ProcessorModel<"g5", G5Model,
def : ProcessorModel<"e500", PPCE500Model,
[DirectiveE500,
FeatureICBT, FeatureBookE,
FeatureISEL, FeatureMFTB, FeatureSPE]>;
FeatureISEL, FeatureMFTB, FeatureMSYNC, FeatureSPE]>;
def : ProcessorModel<"e500mc", PPCE500mcModel,
[DirectiveE500mc,
FeatureSTFIWX, FeatureICBT, FeatureBookE,

1
test/CodeGen/PowerPC/atomics-fences.ll
View File

@ -1,6 +1,7 @@
; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -mcpu=440 | FileCheck %s --check-prefix=PPC440
; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -mcpu=e500 | FileCheck %s --check-prefix=PPC440
; Fences
define void @fence_acquire() {