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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-22 10:42:39 +01:00

Add more const qualifiers for LLVM IR pointers in CodeGen.

llvm-svn: 101342
This commit is contained in:
Dan Gohman 2010-04-15 04:33:49 +00:00
parent 553267e9cc
commit 64a84ceb3f
9 changed files with 30 additions and 28 deletions

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@ -70,7 +70,7 @@ struct MachineFunctionInfo {
};
class MachineFunction {
Function *Fn;
const Function *Fn;
const TargetMachine &Target;
MCContext &Ctx;
MachineModuleInfo &MMI;
@ -124,8 +124,8 @@ class MachineFunction {
MachineFunction(const MachineFunction &); // DO NOT IMPLEMENT
void operator=(const MachineFunction&); // DO NOT IMPLEMENT
public:
MachineFunction(Function *Fn, const TargetMachine &TM, unsigned FunctionNum,
MachineModuleInfo &MMI);
MachineFunction(const Function *Fn, const TargetMachine &TM,
unsigned FunctionNum, MachineModuleInfo &MMI);
~MachineFunction();
MachineModuleInfo &getMMI() const { return MMI; }
@ -133,7 +133,7 @@ public:
/// getFunction - Return the LLVM function that this machine code represents
///
Function *getFunction() const { return Fn; }
const Function *getFunction() const { return Fn; }
/// getFunctionNumber - Return a unique ID for the current function.
///

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@ -208,7 +208,7 @@ ELFSection &ELFWriter::getDtorSection() {
}
// getTextSection - Get the text section for the specified function
ELFSection &ELFWriter::getTextSection(Function *F) {
ELFSection &ELFWriter::getTextSection(const Function *F) {
const MCSectionELF *Text =
(const MCSectionELF *)TLOF.SectionForGlobal(F, Mang, TM);
return getSection(Text->getSectionName(), Text->getType(), Text->getFlags());

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@ -191,7 +191,7 @@ namespace llvm {
ELFSection &getDtorSection();
ELFSection &getJumpTableSection();
ELFSection &getConstantPoolSection(MachineConstantPoolEntry &CPE);
ELFSection &getTextSection(Function *F);
ELFSection &getTextSection(const Function *F);
ELFSection &getRelocSection(ELFSection &S);
// Helpers for obtaining ELF specific info.

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@ -51,7 +51,7 @@ void ilist_traits<MachineBasicBlock>::deleteNode(MachineBasicBlock *MBB) {
MBB->getParent()->DeleteMachineBasicBlock(MBB);
}
MachineFunction::MachineFunction(Function *F, const TargetMachine &TM,
MachineFunction::MachineFunction(const Function *F, const TargetMachine &TM,
unsigned FunctionNum, MachineModuleInfo &mmi)
: Fn(F), Target(TM), Ctx(mmi.getContext()), MMI(mmi) {
if (TM.getRegisterInfo())

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@ -123,10 +123,11 @@ void llvm::ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
/// PHI nodes or outside of the basic block that defines it, or used by a
/// switch or atomic instruction, which may expand to multiple basic blocks.
static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
static bool isUsedOutsideOfDefiningBlock(const Instruction *I) {
if (isa<PHINode>(I)) return true;
BasicBlock *BB = I->getParent();
for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
const BasicBlock *BB = I->getParent();
for (Value::const_use_iterator UI = I->use_begin(), E = I->use_end();
UI != E; ++UI)
if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI))
return true;
return false;
@ -135,7 +136,7 @@ static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
/// isOnlyUsedInEntryBlock - If the specified argument is only used in the
/// entry block, return true. This includes arguments used by switches, since
/// the switch may expand into multiple basic blocks.
static bool isOnlyUsedInEntryBlock(Argument *A, bool EnableFastISel) {
static bool isOnlyUsedInEntryBlock(const Argument *A, bool EnableFastISel) {
// With FastISel active, we may be splitting blocks, so force creation
// of virtual registers for all non-dead arguments.
// Don't force virtual registers for byval arguments though, because
@ -143,8 +144,9 @@ static bool isOnlyUsedInEntryBlock(Argument *A, bool EnableFastISel) {
if (EnableFastISel && !A->hasByValAttr())
return A->use_empty();
BasicBlock *Entry = A->getParent()->begin();
for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
const BasicBlock *Entry = A->getParent()->begin();
for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end();
UI != E; ++UI)
if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
return false; // Use not in entry block.
return true;
@ -154,7 +156,7 @@ FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli)
: TLI(tli) {
}
void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf,
void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
bool EnableFastISel) {
Fn = &fn;
MF = &mf;
@ -162,7 +164,7 @@ void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf,
// Create a vreg for each argument register that is not dead and is used
// outside of the entry block for the function.
for (Function::arg_iterator AI = Fn->arg_begin(), E = Fn->arg_end();
for (Function::const_arg_iterator AI = Fn->arg_begin(), E = Fn->arg_end();
AI != E; ++AI)
if (!isOnlyUsedInEntryBlock(AI, EnableFastISel))
InitializeRegForValue(AI);
@ -170,10 +172,10 @@ void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf,
// Initialize the mapping of values to registers. This is only set up for
// instruction values that are used outside of the block that defines
// them.
Function::iterator BB = Fn->begin(), EB = Fn->end();
for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
Function::const_iterator BB = Fn->begin(), EB = Fn->end();
for (BasicBlock::const_iterator I = BB->begin(), E = BB->end(); I != E; ++I)
if (const AllocaInst *AI = dyn_cast<AllocaInst>(I))
if (const ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
const Type *Ty = AI->getAllocatedType();
uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
unsigned Align =
@ -187,7 +189,7 @@ void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf,
}
for (; BB != EB; ++BB)
for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
for (BasicBlock::const_iterator I = BB->begin(), E = BB->end(); I != E; ++I)
if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
if (!isa<AllocaInst>(I) ||
!StaticAllocaMap.count(cast<AllocaInst>(I)))
@ -209,9 +211,9 @@ void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf,
// Create Machine PHI nodes for LLVM PHI nodes, lowering them as
// appropriate.
PHINode *PN;
const PHINode *PN;
DebugLoc DL;
for (BasicBlock::iterator
for (BasicBlock::const_iterator
I = BB->begin(), E = BB->end(); I != E; ++I) {
PN = dyn_cast<PHINode>(I);
@ -235,7 +237,7 @@ void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf,
// Mark landing pad blocks.
for (BB = Fn->begin(); BB != EB; ++BB)
if (InvokeInst *Invoke = dyn_cast<InvokeInst>(BB->getTerminator()))
if (const InvokeInst *Invoke = dyn_cast<InvokeInst>(BB->getTerminator()))
MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
}

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@ -48,7 +48,7 @@ class Value;
class FunctionLoweringInfo {
public:
TargetLowering &TLI;
Function *Fn;
const Function *Fn;
MachineFunction *MF;
MachineRegisterInfo *RegInfo;
@ -93,7 +93,7 @@ public:
/// set - Initialize this FunctionLoweringInfo with the given Function
/// and its associated MachineFunction.
///
void set(Function &Fn, MachineFunction &MF, bool EnableFastISel);
void set(const Function &Fn, MachineFunction &MF, bool EnableFastISel);
/// clear - Clear out all the function-specific state. This returns this
/// FunctionLoweringInfo to an empty state, ready to be used for a

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@ -3610,7 +3610,7 @@ static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS,
if (Val == 0)
return DAG.getConstantFP(1.0, LHS.getValueType());
Function *F = DAG.getMachineFunction().getFunction();
const Function *F = DAG.getMachineFunction().getFunction();
if (!F->hasFnAttr(Attribute::OptimizeForSize) ||
// If optimizing for size, don't insert too many multiplies. This
// inserts up to 5 multiplies.

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@ -195,7 +195,7 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
assert((!EnableFastISelAbort || EnableFastISel) &&
"-fast-isel-abort requires -fast-isel");
Function &Fn = *mf.getFunction();
const Function &Fn = *mf.getFunction();
const TargetInstrInfo &TII = *TM.getInstrInfo();
const TargetRegisterInfo &TRI = *TM.getRegisterInfo();

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@ -1358,7 +1358,7 @@ ARMPreAllocLoadStoreOpt::CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1,
return false;
unsigned Align = (*Op0->memoperands_begin())->getAlignment();
Function *Func = MF->getFunction();
const Function *Func = MF->getFunction();
unsigned ReqAlign = STI->hasV6Ops()
? TD->getPrefTypeAlignment(Type::getInt64Ty(Func->getContext()))
: 8; // Pre-v6 need 8-byte align