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Add more const qualifiers for LLVM IR pointers in CodeGen.
llvm-svn: 101342
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553267e9cc
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@ -70,7 +70,7 @@ struct MachineFunctionInfo {
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};
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class MachineFunction {
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Function *Fn;
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const Function *Fn;
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const TargetMachine &Target;
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MCContext &Ctx;
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MachineModuleInfo &MMI;
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@ -124,8 +124,8 @@ class MachineFunction {
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MachineFunction(const MachineFunction &); // DO NOT IMPLEMENT
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void operator=(const MachineFunction&); // DO NOT IMPLEMENT
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public:
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MachineFunction(Function *Fn, const TargetMachine &TM, unsigned FunctionNum,
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MachineModuleInfo &MMI);
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MachineFunction(const Function *Fn, const TargetMachine &TM,
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unsigned FunctionNum, MachineModuleInfo &MMI);
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~MachineFunction();
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MachineModuleInfo &getMMI() const { return MMI; }
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@ -133,7 +133,7 @@ public:
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/// getFunction - Return the LLVM function that this machine code represents
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///
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Function *getFunction() const { return Fn; }
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const Function *getFunction() const { return Fn; }
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/// getFunctionNumber - Return a unique ID for the current function.
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///
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@ -208,7 +208,7 @@ ELFSection &ELFWriter::getDtorSection() {
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}
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// getTextSection - Get the text section for the specified function
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ELFSection &ELFWriter::getTextSection(Function *F) {
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ELFSection &ELFWriter::getTextSection(const Function *F) {
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const MCSectionELF *Text =
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(const MCSectionELF *)TLOF.SectionForGlobal(F, Mang, TM);
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return getSection(Text->getSectionName(), Text->getType(), Text->getFlags());
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@ -191,7 +191,7 @@ namespace llvm {
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ELFSection &getDtorSection();
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ELFSection &getJumpTableSection();
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ELFSection &getConstantPoolSection(MachineConstantPoolEntry &CPE);
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ELFSection &getTextSection(Function *F);
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ELFSection &getTextSection(const Function *F);
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ELFSection &getRelocSection(ELFSection &S);
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// Helpers for obtaining ELF specific info.
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@ -51,7 +51,7 @@ void ilist_traits<MachineBasicBlock>::deleteNode(MachineBasicBlock *MBB) {
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MBB->getParent()->DeleteMachineBasicBlock(MBB);
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}
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MachineFunction::MachineFunction(Function *F, const TargetMachine &TM,
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MachineFunction::MachineFunction(const Function *F, const TargetMachine &TM,
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unsigned FunctionNum, MachineModuleInfo &mmi)
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: Fn(F), Target(TM), Ctx(mmi.getContext()), MMI(mmi) {
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if (TM.getRegisterInfo())
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@ -123,10 +123,11 @@ void llvm::ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
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/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
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/// PHI nodes or outside of the basic block that defines it, or used by a
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/// switch or atomic instruction, which may expand to multiple basic blocks.
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static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
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static bool isUsedOutsideOfDefiningBlock(const Instruction *I) {
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if (isa<PHINode>(I)) return true;
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BasicBlock *BB = I->getParent();
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for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
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const BasicBlock *BB = I->getParent();
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for (Value::const_use_iterator UI = I->use_begin(), E = I->use_end();
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UI != E; ++UI)
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if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI))
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return true;
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return false;
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@ -135,7 +136,7 @@ static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
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/// isOnlyUsedInEntryBlock - If the specified argument is only used in the
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/// entry block, return true. This includes arguments used by switches, since
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/// the switch may expand into multiple basic blocks.
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static bool isOnlyUsedInEntryBlock(Argument *A, bool EnableFastISel) {
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static bool isOnlyUsedInEntryBlock(const Argument *A, bool EnableFastISel) {
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// With FastISel active, we may be splitting blocks, so force creation
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// of virtual registers for all non-dead arguments.
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// Don't force virtual registers for byval arguments though, because
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@ -143,8 +144,9 @@ static bool isOnlyUsedInEntryBlock(Argument *A, bool EnableFastISel) {
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if (EnableFastISel && !A->hasByValAttr())
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return A->use_empty();
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BasicBlock *Entry = A->getParent()->begin();
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for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
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const BasicBlock *Entry = A->getParent()->begin();
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for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end();
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UI != E; ++UI)
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if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
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return false; // Use not in entry block.
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return true;
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@ -154,7 +156,7 @@ FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli)
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: TLI(tli) {
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}
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void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf,
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void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
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bool EnableFastISel) {
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Fn = &fn;
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MF = &mf;
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@ -162,7 +164,7 @@ void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf,
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// Create a vreg for each argument register that is not dead and is used
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// outside of the entry block for the function.
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for (Function::arg_iterator AI = Fn->arg_begin(), E = Fn->arg_end();
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for (Function::const_arg_iterator AI = Fn->arg_begin(), E = Fn->arg_end();
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AI != E; ++AI)
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if (!isOnlyUsedInEntryBlock(AI, EnableFastISel))
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InitializeRegForValue(AI);
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@ -170,10 +172,10 @@ void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf,
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// Initialize the mapping of values to registers. This is only set up for
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// instruction values that are used outside of the block that defines
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// them.
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Function::iterator BB = Fn->begin(), EB = Fn->end();
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for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
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if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
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if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
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Function::const_iterator BB = Fn->begin(), EB = Fn->end();
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for (BasicBlock::const_iterator I = BB->begin(), E = BB->end(); I != E; ++I)
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if (const AllocaInst *AI = dyn_cast<AllocaInst>(I))
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if (const ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
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const Type *Ty = AI->getAllocatedType();
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uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
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unsigned Align =
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@ -187,7 +189,7 @@ void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf,
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}
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for (; BB != EB; ++BB)
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for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
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for (BasicBlock::const_iterator I = BB->begin(), E = BB->end(); I != E; ++I)
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if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
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if (!isa<AllocaInst>(I) ||
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!StaticAllocaMap.count(cast<AllocaInst>(I)))
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@ -209,9 +211,9 @@ void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf,
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// Create Machine PHI nodes for LLVM PHI nodes, lowering them as
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// appropriate.
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PHINode *PN;
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const PHINode *PN;
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DebugLoc DL;
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for (BasicBlock::iterator
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for (BasicBlock::const_iterator
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I = BB->begin(), E = BB->end(); I != E; ++I) {
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PN = dyn_cast<PHINode>(I);
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@ -235,7 +237,7 @@ void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf,
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// Mark landing pad blocks.
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for (BB = Fn->begin(); BB != EB; ++BB)
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if (InvokeInst *Invoke = dyn_cast<InvokeInst>(BB->getTerminator()))
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if (const InvokeInst *Invoke = dyn_cast<InvokeInst>(BB->getTerminator()))
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MBBMap[Invoke->getSuccessor(1)]->setIsLandingPad();
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}
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@ -48,7 +48,7 @@ class Value;
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class FunctionLoweringInfo {
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public:
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TargetLowering &TLI;
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Function *Fn;
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const Function *Fn;
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MachineFunction *MF;
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MachineRegisterInfo *RegInfo;
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@ -93,7 +93,7 @@ public:
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/// set - Initialize this FunctionLoweringInfo with the given Function
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/// and its associated MachineFunction.
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///
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void set(Function &Fn, MachineFunction &MF, bool EnableFastISel);
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void set(const Function &Fn, MachineFunction &MF, bool EnableFastISel);
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/// clear - Clear out all the function-specific state. This returns this
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/// FunctionLoweringInfo to an empty state, ready to be used for a
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@ -3610,7 +3610,7 @@ static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS,
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if (Val == 0)
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return DAG.getConstantFP(1.0, LHS.getValueType());
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Function *F = DAG.getMachineFunction().getFunction();
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const Function *F = DAG.getMachineFunction().getFunction();
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if (!F->hasFnAttr(Attribute::OptimizeForSize) ||
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// If optimizing for size, don't insert too many multiplies. This
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// inserts up to 5 multiplies.
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@ -195,7 +195,7 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
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assert((!EnableFastISelAbort || EnableFastISel) &&
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"-fast-isel-abort requires -fast-isel");
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Function &Fn = *mf.getFunction();
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const Function &Fn = *mf.getFunction();
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const TargetInstrInfo &TII = *TM.getInstrInfo();
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const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
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@ -1358,7 +1358,7 @@ ARMPreAllocLoadStoreOpt::CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1,
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return false;
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unsigned Align = (*Op0->memoperands_begin())->getAlignment();
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Function *Func = MF->getFunction();
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const Function *Func = MF->getFunction();
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unsigned ReqAlign = STI->hasV6Ops()
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? TD->getPrefTypeAlignment(Type::getInt64Ty(Func->getContext()))
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: 8; // Pre-v6 need 8-byte align
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