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[PowerPC] Allow wa inline asm to also accept floating point arguments

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GCC documentation for the `wa` constraint states that:
```
wa

    A VSX register (VSR), vs0…vs63. This is either an FPR (vs0…vs31 are f0…f31)
    or a VR (vs32…vs63 are v0…v31).
```
This technically means that we could accept floating point parameters. In fact,
gcc itself does. The following testcase compiles and runs on all PPC platforms with GCC,
whereas clang/llc will assert:
```
#include <stdio.h>
double foo ( vector double a ) {
  double b, c;
  asm("xvabsdp  %x0, %x2        \n"
             "xxsldwi  %x1, %x0, %x0, 2 \n"
      :  "+wa"    (b),
         "=wa"    (c)
      :  "wa"    (a)
      );
  return b+c;
}
int main(void) {
  vector double a = {-3., -4.};
  double t = foo( a );
  printf("%g\n", t);
}
```
This patch allows clang/llc to build and run this testcase.

Reviewed By: nemanjai, #powerpc

Differential Revision: https://reviews.llvm.org/D103409
This commit is contained in:
Zarko Todorovski 2021-06-10 16:49:51 -04:00
parent 3bc0d7e3d3
commit 64bac7eb58
2 changed files with 29 additions and 1 deletions
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8
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -15648,7 +15648,13 @@ PPCTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
} else if ((Constraint == "wa" || Constraint == "wd" ||
Constraint == "wf" || Constraint == "wi") &&
Subtarget.hasVSX()) {
return std::make_pair(0U, &PPC::VSRCRegClass);
// A VSX register for either a scalar (FP) or vector. There is no
// support for single precision scalars on subtargets prior to Power8.
if (VT.isVector())
return std::make_pair(0U, &PPC::VSRCRegClass);
if (VT == MVT::f32 && Subtarget.hasP8Vector())
return std::make_pair(0U, &PPC::VSSRCRegClass);
return std::make_pair(0U, &PPC::VSFRCRegClass);
} else if ((Constraint == "ws" || Constraint == "ww") && Subtarget.hasVSX()) {
if (VT == MVT::f32 && Subtarget.hasP8Vector())
return std::make_pair(0U, &PPC::VSSRCRegClass);

22
test/CodeGen/PowerPC/wa-asm-fpr.ll Normal file
View File

@ -0,0 +1,22 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple powerpc64le-linux-gnu --ppc-asm-full-reg-names \
; RUN: -verify-machineinstrs -mattr=vsx -mattr=altivec < %s | \
; RUN: FileCheck %s
define double @foo(<2 x double> %a) {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: #APP
; CHECK-NEXT: xvabsdp vs0, vs34
; CHECK-NEXT: xxsldwi vs1, vs0, vs0, 2
; CHECK-EMPTY:
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: xsadddp f1, f0, f1
; CHECK-NEXT: blr
entry:
%0 = call { double, double } asm "xvabsdp ${0:x}, ${2:x} \0Axxsldwi ${1:x}, ${0:x}, ${0:x}, 2 \0A", "=^wa,=^wa,^wa,0"(<2 x double> %a, double undef)
%asmresult = extractvalue { double, double } %0, 0
%asmresult1 = extractvalue { double, double } %0, 1
%add = fadd double %asmresult, %asmresult1
ret double %add
}