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[SystemZ] Support load-and-trap instructions
This adds support for the instructions provided with the load-and-trap facility. llvm-svn: 288030
This commit is contained in:
Ulrich Weigand
parent
0487d18102
commit
64c39ae7f5
@ -28,6 +28,7 @@ using namespace llvm;
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#define DEBUG_TYPE "systemz-elim-compare"
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STATISTIC(BranchOnCounts, "Number of branch-on-count instructions");
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STATISTIC(LoadAndTraps, "Number of load-and-trap instructions");
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STATISTIC(EliminatedComparisons, "Number of eliminated comparisons");
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STATISTIC(FusedComparisons, "Number of fused compare-and-branch instructions");
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@ -73,6 +74,8 @@ private:
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Reference getRegReferences(MachineInstr &MI, unsigned Reg);
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bool convertToBRCT(MachineInstr &MI, MachineInstr &Compare,
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SmallVectorImpl<MachineInstr *> &CCUsers);
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bool convertToLoadAndTrap(MachineInstr &MI, MachineInstr &Compare,
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SmallVectorImpl<MachineInstr *> &CCUsers);
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bool convertToLoadAndTest(MachineInstr &MI);
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bool adjustCCMasksForInstr(MachineInstr &MI, MachineInstr &Compare,
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SmallVectorImpl<MachineInstr *> &CCUsers);
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@ -225,6 +228,48 @@ bool SystemZElimCompare::convertToBRCT(
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return true;
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}
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// Compare compares the result of MI against zero. If MI is a suitable load
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// instruction and if CCUsers is a single conditional trap on zero, eliminate
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// the load and convert the branch to a load-and-trap. Return true on success.
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bool SystemZElimCompare::convertToLoadAndTrap(
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MachineInstr &MI, MachineInstr &Compare,
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SmallVectorImpl<MachineInstr *> &CCUsers) {
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unsigned LATOpcode = TII->getLoadAndTrap(MI.getOpcode());
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if (!LATOpcode)
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return false;
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// Check whether we have a single CondTrap that traps on zero.
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if (CCUsers.size() != 1)
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return false;
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MachineInstr *Branch = CCUsers[0];
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if (Branch->getOpcode() != SystemZ::CondTrap ||
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Branch->getOperand(0).getImm() != SystemZ::CCMASK_ICMP ||
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Branch->getOperand(1).getImm() != SystemZ::CCMASK_CMP_EQ)
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return false;
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// We already know that there are no references to the register between
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// MI and Compare. Make sure that there are also no references between
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// Compare and Branch.
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unsigned SrcReg = getCompareSourceReg(Compare);
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MachineBasicBlock::iterator MBBI = Compare, MBBE = Branch;
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for (++MBBI; MBBI != MBBE; ++MBBI)
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if (getRegReferences(*MBBI, SrcReg))
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return false;
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// The transformation is OK. Rebuild Branch as a load-and-trap.
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MachineOperand Target(Branch->getOperand(2));
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while (Branch->getNumOperands())
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Branch->RemoveOperand(0);
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Branch->setDesc(TII->get(LATOpcode));
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MachineInstrBuilder(*Branch->getParent()->getParent(), Branch)
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.addOperand(MI.getOperand(0))
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.addOperand(MI.getOperand(1))
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.addOperand(MI.getOperand(2))
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.addOperand(MI.getOperand(3));
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MI.eraseFromParent();
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return true;
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}
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// If MI is a load instruction, try to convert it into a LOAD AND TEST.
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// Return true on success.
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bool SystemZElimCompare::convertToLoadAndTest(MachineInstr &MI) {
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@ -353,11 +398,17 @@ bool SystemZElimCompare::optimizeCompareZero(
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MachineInstr &MI = *MBBI;
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if (resultTests(MI, SrcReg)) {
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// Try to remove both MI and Compare by converting a branch to BRCT(G).
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// We don't care in this case whether CC is modified between MI and
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// Compare.
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if (!CCRefs.Use && !SrcRefs && convertToBRCT(MI, Compare, CCUsers)) {
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BranchOnCounts += 1;
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return true;
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// or a load-and-trap instruction. We don't care in this case whether
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// CC is modified between MI and Compare.
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if (!CCRefs.Use && !SrcRefs) {
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if (convertToBRCT(MI, Compare, CCUsers)) {
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BranchOnCounts += 1;
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return true;
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}
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if (convertToLoadAndTrap(MI, Compare, CCUsers)) {
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LoadAndTraps += 1;
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return true;
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}
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}
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// Try to eliminate Compare by reusing a CC result from MI.
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if ((!CCRefs && convertToLoadAndTest(MI)) ||
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@ -84,6 +84,11 @@ def Arch9NewFeatures : SystemZFeatureList<[
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//
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//===----------------------------------------------------------------------===//
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def FeatureLoadAndTrap : SystemZFeature<
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"load-and-trap", "LoadAndTrap",
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"Assume that the load-and-trap facility is installed"
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>;
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def FeatureMiscellaneousExtensions : SystemZFeature<
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"miscellaneous-extensions", "MiscellaneousExtensions",
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"Assume that the miscellaneous-extensions facility is installed"
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@ -100,6 +105,7 @@ def FeatureTransactionalExecution : SystemZFeature<
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>;
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def Arch10NewFeatures : SystemZFeatureList<[
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FeatureLoadAndTrap,
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FeatureMiscellaneousExtensions,
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FeatureProcessorAssist,
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FeatureTransactionalExecution
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@ -1678,6 +1678,25 @@ unsigned SystemZInstrInfo::getFusedCompare(unsigned Opcode,
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return 0;
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}
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unsigned SystemZInstrInfo::getLoadAndTrap(unsigned Opcode) const {
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if (!STI.hasLoadAndTrap())
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return 0;
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switch (Opcode) {
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case SystemZ::L:
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case SystemZ::LY:
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return SystemZ::LAT;
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case SystemZ::LG:
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return SystemZ::LGAT;
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case SystemZ::LFH:
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return SystemZ::LFHAT;
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case SystemZ::LLGF:
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return SystemZ::LLGFAT;
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case SystemZ::LLGT:
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return SystemZ::LLGTAT;
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}
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return 0;
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}
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void SystemZInstrInfo::loadImmediate(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned Reg, uint64_t Value) const {
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@ -286,6 +286,10 @@ public:
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SystemZII::FusedCompareType Type,
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const MachineInstr *MI = nullptr) const;
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// If Opcode is a LOAD opcode for with an associated LOAD AND TRAP
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// operation exists, returh the opcode for the latter, otherwise return 0.
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unsigned getLoadAndTrap(unsigned Opcode) const;
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// Emit code before MBBI in MI to move immediate value Value into
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// physical register Reg.
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void loadImmediate(MachineBasicBlock &MBB,
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@ -426,6 +426,13 @@ let Predicates = [FeatureLoadAndZeroRightmostByte] in {
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(LZRG bdxaddr20only:$src)>;
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}
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// Load and trap.
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let Predicates = [FeatureLoadAndTrap] in {
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def LAT : UnaryRXY<"lat", 0xE39F, null_frag, GR32, 4>;
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def LFHAT : UnaryRXY<"lfhat", 0xE3C8, null_frag, GRH32, 4>;
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def LGAT : UnaryRXY<"lgat", 0xE385, null_frag, GR64, 8>;
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}
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// Register stores.
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let SimpleBDXStore = 1 in {
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// Expands to ST, STY or STFH, depending on the choice of register.
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@ -662,6 +669,12 @@ let Predicates = [FeatureLoadAndZeroRightmostByte] in {
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(LLZRGF bdxaddr20only:$src)>;
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}
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// Load and trap.
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let Predicates = [FeatureLoadAndTrap] in {
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def LLGFAT : UnaryRXY<"llgfat", 0xE39D, null_frag, GR64, 4>;
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def LLGTAT : UnaryRXY<"llgtat", 0xE39C, null_frag, GR64, 4>;
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}
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//===----------------------------------------------------------------------===//
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// Truncations
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//===----------------------------------------------------------------------===//
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@ -202,6 +202,9 @@ def : InstRW<[FXa], (instregex "LR(Mux)?$")>;
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// Load and zero rightmost byte
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def : InstRW<[LSU], (instregex "LZR(F|G)$")>;
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// Load and trap
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def : InstRW<[FXb, LSU, Lat5], (instregex "L(FH|G)?AT$")>;
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// Load and test
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def : InstRW<[FXa, LSU, Lat5], (instregex "LT(G)?$")>;
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def : InstRW<[FXa], (instregex "LT(G)?R$")>;
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@ -256,6 +259,9 @@ def : InstRW<[LSU], (instregex "LLG(C|H|F|T|HRL|FRL)$")>;
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// Load and zero rightmost byte
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def : InstRW<[LSU], (instregex "LLZRGF$")>;
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// Load and trap
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def : InstRW<[FXb, LSU, Lat5], (instregex "LLG(F|T)?AT$")>;
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//===----------------------------------------------------------------------===//
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// Truncations
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//===----------------------------------------------------------------------===//
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@ -175,6 +175,9 @@ def : InstRW<[FXU], (instregex "LG(F|H)I$")>;
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def : InstRW<[FXU], (instregex "LHI(Mux)?$")>;
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def : InstRW<[FXU], (instregex "LR(Mux)?$")>;
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// Load and trap
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def : InstRW<[FXU, LSU, Lat5], (instregex "L(FH|G)?AT$")>;
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// Load and test
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def : InstRW<[FXU, LSU, Lat5], (instregex "LT(G)?$")>;
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def : InstRW<[FXU], (instregex "LT(G)?R$")>;
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@ -224,6 +227,9 @@ def : InstRW<[FXU, LSU, Lat5], (instregex "LL(C|H)H$")>;
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def : InstRW<[LSU], (instregex "LLHRL$")>;
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def : InstRW<[LSU], (instregex "LLG(C|H|F|T|HRL|FRL)$")>;
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// Load and trap
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def : InstRW<[FXU, LSU, Lat5], (instregex "LLG(F|T)?AT$")>;
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//===----------------------------------------------------------------------===//
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// Truncations
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//===----------------------------------------------------------------------===//
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@ -39,8 +39,8 @@ SystemZSubtarget::SystemZSubtarget(const Triple &TT, const std::string &CPU,
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HasLoadStoreOnCond(false), HasHighWord(false), HasFPExtension(false),
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HasPopulationCount(false), HasFastSerialization(false),
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HasInterlockedAccess1(false), HasMiscellaneousExtensions(false),
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HasTransactionalExecution(false), HasProcessorAssist(false),
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HasVector(false), HasLoadStoreOnCond2(false),
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HasLoadAndTrap(false), HasTransactionalExecution(false),
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HasProcessorAssist(false), HasVector(false), HasLoadStoreOnCond2(false),
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HasLoadAndZeroRightmostByte(false),
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TargetTriple(TT), InstrInfo(initializeSubtargetDependencies(CPU, FS)),
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TLInfo(TM, *this), TSInfo(), FrameLowering() {}
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@ -42,6 +42,7 @@ protected:
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bool HasFastSerialization;
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bool HasInterlockedAccess1;
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bool HasMiscellaneousExtensions;
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bool HasLoadAndTrap;
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bool HasTransactionalExecution;
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bool HasProcessorAssist;
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bool HasVector;
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@ -113,6 +114,9 @@ public:
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return HasMiscellaneousExtensions;
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}
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// Return true if the target has the load-and-trap facility.
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bool hasLoadAndTrap() const { return HasLoadAndTrap; }
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// Return true if the target has the transactional-execution facility.
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bool hasTransactionalExecution() const { return HasTransactionalExecution; }
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157
test/CodeGen/SystemZ/trap-03.ll
Normal file
157
test/CodeGen/SystemZ/trap-03.ll
Normal file
@ -0,0 +1,157 @@
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; Test load-and-trap instructions (LAT/LGAT)
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s
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declare void @llvm.trap()
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; Check LAT with no displacement.
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define i32 @f1(i32 *%ptr) {
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; CHECK-LABEL: f1:
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; CHECK: lat %r2, 0(%r2)
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; CHECK: br %r14
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entry:
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%val = load i32, i32 *%ptr
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%cmp = icmp eq i32 %val, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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tail call void @llvm.trap()
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unreachable
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if.end: ; preds = %entry
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ret i32 %val
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}
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; Check the high end of the LAT range.
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define i32 @f2(i32 *%src) {
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; CHECK-LABEL: f2:
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; CHECK: lat %r2, 524284(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 131071
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%val = load i32, i32 *%ptr
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%cmp = icmp eq i32 %val, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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tail call void @llvm.trap()
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unreachable
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if.end: ; preds = %entry
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ret i32 %val
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}
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; Check the next word up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i32 @f3(i32 *%src) {
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; CHECK-LABEL: f3:
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; CHECK: agfi %r2, 524288
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; CHECK: lat %r2, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32, i32 *%src, i64 131072
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%val = load i32, i32 *%ptr
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%cmp = icmp eq i32 %val, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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tail call void @llvm.trap()
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unreachable
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if.end: ; preds = %entry
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ret i32 %val
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}
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; Check that LAT allows an index.
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define i32 @f4(i64 %src, i64 %index) {
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; CHECK-LABEL: f4:
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; CHECK: lat %r2, 524287(%r3,%r2)
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 524287
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%ptr = inttoptr i64 %add2 to i32 *
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%val = load i32, i32 *%ptr
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%cmp = icmp eq i32 %val, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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tail call void @llvm.trap()
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unreachable
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if.end: ; preds = %entry
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ret i32 %val
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}
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; Check LGAT with no displacement.
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define i64 @f5(i64 *%ptr) {
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; CHECK-LABEL: f5:
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; CHECK: lgat %r2, 0(%r2)
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; CHECK: br %r14
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entry:
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%val = load i64, i64 *%ptr
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%cmp = icmp eq i64 %val, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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tail call void @llvm.trap()
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unreachable
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if.end: ; preds = %entry
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ret i64 %val
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}
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; Check the high end of the LGAT range.
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define i64 @f6(i64 *%src) {
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; CHECK-LABEL: f6:
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; CHECK: lgat %r2, 524280(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i64, i64 *%src, i64 65535
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%val = load i64, i64 *%ptr
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%cmp = icmp eq i64 %val, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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tail call void @llvm.trap()
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unreachable
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if.end: ; preds = %entry
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ret i64 %val
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}
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; Check the next word up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f7(i64 *%src) {
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; CHECK-LABEL: f7:
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; CHECK: agfi %r2, 524288
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; CHECK: lgat %r2, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i64, i64 *%src, i64 65536
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%val = load i64, i64 *%ptr
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%cmp = icmp eq i64 %val, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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tail call void @llvm.trap()
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unreachable
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if.end: ; preds = %entry
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ret i64 %val
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}
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; Check that LGAT allows an index.
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define i64 @f8(i64 %src, i64 %index) {
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; CHECK-LABEL: f8:
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; CHECK: lgat %r2, 524287(%r3,%r2)
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 524287
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%ptr = inttoptr i64 %add2 to i64 *
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%val = load i64, i64 *%ptr
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%cmp = icmp eq i64 %val, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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tail call void @llvm.trap()
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unreachable
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if.end: ; preds = %entry
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ret i64 %val
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}
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170
test/CodeGen/SystemZ/trap-04.ll
Normal file
170
test/CodeGen/SystemZ/trap-04.ll
Normal file
@ -0,0 +1,170 @@
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; Test load-and-trap instructions (LLGFAT/LLGFTAT)
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s
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declare void @llvm.trap()
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; Check LLGFAT with no displacement.
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define i64 @f1(i32 *%ptr) {
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; CHECK-LABEL: f1:
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; CHECK: llgfat %r2, 0(%r2)
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; CHECK: br %r14
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entry:
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%val = load i32, i32 *%ptr
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%ext = zext i32 %val to i64
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%cmp = icmp eq i64 %ext, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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tail call void @llvm.trap()
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unreachable
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if.end: ; preds = %entry
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ret i64 %ext
|
||||
}
|
||||
|
||||
; Check the high end of the LLGFAT range.
|
||||
define i64 @f2(i32 *%src) {
|
||||
; CHECK-LABEL: f2:
|
||||
; CHECK: llgfat %r2, 524284(%r2)
|
||||
; CHECK: br %r14
|
||||
%ptr = getelementptr i32, i32 *%src, i64 131071
|
||||
%val = load i32, i32 *%ptr
|
||||
%ext = zext i32 %val to i64
|
||||
%cmp = icmp eq i64 %ext, 0
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
|
||||
if.then: ; preds = %entry
|
||||
tail call void @llvm.trap()
|
||||
unreachable
|
||||
|
||||
if.end: ; preds = %entry
|
||||
ret i64 %ext
|
||||
}
|
||||
|
||||
; Check the next word up, which needs separate address logic.
|
||||
; Other sequences besides this one would be OK.
|
||||
define i64 @f3(i32 *%src) {
|
||||
; CHECK-LABEL: f3:
|
||||
; CHECK: agfi %r2, 524288
|
||||
; CHECK: llgfat %r2, 0(%r2)
|
||||
; CHECK: br %r14
|
||||
%ptr = getelementptr i32, i32 *%src, i64 131072
|
||||
%val = load i32, i32 *%ptr
|
||||
%ext = zext i32 %val to i64
|
||||
%cmp = icmp eq i64 %ext, 0
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
|
||||
if.then: ; preds = %entry
|
||||
tail call void @llvm.trap()
|
||||
unreachable
|
||||
|
||||
if.end: ; preds = %entry
|
||||
ret i64 %ext
|
||||
}
|
||||
|
||||
; Check that LLGFAT allows an index.
|
||||
define i64 @f4(i64 %src, i64 %index) {
|
||||
; CHECK-LABEL: f4:
|
||||
; CHECK: llgfat %r2, 524287(%r3,%r2)
|
||||
; CHECK: br %r14
|
||||
%add1 = add i64 %src, %index
|
||||
%add2 = add i64 %add1, 524287
|
||||
%ptr = inttoptr i64 %add2 to i32 *
|
||||
%val = load i32, i32 *%ptr
|
||||
%ext = zext i32 %val to i64
|
||||
%cmp = icmp eq i64 %ext, 0
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
|
||||
if.then: ; preds = %entry
|
||||
tail call void @llvm.trap()
|
||||
unreachable
|
||||
|
||||
if.end: ; preds = %entry
|
||||
ret i64 %ext
|
||||
}
|
||||
|
||||
; Check LLGTAT with no displacement.
|
||||
define i64 @f5(i32 *%ptr) {
|
||||
; CHECK-LABEL: f5:
|
||||
; CHECK: llgtat %r2, 0(%r2)
|
||||
; CHECK: br %r14
|
||||
entry:
|
||||
%val = load i32, i32 *%ptr
|
||||
%ext = zext i32 %val to i64
|
||||
%and = and i64 %ext, 2147483647
|
||||
%cmp = icmp eq i64 %and, 0
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
|
||||
if.then: ; preds = %entry
|
||||
tail call void @llvm.trap()
|
||||
unreachable
|
||||
|
||||
if.end: ; preds = %entry
|
||||
ret i64 %and
|
||||
}
|
||||
|
||||
; Check the high end of the LLGTAT range.
|
||||
define i64 @f6(i32 *%src) {
|
||||
; CHECK-LABEL: f6:
|
||||
; CHECK: llgtat %r2, 524284(%r2)
|
||||
; CHECK: br %r14
|
||||
%ptr = getelementptr i32, i32 *%src, i64 131071
|
||||
%val = load i32, i32 *%ptr
|
||||
%ext = zext i32 %val to i64
|
||||
%and = and i64 %ext, 2147483647
|
||||
%cmp = icmp eq i64 %and, 0
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
|
||||
if.then: ; preds = %entry
|
||||
tail call void @llvm.trap()
|
||||
unreachable
|
||||
|
||||
if.end: ; preds = %entry
|
||||
ret i64 %and
|
||||
}
|
||||
|
||||
; Check the next word up, which needs separate address logic.
|
||||
; Other sequences besides this one would be OK.
|
||||
define i64 @f7(i32 *%src) {
|
||||
; CHECK-LABEL: f7:
|
||||
; CHECK: agfi %r2, 524288
|
||||
; CHECK: llgtat %r2, 0(%r2)
|
||||
; CHECK: br %r14
|
||||
%ptr = getelementptr i32, i32 *%src, i64 131072
|
||||
%val = load i32, i32 *%ptr
|
||||
%ext = zext i32 %val to i64
|
||||
%and = and i64 %ext, 2147483647
|
||||
%cmp = icmp eq i64 %and, 0
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
|
||||
if.then: ; preds = %entry
|
||||
tail call void @llvm.trap()
|
||||
unreachable
|
||||
|
||||
if.end: ; preds = %entry
|
||||
ret i64 %and
|
||||
}
|
||||
|
||||
; Check that LLGTAT allows an index.
|
||||
define i64 @f8(i64 %src, i64 %index) {
|
||||
; CHECK-LABEL: f8:
|
||||
; CHECK: llgtat %r2, 524287(%r3,%r2)
|
||||
; CHECK: br %r14
|
||||
%add1 = add i64 %src, %index
|
||||
%add2 = add i64 %add1, 524287
|
||||
%ptr = inttoptr i64 %add2 to i32 *
|
||||
%val = load i32, i32 *%ptr
|
||||
%ext = zext i32 %val to i64
|
||||
%and = and i64 %ext, 2147483647
|
||||
%cmp = icmp eq i64 %and, 0
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
|
||||
if.then: ; preds = %entry
|
||||
tail call void @llvm.trap()
|
||||
unreachable
|
||||
|
||||
if.end: ; preds = %entry
|
||||
ret i64 %and
|
||||
}
|
||||
|
||||
92
test/CodeGen/SystemZ/trap-05.ll
Normal file
92
test/CodeGen/SystemZ/trap-05.ll
Normal file
@ -0,0 +1,92 @@
|
||||
; Test load-and-trap instructions (LFHAT)
|
||||
; See comments in asm-18.ll about testing high-word operations.
|
||||
;
|
||||
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 \
|
||||
; RUN: -no-integrated-as | FileCheck %s
|
||||
|
||||
declare void @llvm.trap()
|
||||
|
||||
; Check LAT with no displacement.
|
||||
define void @f1(i32 *%ptr) {
|
||||
; CHECK-LABEL: f1:
|
||||
; CHECK: lfhat [[REG:%r[0-9]+]], 0(%r2)
|
||||
; CHECK: stepa [[REG]]
|
||||
; CHECK: br %r14
|
||||
entry:
|
||||
%val = load i32, i32 *%ptr
|
||||
%cmp = icmp eq i32 %val, 0
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
|
||||
if.then: ; preds = %entry
|
||||
tail call void @llvm.trap()
|
||||
unreachable
|
||||
|
||||
if.end: ; preds = %entry
|
||||
call void asm sideeffect "stepa $0", "h"(i32 %val)
|
||||
ret void;
|
||||
}
|
||||
|
||||
; Check the high end of the LAT range.
|
||||
define void @f2(i32 *%src) {
|
||||
; CHECK-LABEL: f2:
|
||||
; CHECK: lfhat [[REG:%r[0-9]+]], 524284(%r2)
|
||||
; CHECK: stepa [[REG]]
|
||||
; CHECK: br %r14
|
||||
%ptr = getelementptr i32, i32 *%src, i64 131071
|
||||
%val = load i32, i32 *%ptr
|
||||
%cmp = icmp eq i32 %val, 0
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
|
||||
if.then: ; preds = %entry
|
||||
tail call void @llvm.trap()
|
||||
unreachable
|
||||
|
||||
if.end: ; preds = %entry
|
||||
call void asm sideeffect "stepa $0", "h"(i32 %val)
|
||||
ret void;
|
||||
}
|
||||
|
||||
; Check the next word up, which needs separate address logic.
|
||||
; Other sequences besides this one would be OK.
|
||||
define void @f3(i32 *%src) {
|
||||
; CHECK-LABEL: f3:
|
||||
; CHECK: agfi %r2, 524288
|
||||
; CHECK: lfhat [[REG:%r[0-9]+]], 0(%r2)
|
||||
; CHECK: stepa [[REG]]
|
||||
; CHECK: br %r14
|
||||
%ptr = getelementptr i32, i32 *%src, i64 131072
|
||||
%val = load i32, i32 *%ptr
|
||||
%cmp = icmp eq i32 %val, 0
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
|
||||
if.then: ; preds = %entry
|
||||
tail call void @llvm.trap()
|
||||
unreachable
|
||||
|
||||
if.end: ; preds = %entry
|
||||
call void asm sideeffect "stepa $0", "h"(i32 %val)
|
||||
ret void;
|
||||
}
|
||||
|
||||
; Check that LAT allows an index.
|
||||
define void @f4(i64 %src, i64 %index) {
|
||||
; CHECK-LABEL: f4:
|
||||
; CHECK: lfhat [[REG:%r[0-9]+]], 524287(%r3,%r2)
|
||||
; CHECK: stepa [[REG]]
|
||||
; CHECK: br %r14
|
||||
%add1 = add i64 %src, %index
|
||||
%add2 = add i64 %add1, 524287
|
||||
%ptr = inttoptr i64 %add2 to i32 *
|
||||
%val = load i32, i32 *%ptr
|
||||
%cmp = icmp eq i32 %val, 0
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
|
||||
if.then: ; preds = %entry
|
||||
tail call void @llvm.trap()
|
||||
unreachable
|
||||
|
||||
if.end: ; preds = %entry
|
||||
call void asm sideeffect "stepa $0", "h"(i32 %val)
|
||||
ret void;
|
||||
}
|
||||
|
||||
@ -5188,6 +5188,36 @@
|
||||
# CHECK: lfh %r15, 0
|
||||
0xe3 0xf0 0x00 0x00 0x00 0xca
|
||||
|
||||
# CHECK: lfhat %r0, -524288
|
||||
0xe3 0x00 0x00 0x00 0x80 0xc8
|
||||
|
||||
# CHECK: lfhat %r0, -1
|
||||
0xe3 0x00 0x0f 0xff 0xff 0xc8
|
||||
|
||||
# CHECK: lfhat %r0, 0
|
||||
0xe3 0x00 0x00 0x00 0x00 0xc8
|
||||
|
||||
# CHECK: lfhat %r0, 1
|
||||
0xe3 0x00 0x00 0x01 0x00 0xc8
|
||||
|
||||
# CHECK: lfhat %r0, 524287
|
||||
0xe3 0x00 0x0f 0xff 0x7f 0xc8
|
||||
|
||||
# CHECK: lfhat %r0, 0(%r1)
|
||||
0xe3 0x00 0x10 0x00 0x00 0xc8
|
||||
|
||||
# CHECK: lfhat %r0, 0(%r15)
|
||||
0xe3 0x00 0xf0 0x00 0x00 0xc8
|
||||
|
||||
# CHECK: lfhat %r0, 524287(%r1,%r15)
|
||||
0xe3 0x01 0xff 0xff 0x7f 0xc8
|
||||
|
||||
# CHECK: lfhat %r0, 524287(%r15,%r1)
|
||||
0xe3 0x0f 0x1f 0xff 0x7f 0xc8
|
||||
|
||||
# CHECK: lfhat %r15, 0
|
||||
0xe3 0xf0 0x00 0x00 0x00 0xc8
|
||||
|
||||
# CHECK: lgbr %r0, %r15
|
||||
0xb9 0x06 0x00 0x0f
|
||||
|
||||
@ -5398,6 +5428,36 @@
|
||||
# CHECK: lg %r15, 0
|
||||
0xe3 0xf0 0x00 0x00 0x00 0x04
|
||||
|
||||
# CHECK: lgat %r0, -524288
|
||||
0xe3 0x00 0x00 0x00 0x80 0x85
|
||||
|
||||
# CHECK: lgat %r0, -1
|
||||
0xe3 0x00 0x0f 0xff 0xff 0x85
|
||||
|
||||
# CHECK: lgat %r0, 0
|
||||
0xe3 0x00 0x00 0x00 0x00 0x85
|
||||
|
||||
# CHECK: lgat %r0, 1
|
||||
0xe3 0x00 0x00 0x01 0x00 0x85
|
||||
|
||||
# CHECK: lgat %r0, 524287
|
||||
0xe3 0x00 0x0f 0xff 0x7f 0x85
|
||||
|
||||
# CHECK: lgat %r0, 0(%r1)
|
||||
0xe3 0x00 0x10 0x00 0x00 0x85
|
||||
|
||||
# CHECK: lgat %r0, 0(%r15)
|
||||
0xe3 0x00 0xf0 0x00 0x00 0x85
|
||||
|
||||
# CHECK: lgat %r0, 524287(%r1,%r15)
|
||||
0xe3 0x01 0xff 0xff 0x7f 0x85
|
||||
|
||||
# CHECK: lgat %r0, 524287(%r15,%r1)
|
||||
0xe3 0x0f 0x1f 0xff 0x7f 0x85
|
||||
|
||||
# CHECK: lgat %r15, 0
|
||||
0xe3 0xf0 0x00 0x00 0x00 0x85
|
||||
|
||||
# CHECK: lhi %r0, -32768
|
||||
0xa7 0x08 0x80 0x00
|
||||
|
||||
@ -5653,6 +5713,36 @@
|
||||
# CHECK: llgf %r15, 0
|
||||
0xe3 0xf0 0x00 0x00 0x00 0x16
|
||||
|
||||
# CHECK: llgfat %r0, -524288
|
||||
0xe3 0x00 0x00 0x00 0x80 0x9d
|
||||
|
||||
# CHECK: llgfat %r0, -1
|
||||
0xe3 0x00 0x0f 0xff 0xff 0x9d
|
||||
|
||||
# CHECK: llgfat %r0, 0
|
||||
0xe3 0x00 0x00 0x00 0x00 0x9d
|
||||
|
||||
# CHECK: llgfat %r0, 1
|
||||
0xe3 0x00 0x00 0x01 0x00 0x9d
|
||||
|
||||
# CHECK: llgfat %r0, 524287
|
||||
0xe3 0x00 0x0f 0xff 0x7f 0x9d
|
||||
|
||||
# CHECK: llgfat %r0, 0(%r1)
|
||||
0xe3 0x00 0x10 0x00 0x00 0x9d
|
||||
|
||||
# CHECK: llgfat %r0, 0(%r15)
|
||||
0xe3 0x00 0xf0 0x00 0x00 0x9d
|
||||
|
||||
# CHECK: llgfat %r0, 524287(%r1,%r15)
|
||||
0xe3 0x01 0xff 0xff 0x7f 0x9d
|
||||
|
||||
# CHECK: llgfat %r0, 524287(%r15,%r1)
|
||||
0xe3 0x0f 0x1f 0xff 0x7f 0x9d
|
||||
|
||||
# CHECK: llgfat %r15, 0
|
||||
0xe3 0xf0 0x00 0x00 0x00 0x9d
|
||||
|
||||
# CHECK: llgtr %r0, %r15
|
||||
0xb9 0x17 0x00 0x0f
|
||||
|
||||
@ -5692,6 +5782,36 @@
|
||||
# CHECK: llgt %r15, 0
|
||||
0xe3 0xf0 0x00 0x00 0x00 0x17
|
||||
|
||||
# CHECK: llgtat %r0, -524288
|
||||
0xe3 0x00 0x00 0x00 0x80 0x9c
|
||||
|
||||
# CHECK: llgtat %r0, -1
|
||||
0xe3 0x00 0x0f 0xff 0xff 0x9c
|
||||
|
||||
# CHECK: llgtat %r0, 0
|
||||
0xe3 0x00 0x00 0x00 0x00 0x9c
|
||||
|
||||
# CHECK: llgtat %r0, 1
|
||||
0xe3 0x00 0x00 0x01 0x00 0x9c
|
||||
|
||||
# CHECK: llgtat %r0, 524287
|
||||
0xe3 0x00 0x0f 0xff 0x7f 0x9c
|
||||
|
||||
# CHECK: llgtat %r0, 0(%r1)
|
||||
0xe3 0x00 0x10 0x00 0x00 0x9c
|
||||
|
||||
# CHECK: llgtat %r0, 0(%r15)
|
||||
0xe3 0x00 0xf0 0x00 0x00 0x9c
|
||||
|
||||
# CHECK: llgtat %r0, 524287(%r1,%r15)
|
||||
0xe3 0x01 0xff 0xff 0x7f 0x9c
|
||||
|
||||
# CHECK: llgtat %r0, 524287(%r15,%r1)
|
||||
0xe3 0x0f 0x1f 0xff 0x7f 0x9c
|
||||
|
||||
# CHECK: llgtat %r15, 0
|
||||
0xe3 0xf0 0x00 0x00 0x00 0x9c
|
||||
|
||||
# CHECK: llghr %r0, %r15
|
||||
0xb9 0x85 0x00 0x0f
|
||||
|
||||
@ -6502,6 +6622,36 @@
|
||||
# CHECK: l %r15, 0
|
||||
0x58 0xf0 0x00 0x00
|
||||
|
||||
# CHECK: lat %r0, -524288
|
||||
0xe3 0x00 0x00 0x00 0x80 0x9f
|
||||
|
||||
# CHECK: lat %r0, -1
|
||||
0xe3 0x00 0x0f 0xff 0xff 0x9f
|
||||
|
||||
# CHECK: lat %r0, 0
|
||||
0xe3 0x00 0x00 0x00 0x00 0x9f
|
||||
|
||||
# CHECK: lat %r0, 1
|
||||
0xe3 0x00 0x00 0x01 0x00 0x9f
|
||||
|
||||
# CHECK: lat %r0, 524287
|
||||
0xe3 0x00 0x0f 0xff 0x7f 0x9f
|
||||
|
||||
# CHECK: lat %r0, 0(%r1)
|
||||
0xe3 0x00 0x10 0x00 0x00 0x9f
|
||||
|
||||
# CHECK: lat %r0, 0(%r15)
|
||||
0xe3 0x00 0xf0 0x00 0x00 0x9f
|
||||
|
||||
# CHECK: lat %r0, 524287(%r1,%r15)
|
||||
0xe3 0x01 0xff 0xff 0x7f 0x9f
|
||||
|
||||
# CHECK: lat %r0, 524287(%r15,%r1)
|
||||
0xe3 0x0f 0x1f 0xff 0x7f 0x9f
|
||||
|
||||
# CHECK: lat %r15, 0
|
||||
0xe3 0xf0 0x00 0x00 0x00 0x9f
|
||||
|
||||
# CHECK: lt %r0, -524288
|
||||
0xe3 0x00 0x00 0x00 0x80 0x12
|
||||
|
||||
|
||||
@ -54,6 +54,46 @@
|
||||
clgto %r0, 0
|
||||
clgtno %r0, 0
|
||||
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: lat %r0, -524289
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: lat %r0, 524288
|
||||
|
||||
lat %r0, -524289
|
||||
lat %r0, 524288
|
||||
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: lfhat %r0, -524289
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: lfhat %r0, 524288
|
||||
|
||||
lfhat %r0, -524289
|
||||
lfhat %r0, 524288
|
||||
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: lgat %r0, -524289
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: lgat %r0, 524288
|
||||
|
||||
lgat %r0, -524289
|
||||
lgat %r0, 524288
|
||||
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: llgfat %r0, -524289
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: llgfat %r0, 524288
|
||||
|
||||
llgfat %r0, -524289
|
||||
llgfat %r0, 524288
|
||||
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: llgtat %r0, -524289
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: llgtat %r0, 524288
|
||||
|
||||
llgtat %r0, -524289
|
||||
llgtat %r0, 524288
|
||||
|
||||
#CHECK: error: instruction requires: vector
|
||||
#CHECK: lcbb %r0, 0, 0
|
||||
|
||||
|
||||
@ -66,6 +66,116 @@
|
||||
clgtnl %r0, 0(%r15)
|
||||
clgtnh %r0, 0(%r15)
|
||||
|
||||
#CHECK: lat %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x9f]
|
||||
#CHECK: lat %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x9f]
|
||||
#CHECK: lat %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x9f]
|
||||
#CHECK: lat %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x9f]
|
||||
#CHECK: lat %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x9f]
|
||||
#CHECK: lat %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x9f]
|
||||
#CHECK: lat %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x9f]
|
||||
#CHECK: lat %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x9f]
|
||||
#CHECK: lat %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x9f]
|
||||
#CHECK: lat %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x9f]
|
||||
|
||||
lat %r0, -524288
|
||||
lat %r0, -1
|
||||
lat %r0, 0
|
||||
lat %r0, 1
|
||||
lat %r0, 524287
|
||||
lat %r0, 0(%r1)
|
||||
lat %r0, 0(%r15)
|
||||
lat %r0, 524287(%r1,%r15)
|
||||
lat %r0, 524287(%r15,%r1)
|
||||
lat %r15, 0
|
||||
|
||||
#CHECK: lfhat %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0xc8]
|
||||
#CHECK: lfhat %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0xc8]
|
||||
#CHECK: lfhat %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0xc8]
|
||||
#CHECK: lfhat %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0xc8]
|
||||
#CHECK: lfhat %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0xc8]
|
||||
#CHECK: lfhat %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0xc8]
|
||||
#CHECK: lfhat %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0xc8]
|
||||
#CHECK: lfhat %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0xc8]
|
||||
#CHECK: lfhat %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0xc8]
|
||||
#CHECK: lfhat %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0xc8]
|
||||
|
||||
lfhat %r0, -524288
|
||||
lfhat %r0, -1
|
||||
lfhat %r0, 0
|
||||
lfhat %r0, 1
|
||||
lfhat %r0, 524287
|
||||
lfhat %r0, 0(%r1)
|
||||
lfhat %r0, 0(%r15)
|
||||
lfhat %r0, 524287(%r1,%r15)
|
||||
lfhat %r0, 524287(%r15,%r1)
|
||||
lfhat %r15, 0
|
||||
|
||||
#CHECK: lgat %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x85]
|
||||
#CHECK: lgat %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x85]
|
||||
#CHECK: lgat %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x85]
|
||||
#CHECK: lgat %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x85]
|
||||
#CHECK: lgat %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x85]
|
||||
#CHECK: lgat %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x85]
|
||||
#CHECK: lgat %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x85]
|
||||
#CHECK: lgat %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x85]
|
||||
#CHECK: lgat %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x85]
|
||||
#CHECK: lgat %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x85]
|
||||
|
||||
lgat %r0, -524288
|
||||
lgat %r0, -1
|
||||
lgat %r0, 0
|
||||
lgat %r0, 1
|
||||
lgat %r0, 524287
|
||||
lgat %r0, 0(%r1)
|
||||
lgat %r0, 0(%r15)
|
||||
lgat %r0, 524287(%r1,%r15)
|
||||
lgat %r0, 524287(%r15,%r1)
|
||||
lgat %r15, 0
|
||||
|
||||
#CHECK: llgfat %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x9d]
|
||||
#CHECK: llgfat %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x9d]
|
||||
#CHECK: llgfat %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x9d]
|
||||
#CHECK: llgfat %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x9d]
|
||||
#CHECK: llgfat %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x9d]
|
||||
#CHECK: llgfat %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x9d]
|
||||
#CHECK: llgfat %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x9d]
|
||||
#CHECK: llgfat %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x9d]
|
||||
#CHECK: llgfat %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x9d]
|
||||
#CHECK: llgfat %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x9d]
|
||||
|
||||
llgfat %r0, -524288
|
||||
llgfat %r0, -1
|
||||
llgfat %r0, 0
|
||||
llgfat %r0, 1
|
||||
llgfat %r0, 524287
|
||||
llgfat %r0, 0(%r1)
|
||||
llgfat %r0, 0(%r15)
|
||||
llgfat %r0, 524287(%r1,%r15)
|
||||
llgfat %r0, 524287(%r15,%r1)
|
||||
llgfat %r15, 0
|
||||
|
||||
#CHECK: llgtat %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x9c]
|
||||
#CHECK: llgtat %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x9c]
|
||||
#CHECK: llgtat %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x9c]
|
||||
#CHECK: llgtat %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x9c]
|
||||
#CHECK: llgtat %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x9c]
|
||||
#CHECK: llgtat %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x9c]
|
||||
#CHECK: llgtat %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x9c]
|
||||
#CHECK: llgtat %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x9c]
|
||||
#CHECK: llgtat %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x9c]
|
||||
#CHECK: llgtat %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x9c]
|
||||
|
||||
llgtat %r0, -524288
|
||||
llgtat %r0, -1
|
||||
llgtat %r0, 0
|
||||
llgtat %r0, 1
|
||||
llgtat %r0, 524287
|
||||
llgtat %r0, 0(%r1)
|
||||
llgtat %r0, 0(%r15)
|
||||
llgtat %r0, 524287(%r1,%r15)
|
||||
llgtat %r0, 524287(%r15,%r1)
|
||||
llgtat %r15, 0
|
||||
|
||||
#CHECK: etnd %r0 # encoding: [0xb2,0xec,0x00,0x00]
|
||||
#CHECK: etnd %r15 # encoding: [0xb2,0xec,0x00,0xf0]
|
||||
#CHECK: etnd %r7 # encoding: [0xb2,0xec,0x00,0x70]
|
||||
|
||||
Loading…
Reference in New Issue
Block a user