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Fix a bug in the ARM disassembly of the neon VLD2 all lanes instruction.

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llvm-svn: 152127
This commit is contained in:
Kevin Enderby 2012-03-06 18:33:12 +00:00
parent 9bfd7cd1ad
commit 64d11852dd
3 changed files with 21 additions and 7 deletions
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14
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
View File

@ -2556,17 +2556,14 @@ static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
unsigned align = fieldFromInstruction32(Insn, 4, 1);
unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
unsigned pred = fieldFromInstruction32(Insn, 22, 4);
align *= 2*size;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
return MCDisassembler::Fail;
if (Rm != 0xF) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
}
if (Rm != 0xF)
Inst.addOperand(MCOperand::CreateImm(0));
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
@ -2579,6 +2576,9 @@ static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
return MCDisassembler::Fail;
}
if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
return MCDisassembler::Fail;
return S;
}

7
test/MC/Disassembler/ARM/neon.txt
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@ -1869,3 +1869,10 @@
# CHECK: vmov.f32 d0, #1.600000e+01
# CHECK: vmov.f32 q0, #1.600000e+01
# rdar://10798451
0xe7 0xf9 0x32 0x1d
# CHECK vld2.8 {d17[], d19[]}, [r7, :16], r2
0xe7 0xf9 0x3d 0x1d
# CHECK vld2.8 {d17[], d19[]}, [r7, :16]!
0xe7 0xf9 0x3f 0x1d
# CHECK vld2.8 {d17[], d19[]}, [r7, :16]

7
test/MC/Disassembler/ARM/neont2.txt
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@ -1588,3 +1588,10 @@
0x63 0xf9 0x37 0xc9
# CHECK: vld2.8 {d28, d30}, [r3, :256], r7
# rdar://10798451
0xe7 0xf9 0x32 0x1d
# CHECK vld2.8 {d17[], d19[]}, [r7, :16], r2
0xe7 0xf9 0x3d 0x1d
# CHECK vld2.8 {d17[], d19[]}, [r7, :16]!
0xe7 0xf9 0x3f 0x1d
# CHECK vld2.8 {d17[], d19[]}, [r7, :16]