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[X86] X86DAGToDAGISel::matchBitExtract(): pattern c: truncation awareness

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Summary:
The one thing of note here is that the 'bitwidth' constant (32/64) was previously pessimistic.
Given `x & (-1 >> (C - z))`, we were taking `C` to be `bitwidth(x)`, but in reality
we want `(-1 >> (C - z))` pattern to mean "low z bits must be all-ones".
And for that, `C` should be `bitwidth(-1 >> (C - z))`, i.e. of the shift operation itself.

Last pattern D does not seem to exhibit any of these truncation issues.
Although it has the opposite problem - if we extract low bits (no shift) from i64,
and then truncate to i32, then we fail to shrink this 64-bit extraction into 32-bit extraction.

Reviewers: RKSimon, craig.topper, spatel

Reviewed By: RKSimon

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D62806

llvm-svn: 364419
This commit is contained in:
Roman Lebedev 2019-06-26 12:19:47 +00:00
parent 3a16dbe1da
commit 64d5bf1738
3 changed files with 21 additions and 34 deletions
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20
lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@ -3136,8 +3136,6 @@ bool X86DAGToDAGISel::matchBitExtract(SDNode *Node) {
if (NVT != MVT::i32 && NVT != MVT::i64)
return false;
unsigned Size = NVT.getSizeInBits();
SDValue NBits;
// If we have BMI2's BZHI, we are ok with muti-use patterns.
@ -3207,7 +3205,8 @@ bool X86DAGToDAGISel::matchBitExtract(SDNode *Node) {
};
// Match potentially-truncated (bitwidth - y)
auto matchShiftAmt = [checkOneUse, Size, &NBits](SDValue ShiftAmt) {
auto matchShiftAmt = [checkOneUse, &NBits](SDValue ShiftAmt,
unsigned Bitwidth) {
// Skip over a truncate of the shift amount.
if (ShiftAmt.getOpcode() == ISD::TRUNCATE) {
ShiftAmt = ShiftAmt.getOperand(0);
@ -3219,25 +3218,29 @@ bool X86DAGToDAGISel::matchBitExtract(SDNode *Node) {
if (ShiftAmt.getOpcode() != ISD::SUB)
return false;
auto V0 = dyn_cast<ConstantSDNode>(ShiftAmt.getOperand(0));
if (!V0 || V0->getZExtValue() != Size)
if (!V0 || V0->getZExtValue() != Bitwidth)
return false;
NBits = ShiftAmt.getOperand(1);
return true;
};
// c) x & (-1 >> (32 - y))
auto matchPatternC = [&checkOneUse, matchShiftAmt](SDValue Mask) -> bool {
auto matchPatternC = [&checkOneUse, &peekThroughOneUseTruncation,
matchShiftAmt](SDValue Mask) -> bool {
// The mask itself may be truncated.
Mask = peekThroughOneUseTruncation(Mask);
unsigned Bitwidth = Mask.getSimpleValueType().getSizeInBits();
// Match `l>>`. Must only have one use!
if (Mask.getOpcode() != ISD::SRL || !checkOneUse(Mask))
return false;
// We should be shifting all-ones constant.
// We should be shifting truly all-ones constant.
if (!isAllOnesConstant(Mask.getOperand(0)))
return false;
SDValue M1 = Mask.getOperand(1);
// The shift amount should not be used externally.
if (!checkOneUse(M1))
return false;
return matchShiftAmt(M1);
return matchShiftAmt(M1, Bitwidth);
};
SDValue X;
@ -3250,13 +3253,14 @@ bool X86DAGToDAGISel::matchBitExtract(SDNode *Node) {
SDValue N0 = Node->getOperand(0);
if (N0->getOpcode() != ISD::SHL || !checkOneUse(N0))
return false;
unsigned Bitwidth = N0.getSimpleValueType().getSizeInBits();
SDValue N1 = Node->getOperand(1);
SDValue N01 = N0->getOperand(1);
// Both of the shifts must be by the exact same value.
// There should not be any uses of the shift amount outside of the pattern.
if (N1 != N01 || !checkTwoUse(N1))
return false;
if (!matchShiftAmt(N1))
if (!matchShiftAmt(N1, Bitwidth))
return false;
X = N0->getOperand(0);
return true;

20
test/CodeGen/X86/extract-bits.ll
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@ -6258,25 +6258,17 @@ define i32 @bextr64_32_c0(i64 %val, i64 %numskipbits, i64 %numlowbits) nounwind
;
; X64-BMI1NOTBM-LABEL: bextr64_32_c0:
; X64-BMI1NOTBM: # %bb.0:
; X64-BMI1NOTBM-NEXT: movq %rsi, %rcx
; X64-BMI1NOTBM-NEXT: # kill: def $cl killed $cl killed $rcx
; X64-BMI1NOTBM-NEXT: shrq %cl, %rdi
; X64-BMI1NOTBM-NEXT: negb %dl
; X64-BMI1NOTBM-NEXT: movq $-1, %rax
; X64-BMI1NOTBM-NEXT: movl %edx, %ecx
; X64-BMI1NOTBM-NEXT: shrq %cl, %rax
; X64-BMI1NOTBM-NEXT: andl %edi, %eax
; X64-BMI1NOTBM-NEXT: shll $8, %edx
; X64-BMI1NOTBM-NEXT: movzbl %sil, %eax
; X64-BMI1NOTBM-NEXT: orl %edx, %eax
; X64-BMI1NOTBM-NEXT: bextrq %rax, %rdi, %rax
; X64-BMI1NOTBM-NEXT: # kill: def $eax killed $eax killed $rax
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bextr64_32_c0:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: shrxq %rsi, %rdi, %rcx
; X64-BMI1BMI2-NEXT: negb %dl
; X64-BMI1BMI2-NEXT: movq $-1, %rax
; X64-BMI1BMI2-NEXT: shrxq %rdx, %rax, %rax
; X64-BMI1BMI2-NEXT: andl %ecx, %eax
; X64-BMI1BMI2-NEXT: # kill: def $eax killed $eax killed $rax
; X64-BMI1BMI2-NEXT: shrxq %rsi, %rdi, %rax
; X64-BMI1BMI2-NEXT: bzhil %edx, %eax, %eax
; X64-BMI1BMI2-NEXT: retq
%shifted = lshr i64 %val, %numskipbits
%numhighbits = sub i64 64, %numlowbits

15
test/CodeGen/X86/extract-lowbits.ll
View File

@ -3463,22 +3463,13 @@ define i32 @bzhi64_32_c0(i64 %val, i64 %numlowbits) nounwind {
;
; X64-BMI1NOTBM-LABEL: bzhi64_32_c0:
; X64-BMI1NOTBM: # %bb.0:
; X64-BMI1NOTBM-NEXT: movq %rsi, %rcx
; X64-BMI1NOTBM-NEXT: negb %cl
; X64-BMI1NOTBM-NEXT: movq $-1, %rax
; X64-BMI1NOTBM-NEXT: # kill: def $cl killed $cl killed $rcx
; X64-BMI1NOTBM-NEXT: shrq %cl, %rax
; X64-BMI1NOTBM-NEXT: andl %edi, %eax
; X64-BMI1NOTBM-NEXT: # kill: def $eax killed $eax killed $rax
; X64-BMI1NOTBM-NEXT: shll $8, %esi
; X64-BMI1NOTBM-NEXT: bextrl %esi, %edi, %eax
; X64-BMI1NOTBM-NEXT: retq
;
; X64-BMI1BMI2-LABEL: bzhi64_32_c0:
; X64-BMI1BMI2: # %bb.0:
; X64-BMI1BMI2-NEXT: negb %sil
; X64-BMI1BMI2-NEXT: movq $-1, %rax
; X64-BMI1BMI2-NEXT: shrxq %rsi, %rax, %rax
; X64-BMI1BMI2-NEXT: andl %edi, %eax
; X64-BMI1BMI2-NEXT: # kill: def $eax killed $eax killed $rax
; X64-BMI1BMI2-NEXT: bzhil %esi, %edi, %eax
; X64-BMI1BMI2-NEXT: retq
%numhighbits = sub i64 64, %numlowbits
%mask = lshr i64 -1, %numhighbits