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Handle the case of live 16-bit subregisters in X86FixupBWInsts
Differential Revision: https://reviews.llvm.org/D40524 Change-Id: Ie3a405b28503ceae999f5f3ba07a68fa733a2400 llvm-svn: 321674
This commit is contained in:
Andrew Kaylor
parent
75e3183a98
commit
656d44c5da
@ -166,81 +166,6 @@ bool FixupBWInstPass::runOnMachineFunction(MachineFunction &MF) {
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return true;
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}
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/// Check if register \p Reg is live after the \p MI.
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///
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/// \p LiveRegs should be in a state describing liveness information in
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/// that exact place as this function tries to precise analysis made
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/// by \p LiveRegs by exploiting the information about particular
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/// instruction \p MI. \p MI is expected to be one of the MOVs handled
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/// by the x86FixupBWInsts pass.
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/// Note: similar to LivePhysRegs::contains this would state that
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/// super-register is not used if only some part of it is used.
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///
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/// X86 backend does not have subregister liveness tracking enabled,
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/// so liveness information might be overly conservative. However, for
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/// some specific instructions (this pass only cares about MOVs) we can
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/// produce more precise results by analysing that MOV's operands.
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///
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/// Indeed, if super-register is not live before the mov it means that it
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/// was originally <read-undef> and so we are free to modify these
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/// undef upper bits. That may happen in case where the use is in another MBB
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/// and the vreg/physreg corresponding to the move has higher width than
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/// necessary (e.g. due to register coalescing with a "truncate" copy).
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/// So, it handles pattern like this:
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///
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/// %bb.2: derived from LLVM BB %if.then
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/// Live Ins: %rdi
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/// Predecessors according to CFG: %bb.0
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/// %ax = MOV16rm killed %rdi, 1, %noreg, 0, %noreg, implicit-def %eax;
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/// mem:LD2[%p]
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/// No implicit %eax
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/// Successors according to CFG: %bb.3(?%)
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///
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/// %bb.3: derived from LLVM BB %if.end
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/// Live Ins: %eax Only %ax is actually live
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/// Predecessors according to CFG: %bb.2 %bb.1
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/// %ax = KILL %ax, implicit killed %eax
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/// RET 0, %ax
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static bool isLive(const MachineInstr &MI,
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const LivePhysRegs &LiveRegs,
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const TargetRegisterInfo *TRI,
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unsigned Reg) {
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if (!LiveRegs.contains(Reg))
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return false;
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unsigned Opc = MI.getOpcode(); (void)Opc;
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// These are the opcodes currently handled by the pass, if something
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// else will be added we need to ensure that new opcode has the same
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// properties.
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assert((Opc == X86::MOV8rm || Opc == X86::MOV16rm || Opc == X86::MOV8rr ||
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Opc == X86::MOV16rr) &&
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"Unexpected opcode.");
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bool IsDefined = false;
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for (auto &MO: MI.implicit_operands()) {
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if (!MO.isReg())
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continue;
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assert((MO.isDef() || MO.isUse()) && "Expected Def or Use only!");
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for (MCSuperRegIterator Supers(Reg, TRI, true); Supers.isValid(); ++Supers) {
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if (*Supers == MO.getReg()) {
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if (MO.isDef())
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IsDefined = true;
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else
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return true; // SuperReg Imp-used' -> live before the MI
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}
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}
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}
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// Reg is not Imp-def'ed -> it's live both before/after the instruction.
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if (!IsDefined)
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return true;
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// Otherwise, the Reg is not live before the MI and the MOV can't
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// make it really live, so it's in fact dead even after the MI.
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return false;
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}
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/// \brief Check if after \p OrigMI the only portion of super register
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/// of the destination register of \p OrigMI that is alive is that
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/// destination register.
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@ -262,20 +187,84 @@ bool FixupBWInstPass::getSuperRegDestIfDead(MachineInstr *OrigMI,
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if (SubRegIdx == X86::sub_8bit_hi)
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return false;
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if (isLive(*OrigMI, LiveRegs, TRI, SuperDestReg))
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return false;
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if (SubRegIdx == X86::sub_8bit) {
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// In the case of byte registers, we also have to check that the upper
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// byte register is also dead. That is considered to be independent of
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// whether the super-register is dead.
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unsigned UpperByteReg =
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getX86SubSuperRegister(SuperDestReg, 8, /*High=*/true);
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if (isLive(*OrigMI, LiveRegs, TRI, UpperByteReg))
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return false;
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// If neither the destination-super register nor any applicable subregisters
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// are live after this instruction, then the super register is safe to use.
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if (!LiveRegs.contains(SuperDestReg)) {
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// If the original destination register was not the low 8-bit subregister
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// then the super register check is sufficient.
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if (SubRegIdx != X86::sub_8bit)
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return true;
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// If the original destination register was the low 8-bit subregister and
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// we also need to check the 16-bit subregister and the high 8-bit
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// subregister.
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if (!LiveRegs.contains(getX86SubSuperRegister(OrigDestReg, 16)) &&
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!LiveRegs.contains(getX86SubSuperRegister(SuperDestReg, 8,
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/*High=*/true)))
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return true;
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// Otherwise, we have a little more checking to do.
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}
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// If we get here, the super-register destination (or some part of it) is
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// marked as live after the original instruction.
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//
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// The X86 backend does not have subregister liveness tracking enabled,
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// so liveness information might be overly conservative. Specifically, the
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// super register might be marked as live because it is implicitly defined
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// by the instruction we are examining.
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//
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// However, for some specific instructions (this pass only cares about MOVs)
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// we can produce more precise results by analysing that MOV's operands.
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//
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// Indeed, if super-register is not live before the mov it means that it
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// was originally <read-undef> and so we are free to modify these
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// undef upper bits. That may happen in case where the use is in another MBB
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// and the vreg/physreg corresponding to the move has higher width than
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// necessary (e.g. due to register coalescing with a "truncate" copy).
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// So, we would like to handle patterns like this:
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//
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// %bb.2: derived from LLVM BB %if.then
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// Live Ins: %rdi
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// Predecessors according to CFG: %bb.0
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// %ax<def> = MOV16rm killed %rdi, 1, %noreg, 0, %noreg, implicit-def %eax
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// ; No implicit %eax
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// Successors according to CFG: %bb.3(?%)
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//
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// %bb.3: derived from LLVM BB %if.end
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// Live Ins: %eax Only %ax is actually live
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// Predecessors according to CFG: %bb.2 %bb.1
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// %ax = KILL %ax, implicit killed %eax
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// RET 0, %ax
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unsigned Opc = OrigMI->getOpcode(); (void)Opc;
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// These are the opcodes currently handled by the pass, if something
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// else will be added we need to ensure that new opcode has the same
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// properties.
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assert((Opc == X86::MOV8rm || Opc == X86::MOV16rm || Opc == X86::MOV8rr ||
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Opc == X86::MOV16rr) &&
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"Unexpected opcode.");
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bool IsDefined = false;
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for (auto &MO: OrigMI->implicit_operands()) {
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if (!MO.isReg())
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continue;
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assert((MO.isDef() || MO.isUse()) && "Expected Def or Use only!");
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for (MCSuperRegIterator Supers(OrigDestReg, TRI, true); Supers.isValid();
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++Supers) {
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if (*Supers == MO.getReg()) {
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if (MO.isDef())
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IsDefined = true;
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else
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return false; // SuperReg Imp-used' -> live before the MI
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}
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}
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}
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// Reg is not Imp-def'ed -> it's live both before/after the instruction.
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if (!IsDefined)
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return false;
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// Otherwise, the Reg is not live before the MI and the MOV can't
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// make it really live, so it's in fact dead even after the MI.
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return true;
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}
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@ -26,6 +26,12 @@
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ret i16 %i.0
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}
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define i16 @test4() {
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entry:
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%t1 = zext i1 undef to i16
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%t2 = or i16 undef, %t1
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ret i16 %t2
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}
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...
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---
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# CHECK-LABEL: name: test1
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@ -149,3 +155,47 @@ body: |
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RETQ %ax
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...
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---
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# CHECK-LABEL: name: test4
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name: test4
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alignment: 4
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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liveins:
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- { reg: '%r9d' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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savePoint: ''
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restorePoint: ''
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fixedStack:
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stack:
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constants:
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# This code copies r10b into r9b and then uses r9w. We would like to promote
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# the copy to a 32-bit copy, but because r9w is used this is not acceptable.
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body: |
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bb.0.entry:
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successors:
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liveins: %r9d
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%r9b = MOV8rr undef %r10b, implicit-def %r9d, implicit killed %r9d, implicit-def %eflags
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; CHECK-NOT: MOV32rr
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%ax = OR16rr undef %ax, %r9w, implicit-def %eflags
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RETQ %ax
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...
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