mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2025-01-31 20:51:52 +01:00
CMake: Builds all targets.
llvm-svn: 56641
This commit is contained in:
Oscar Fuentes
parent
37bd5a0d40
commit
65859a84d0
@ -13,8 +13,14 @@ set(LLVM_BINARY_DIR ${CMAKE_CURRENT_BINARY_DIR})
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set(LLVM_TOOLS_BINARY_DIR ${LLVM_BINARY_DIR}/bin)
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set(LLVM_EXAMPLES_BINARY_DIR ${LLVM_BINARY_DIR}/examples)
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# TODO: Support user-specified targets:
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set(LLVM_TARGETS_TO_BUILD X86)
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if( MSVC )
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set(LLVM_TARGETS_TO_BUILD X86
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CACHE STRING "Semicolon-separated list of targets to build")
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else( MSVC )
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set(LLVM_TARGETS_TO_BUILD
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Alpha ARM CBackend CellSPU CppBackend IA64 Mips MSIL PIC16 PowerPC Sparc X86
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CACHE STRING "Semicolon-separated list of targets to build")
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endif( MSVC )
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if( NOT MSVC )
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set(CMAKE_CXX_LINK_EXECUTABLE "sh -c \"${CMAKE_CXX_LINK_EXECUTABLE}\"")
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@ -96,6 +102,7 @@ include_directories( ${LLVM_BINARY_DIR}/include ${llvm_include_path})
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include(AddLLVM)
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include(AddPartiallyLinkedObject)
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include(TableGen)
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add_subdirectory(lib/Support)
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add_subdirectory(lib/System)
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@ -129,15 +136,21 @@ add_subdirectory(lib/Transforms/Hello)
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add_subdirectory(lib/Linker)
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add_subdirectory(lib/Analysis)
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add_subdirectory(lib/Analysis/IPA)
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add_subdirectory(lib/Target/X86)
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add_subdirectory(lib/Target/X86/AsmPrinter)
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foreach(t ${LLVM_TARGETS_TO_BUILD})
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message(STATUS "Targeting ${t}")
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add_subdirectory(lib/Target/${t})
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if( EXISTS ${CMAKE_SOURCE_DIR}/lib/Target/${t}/AsmPrinter/CMakeLists.txt )
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add_subdirectory(lib/Target/${t}/AsmPrinter)
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endif( EXISTS ${CMAKE_SOURCE_DIR}/lib/Target/${t}/AsmPrinter/CMakeLists.txt )
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endforeach(t)
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add_subdirectory(lib/ExecutionEngine)
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add_subdirectory(lib/ExecutionEngine/Interpreter)
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add_subdirectory(lib/ExecutionEngine/JIT)
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add_subdirectory(lib/Target)
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add_subdirectory(lib/AsmParser)
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add_subdirectory(lib/Debugger)
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# TODO: lib/Target/CBackEnd
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add_subdirectory(lib/Archive)
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add_subdirectory(tools)
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@ -41,3 +41,17 @@ macro(add_llvm_example name)
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# set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${LLVM_EXAMPLES_BINARY_DIR})
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add_llvm_executable(${name} ${ARGN})
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endmacro(add_llvm_example name)
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macro(add_llvm_target target_name)
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if( TABLEGEN_OUTPUT )
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add_custom_target(${target_name}Table_gen
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DEPENDS ${TABLEGEN_OUTPUT})
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add_dependencies(${target_name}Table_gen ${LLVM_COMMON_DEPENDS})
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endif( TABLEGEN_OUTPUT )
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include_directories(BEFORE ${CMAKE_CURRENT_BINARY_DIR})
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add_partially_linked_object(LLVM${target_name} ${ARGN})
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if( TABLEGEN_OUTPUT )
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add_dependencies(LLVM${target_name} ${target_name}Table_gen)
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endif( TABLEGEN_OUTPUT )
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endmacro(add_llvm_target)
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12
cmake/modules/TableGen.cmake
Normal file
12
cmake/modules/TableGen.cmake
Normal file
@ -0,0 +1,12 @@
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# LLVM_TARGET_DEFINITIONS must contain the name of the .td file to process.
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# Extra parameters for `tblgen' may come after `ofn' parameter.
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# Adds the name of the generated file to TABLEGEN_OUTPUT.
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macro(tablegen ofn)
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add_custom_command(OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${ofn}
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COMMAND tblgen ${ARGN} -I ${CMAKE_CURRENT_SOURCE_DIR} -I ${CMAKE_SOURCE_DIR}/lib/Target -I ${llvm_include_path} ${CMAKE_CURRENT_SOURCE_DIR}/${LLVM_TARGET_DEFINITIONS} -o ${ofn}
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DEPENDS tblgen ${CMAKE_CURRENT_SOURCE_DIR}/${LLVM_TARGET_DEFINITIONS}
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COMMENT "Building ${ofn}..."
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)
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set(TABLEGEN_OUTPUT ${TABLEGEN_OUTPUT} ${CMAKE_CURRENT_BINARY_DIR}/${ofn})
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endmacro(tablegen)
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26
lib/Target/ARM/CMakeLists.txt
Normal file
26
lib/Target/ARM/CMakeLists.txt
Normal file
@ -0,0 +1,26 @@
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set(LLVM_TARGET_DEFINITIONS ARM.td)
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tablegen(ARMGenRegisterInfo.h.inc -gen-register-desc-header)
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tablegen(ARMGenRegisterNames.inc -gen-register-enums)
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tablegen(ARMGenRegisterInfo.inc -gen-register-desc)
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tablegen(ARMGenInstrNames.inc -gen-instr-enums)
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tablegen(ARMGenInstrInfo.inc -gen-instr-desc)
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tablegen(ARMGenCodeEmitter.inc -gen-emitter)
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tablegen(ARMGenAsmWriter.inc -gen-asm-writer)
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tablegen(ARMGenDAGISel.inc -gen-dag-isel)
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tablegen(ARMGenSubtarget.inc -gen-subtarget)
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add_llvm_target(ARM
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ARMCodeEmitter.cpp
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ARMConstantIslandPass.cpp
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ARMConstantPoolValue.cpp
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ARMInstrInfo.cpp
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ARMISelDAGToDAG.cpp
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ARMISelLowering.cpp
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ARMJITInfo.cpp
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ARMLoadStoreOptimizer.cpp
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ARMRegisterInfo.cpp
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ARMSubtarget.cpp
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ARMTargetAsmInfo.cpp
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ARMTargetMachine.cpp
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)
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26
lib/Target/Alpha/CMakeLists.txt
Normal file
26
lib/Target/Alpha/CMakeLists.txt
Normal file
@ -0,0 +1,26 @@
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set(LLVM_TARGET_DEFINITIONS Alpha.td)
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tablegen(AlphaGenRegisterInfo.h.inc -gen-register-desc-header)
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tablegen(AlphaGenRegisterNames.inc -gen-register-enums)
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tablegen(AlphaGenRegisterInfo.inc -gen-register-desc)
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tablegen(AlphaGenInstrNames.inc -gen-instr-enums)
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tablegen(AlphaGenInstrInfo.inc -gen-instr-desc)
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tablegen(AlphaGenCodeEmitter.inc -gen-emitter)
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tablegen(AlphaGenAsmWriter.inc -gen-asm-writer)
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tablegen(AlphaGenDAGISel.inc -gen-dag-isel)
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tablegen(AlphaGenSubtarget.inc -gen-subtarget)
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add_llvm_target(Alpha
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AlphaAsmPrinter.cpp
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AlphaBranchSelector.cpp
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AlphaCodeEmitter.cpp
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AlphaInstrInfo.cpp
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AlphaISelDAGToDAG.cpp
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AlphaISelLowering.cpp
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AlphaJITInfo.cpp
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AlphaLLRP.cpp
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AlphaRegisterInfo.cpp
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AlphaSubtarget.cpp
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AlphaTargetAsmInfo.cpp
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AlphaTargetMachine.cpp
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)
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3
lib/Target/CBackend/CMakeLists.txt
Normal file
3
lib/Target/CBackend/CMakeLists.txt
Normal file
@ -0,0 +1,3 @@
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add_llvm_target(CBackEnd
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CBackend.cpp
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)
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25
lib/Target/CellSPU/CMakeLists.txt
Normal file
25
lib/Target/CellSPU/CMakeLists.txt
Normal file
@ -0,0 +1,25 @@
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set(LLVM_TARGET_DEFINITIONS SPU.td)
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tablegen(SPUGenInstrNames.inc -gen-instr-enums)
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tablegen(SPUGenRegisterNames.inc -gen-register-enums)
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tablegen(SPUGenAsmWriter.inc -gen-asm-writer)
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tablegen(SPUGenCodeEmitter.inc -gen-emitter)
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tablegen(SPUGenRegisterInfo.h.inc -gen-register-desc-header)
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tablegen(SPUGenRegisterInfo.inc -gen-register-desc)
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tablegen(SPUGenInstrInfo.inc -gen-instr-desc)
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tablegen(SPUGenDAGISel.inc -gen-dag-isel)
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tablegen(SPUGenSubtarget.inc -gen-subtarget)
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tablegen(SPUGenCallingConv.inc -gen-callingconv)
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add_llvm_target(CellSPU
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SPUAsmPrinter.cpp
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SPUFrameInfo.cpp
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SPUHazardRecognizers.cpp
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SPUInstrInfo.cpp
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SPUISelDAGToDAG.cpp
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SPUISelLowering.cpp
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SPURegisterInfo.cpp
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SPUSubtarget.cpp
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SPUTargetAsmInfo.cpp
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SPUTargetMachine.cpp
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)
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3
lib/Target/CppBackend/CMakeLists.txt
Normal file
3
lib/Target/CppBackend/CMakeLists.txt
Normal file
@ -0,0 +1,3 @@
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add_llvm_target(CppBackend
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CPPBackend.cpp
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)
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20
lib/Target/IA64/CMakeLists.txt
Normal file
20
lib/Target/IA64/CMakeLists.txt
Normal file
@ -0,0 +1,20 @@
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set(LLVM_TARGET_DEFINITIONS IA64.td)
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tablegen(IA64GenRegisterInfo.h.inc -gen-register-desc-header)
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tablegen(IA64GenRegisterNames.inc -gen-register-enums)
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tablegen(IA64GenRegisterInfo.inc -gen-register-desc)
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tablegen(IA64GenInstrNames.inc -gen-instr-enums)
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tablegen(IA64GenInstrInfo.inc -gen-instr-desc)
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tablegen(IA64GenAsmWriter.inc -gen-asm-writer)
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tablegen(IA64GenDAGISel.inc -gen-dag-isel)
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add_llvm_target(IA64
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IA64AsmPrinter.cpp
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IA64Bundling.cpp
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IA64InstrInfo.cpp
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IA64ISelDAGToDAG.cpp
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IA64ISelLowering.cpp
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IA64RegisterInfo.cpp
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IA64TargetAsmInfo.cpp
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IA64TargetMachine.cpp
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)
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3
lib/Target/MSIL/CMakeLists.txt
Normal file
3
lib/Target/MSIL/CMakeLists.txt
Normal file
@ -0,0 +1,3 @@
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add_llvm_target(MSIL
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MSILWriter.cpp
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)
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23
lib/Target/Mips/CMakeLists.txt
Normal file
23
lib/Target/Mips/CMakeLists.txt
Normal file
@ -0,0 +1,23 @@
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set(LLVM_TARGET_DEFINITIONS Mips.td)
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tablegen(MipsGenRegisterInfo.h.inc -gen-register-desc-header)
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tablegen(MipsGenRegisterNames.inc -gen-register-enums)
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tablegen(MipsGenRegisterInfo.inc -gen-register-desc)
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tablegen(MipsGenInstrNames.inc -gen-instr-enums)
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tablegen(MipsGenInstrInfo.inc -gen-instr-desc)
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tablegen(MipsGenAsmWriter.inc -gen-asm-writer)
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tablegen(MipsGenDAGISel.inc -gen-dag-isel)
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tablegen(MipsGenCallingConv.inc -gen-callingconv)
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tablegen(MipsGenSubtarget.inc -gen-subtarget)
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add_llvm_target(Mips
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MipsAsmPrinter.cpp
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MipsDelaySlotFiller.cpp
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MipsInstrInfo.cpp
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MipsISelDAGToDAG.cpp
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MipsISelLowering.cpp
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MipsRegisterInfo.cpp
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MipsSubtarget.cpp
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MipsTargetAsmInfo.cpp
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MipsTargetMachine.cpp
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)
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23
lib/Target/PIC16/CMakeLists.txt
Normal file
23
lib/Target/PIC16/CMakeLists.txt
Normal file
@ -0,0 +1,23 @@
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set(LLVM_TARGET_DEFINITIONS PIC16.td)
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tablegen(PIC16GenRegisterInfo.h.inc -gen-register-desc-header)
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tablegen(PIC16GenRegisterNames.inc -gen-register-enums)
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tablegen(PIC16GenRegisterInfo.inc -gen-register-desc)
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tablegen(PIC16GenInstrNames.inc -gen-instr-enums)
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tablegen(PIC16GenInstrInfo.inc -gen-instr-desc)
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tablegen(PIC16GenAsmWriter.inc -gen-asm-writer)
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tablegen(PIC16GenDAGISel.inc -gen-dag-isel)
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tablegen(PIC16GenCallingConv.inc -gen-callingconv)
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tablegen(PIC16GenSubtarget.inc -gen-subtarget)
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add_llvm_target(PIC16
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PIC16AsmPrinter.cpp
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PIC16ConstantPoolValue.cpp
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PIC16InstrInfo.cpp
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PIC16ISelDAGToDAG.cpp
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PIC16ISelLowering.cpp
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PIC16RegisterInfo.cpp
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PIC16Subtarget.cpp
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PIC16TargetAsmInfo.cpp
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PIC16TargetMachine.cpp
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)
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9
lib/Target/PowerPC/AsmPrinter/CMakeLists.txt
Normal file
9
lib/Target/PowerPC/AsmPrinter/CMakeLists.txt
Normal file
@ -0,0 +1,9 @@
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include_directories( ${CMAKE_CURRENT_BINARY_DIR}/.. ${CMAKE_CURRENT_SOURCE_DIR}/.. )
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add_llvm_library(LLVMPowerPCAsmPrinter
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PPCAsmPrinter.cpp
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)
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target_name_of_partially_linked_object(LLVMPowerPCCodeGen n)
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add_dependencies(LLVMPowerPCAsmPrinter ${n})
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28
lib/Target/PowerPC/CMakeLists.txt
Normal file
28
lib/Target/PowerPC/CMakeLists.txt
Normal file
@ -0,0 +1,28 @@
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set(LLVM_TARGET_DEFINITIONS PPC.td)
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tablegen(PPCGenInstrNames.inc -gen-instr-enums)
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tablegen(PPCGenRegisterNames.inc -gen-register-enums)
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tablegen(PPCGenAsmWriter.inc -gen-asm-writer)
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tablegen(PPCGenCodeEmitter.inc -gen-emitter)
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tablegen(PPCGenRegisterInfo.h.inc -gen-register-desc-header)
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tablegen(PPCGenRegisterInfo.inc -gen-register-desc)
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tablegen(PPCGenInstrInfo.inc -gen-instr-desc)
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tablegen(PPCGenDAGISel.inc -gen-dag-isel)
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tablegen(PPCGenCallingConv.inc -gen-callingconv)
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tablegen(PPCGenSubtarget.inc -gen-subtarget)
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add_llvm_target(PowerPCCodeGen
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PPCBranchSelector.cpp
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PPCCodeEmitter.cpp
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PPCHazardRecognizers.cpp
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PPCInstrInfo.cpp
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PPCISelDAGToDAG.cpp
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PPCISelLowering.cpp
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PPCJITInfo.cpp
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PPCMachOWriterInfo.cpp
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PPCPredicates.cpp
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PPCRegisterInfo.cpp
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PPCSubtarget.cpp
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PPCTargetAsmInfo.cpp
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PPCTargetMachine.cpp
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)
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24
lib/Target/Sparc/CMakeLists.txt
Normal file
24
lib/Target/Sparc/CMakeLists.txt
Normal file
@ -0,0 +1,24 @@
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set(LLVM_TARGET_DEFINITIONS Sparc.td)
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tablegen(SparcGenRegisterInfo.h.inc -gen-register-desc-header)
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tablegen(SparcGenRegisterNames.inc -gen-register-enums)
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tablegen(SparcGenRegisterInfo.inc -gen-register-desc)
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tablegen(SparcGenInstrNames.inc -gen-instr-enums)
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tablegen(SparcGenInstrInfo.inc -gen-instr-desc)
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tablegen(SparcGenAsmWriter.inc -gen-asm-writer)
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tablegen(SparcGenDAGISel.inc -gen-dag-isel)
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tablegen(SparcGenSubtarget.inc -gen-subtarget)
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tablegen(SparcGenCallingConv.inc -gen-callingconv)
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add_llvm_target(Sparc
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DelaySlotFiller.cpp
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FPMover.cpp
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SparcAsmPrinter.cpp
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SparcInstrInfo.cpp
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SparcISelDAGToDAG.cpp
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SparcISelLowering.cpp
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SparcRegisterInfo.cpp
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SparcSubtarget.cpp
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SparcTargetAsmInfo.cpp
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SparcTargetMachine.cpp
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)
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@ -1,43 +1,18 @@
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macro(x86tgen ofn)
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add_custom_command(OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${ofn}
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COMMAND tblgen ${ARGN} -I ${CMAKE_CURRENT_SOURCE_DIR} -I ${CMAKE_SOURCE_DIR}/lib/Target -I ${llvm_include_path} ${CMAKE_CURRENT_SOURCE_DIR}/X86.td -o ${ofn}
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DEPENDS tblgen ${CMAKE_CURRENT_SOURCE_DIR}/X86.td
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COMMENT "Building ${ofn}..."
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)
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endmacro(x86tgen)
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set(LLVM_TARGET_DEFINITIONS X86.td)
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x86tgen(X86GenRegisterInfo.h.inc -gen-register-desc-header)
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x86tgen(X86GenRegisterNames.inc -gen-register-enums)
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x86tgen(X86GenRegisterInfo.inc -gen-register-desc)
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x86tgen(X86GenInstrNames.inc -gen-instr-enums)
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x86tgen(X86GenInstrInfo.inc -gen-instr-desc)
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x86tgen(X86GenAsmWriter.inc -gen-asm-writer)
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x86tgen(X86GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1)
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x86tgen(X86GenDAGISel.inc -gen-dag-isel)
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x86tgen(X86GenFastISel.inc -gen-fast-isel)
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x86tgen(X86GenCallingConv.inc -gen-callingconv)
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x86tgen(X86GenSubtarget.inc -gen-subtarget)
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tablegen(X86GenRegisterInfo.h.inc -gen-register-desc-header)
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tablegen(X86GenRegisterNames.inc -gen-register-enums)
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tablegen(X86GenRegisterInfo.inc -gen-register-desc)
|
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tablegen(X86GenInstrNames.inc -gen-instr-enums)
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tablegen(X86GenInstrInfo.inc -gen-instr-desc)
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tablegen(X86GenAsmWriter.inc -gen-asm-writer)
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tablegen(X86GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1)
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tablegen(X86GenDAGISel.inc -gen-dag-isel)
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tablegen(X86GenFastISel.inc -gen-fast-isel)
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tablegen(X86GenCallingConv.inc -gen-callingconv)
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tablegen(X86GenSubtarget.inc -gen-subtarget)
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add_custom_target(X86Table_gen echo Tablegenning
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DEPENDS
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${CMAKE_CURRENT_BINARY_DIR}/X86GenRegisterInfo.h.inc
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${CMAKE_CURRENT_BINARY_DIR}/X86GenRegisterNames.inc
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${CMAKE_CURRENT_BINARY_DIR}/X86GenRegisterInfo.inc
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${CMAKE_CURRENT_BINARY_DIR}/X86GenInstrNames.inc
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${CMAKE_CURRENT_BINARY_DIR}/X86GenInstrInfo.inc
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${CMAKE_CURRENT_BINARY_DIR}/X86GenAsmWriter.inc
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${CMAKE_CURRENT_BINARY_DIR}/X86GenAsmWriter1.inc
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${CMAKE_CURRENT_BINARY_DIR}/X86GenDAGISel.inc
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${CMAKE_CURRENT_BINARY_DIR}/X86GenFastISel.inc
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||||
${CMAKE_CURRENT_BINARY_DIR}/X86GenCallingConv.inc
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${CMAKE_CURRENT_BINARY_DIR}/X86GenSubtarget.inc
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)
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add_dependencies(X86Table_gen ${LLVM_COMMON_DEPENDS})
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||||
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include_directories(BEFORE ${CMAKE_CURRENT_BINARY_DIR})
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|
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add_partially_linked_object(LLVMX86CodeGen
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add_llvm_target(X86CodeGen
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X86CodeEmitter.cpp
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||||
X86ELFWriterInfo.cpp
|
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X86FloatingPoint.cpp
|
||||
@ -51,7 +26,3 @@ add_partially_linked_object(LLVMX86CodeGen
|
||||
X86TargetMachine.cpp
|
||||
X86FastISel.cpp
|
||||
)
|
||||
|
||||
add_dependencies(LLVMX86CodeGen
|
||||
X86Table_gen
|
||||
)
|
||||
|
||||
@ -40,7 +40,10 @@ if( NOT TT_RV EQUAL 0 )
|
||||
message(FATAL_ERROR "Failed to execute ${config_guess}")
|
||||
endif( NOT TT_RV EQUAL 0 )
|
||||
set(target ${LLVM_TARGET_TRIPLET})
|
||||
set(TARGETS_TO_BUILD "X86") # TODO
|
||||
foreach(c ${LLVM_TARGETS_TO_BUILD})
|
||||
set(TARGETS_BUILT "${TARGETS_BUILT} ${c}")
|
||||
endforeach(c)
|
||||
set(TARGETS_TO_BUILD ${TARGETS_BUILT})
|
||||
set(TARGET_HAS_JIT "1") # TODO
|
||||
|
||||
# Avoids replacement at config-time:
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user