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[RISCV] Add a test showing an incorrect vsetvli insertion

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This patch adds a reduced test case which identifies an illegal vsetvli
inserted by the compiler. The compiler emits a vsetvli which is intended
to preserve VL with the SEW/LMUL ratio e32/m1 when in fact the VL could
have been set by e64/m2 in a predecessor block.

Differential Revision: https://reviews.llvm.org/D106286
This commit is contained in:
Fraser Cormack 2021-07-23 09:16:08 -07:00 committed by Craig Topper
parent cf4b05e2f6
commit 65b887fbf8
1 changed files with 22 additions and 0 deletions
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test/CodeGen/RISCV/rvv/vsetvli-regression.ll Normal file
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=riscv64 -mattr=+experimental-v | FileCheck %s
; This test checks a regression in the vsetvli insertion pass. We used to
; prserve the VL on the second vsetvli with ratio e32/m1, when the the last
; update of VL was the vsetvli with e64/m4. Changing VTYPE here changes VLMAX
; which may make the original VL invalid. Instead of preserving it we use 0.
define i32 @illegal_preserve_vl(<vscale x 2 x i32> %a, <vscale x 4 x i64> %x, <vscale x 4 x i64>* %y) {
; CHECK-LABEL: illegal_preserve_vl:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, mu
; CHECK-NEXT: vadd.vv v28, v12, v12
; CHECK-NEXT: vs4r.v v28, (a0)
; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, mu
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
%index = add <vscale x 4 x i64> %x, %x
store <vscale x 4 x i64> %index, <vscale x 4 x i64>* %y
%elt = extractelement <vscale x 2 x i32> %a, i64 0
ret i32 %elt
}