From 65e46aa23bebd409b2e7b056f12c7a88738a8a54 Mon Sep 17 00:00:00 2001 From: Krzysztof Parzyszek Date: Wed, 3 Feb 2021 10:25:44 -0600 Subject: [PATCH] [Hexagon] Add LLVM instruction definitions for Hexagon V68 --- include/llvm/IR/IntrinsicsHexagonDep.td | 9356 +++++++++-------- lib/Target/Hexagon/Hexagon.td | 12 +- lib/Target/Hexagon/HexagonDepArch.h | 71 +- lib/Target/Hexagon/HexagonDepArch.td | 2 + lib/Target/Hexagon/HexagonDepDecoders.inc | 51 +- lib/Target/Hexagon/HexagonDepIICHVX.td | 863 +- lib/Target/Hexagon/HexagonDepIICScalar.td | 1467 +-- lib/Target/Hexagon/HexagonDepITypes.h | 90 +- lib/Target/Hexagon/HexagonDepITypes.td | 84 +- lib/Target/Hexagon/HexagonDepInstrFormats.td | 7031 ++++++------- lib/Target/Hexagon/HexagonDepInstrInfo.td | 415 +- lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td | 5900 +++++------ lib/Target/Hexagon/HexagonDepMappings.td | 2 + lib/Target/Hexagon/HexagonDepMask.h | 3 +- lib/Target/Hexagon/HexagonDepOperands.td | 180 +- lib/Target/Hexagon/HexagonDepTimingClasses.h | 20 +- lib/Target/Hexagon/HexagonSchedule.td | 1 + lib/Target/Hexagon/HexagonScheduleV68.td | 38 + lib/Target/Hexagon/HexagonSubtarget.h | 9 + .../MCTargetDesc/HexagonMCTargetDesc.cpp | 21 +- 20 files changed, 13111 insertions(+), 12505 deletions(-) create mode 100644 lib/Target/Hexagon/HexagonScheduleV68.td diff --git a/include/llvm/IR/IntrinsicsHexagonDep.td b/include/llvm/IR/IntrinsicsHexagonDep.td index 198b6a7ab0d..6799273bf80 100644 --- a/include/llvm/IR/IntrinsicsHexagonDep.td +++ b/include/llvm/IR/IntrinsicsHexagonDep.td @@ -8,28 +8,126 @@ // Automatically generated file, do not edit! //===----------------------------------------------------------------------===// -// tag : C2_cmpeq -class Hexagon_i32_i32i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : C2_cmpeqp -class Hexagon_i32_i64i64_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : C2_not +// tag : A2_abs class Hexagon_i32_i32_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : C4_and_and +// tag : A2_absp +class Hexagon_i64_i64_Intrinsic intr_properties = [IntrNoMem]> + : Hexagon_Intrinsic; + +// tag : A2_add +class Hexagon_custom_i32_i32i32_Intrinsic< + list intr_properties = [IntrNoMem]> + : Hexagon_NonGCC_Intrinsic< + [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty], + intr_properties>; + +// tag : A2_addh_h16_hh +class Hexagon_i32_i32i32_Intrinsic intr_properties = [IntrNoMem]> + : Hexagon_Intrinsic; + +// tag : A2_addp +class Hexagon_custom_i64_i64i64_Intrinsic< + list intr_properties = [IntrNoMem]> + : Hexagon_NonGCC_Intrinsic< + [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty], + intr_properties>; + +// tag : A2_addpsat +class Hexagon_i64_i64i64_Intrinsic intr_properties = [IntrNoMem]> + : Hexagon_Intrinsic; + +// tag : A2_addsp +class Hexagon_i64_i32i64_Intrinsic intr_properties = [IntrNoMem]> + : Hexagon_Intrinsic; + +// tag : A2_combineii +class Hexagon_i64_i32i32_Intrinsic intr_properties = [IntrNoMem]> + : Hexagon_Intrinsic; + +// tag : A2_neg +class Hexagon_custom_i32_i32_Intrinsic< + list intr_properties = [IntrNoMem]> + : Hexagon_NonGCC_Intrinsic< + [llvm_i32_ty], [llvm_i32_ty], + intr_properties>; + +// tag : A2_roundsat +class Hexagon_i32_i64_Intrinsic intr_properties = [IntrNoMem]> + : Hexagon_Intrinsic; + +// tag : A2_sxtw +class Hexagon_i64_i32_Intrinsic intr_properties = [IntrNoMem]> + : Hexagon_Intrinsic; + +// tag : A2_vcmpbeq +class Hexagon_i32_i64i64_Intrinsic intr_properties = [IntrNoMem]> + : Hexagon_Intrinsic; + +// tag : A2_vraddub_acc +class Hexagon_i64_i64i64i64_Intrinsic intr_properties = [IntrNoMem]> + : Hexagon_Intrinsic; + +// tag : A4_boundscheck +class Hexagon_i32_i32i64_Intrinsic intr_properties = [IntrNoMem]> + : Hexagon_Intrinsic; + +// tag : A4_tlbmatch +class Hexagon_i32_i64i32_Intrinsic intr_properties = [IntrNoMem]> + : Hexagon_Intrinsic; + +// tag : A4_vrmaxh +class Hexagon_i64_i64i64i32_Intrinsic intr_properties = [IntrNoMem]> + : Hexagon_Intrinsic; + +// tag : A7_croundd_ri +class Hexagon_i64_i64i32_Intrinsic intr_properties = [IntrNoMem]> + : Hexagon_Intrinsic; + +// tag : C2_mux class Hexagon_i32_i32i32i32_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : C2_mask -class Hexagon_i64_i32_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : A4_vcmpbeqi -class Hexagon_i32_i64i32_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : A4_boundscheck -class Hexagon_i32_i32i64_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : M2_mpyd_acc_hh_s0 -class Hexagon_i64_i64i32i32_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : M2_mpyd_hh_s0 -class Hexagon_i64_i32i32_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : M2_vmpy2es_s0 -class Hexagon_i64_i64i64_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : M2_vmac2es_s0 -class Hexagon_i64_i64i64i64_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : M2_vrcmpys_s1 -class Hexagon_i64_i64i32_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : M2_vrcmpys_acc_s1 -class Hexagon_i64_i64i64i32_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : S4_vrcrotate_acc -class Hexagon_i64_i64i64i32i32_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : A2_addsp -class Hexagon_i64_i32i64_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : A2_vconj -class Hexagon_i64_i64_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : A2_sat -class Hexagon_i32_i64_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; + +// tag : F2_dfmpyhh +class Hexagon_double_doubledoubledouble_Intrinsic intr_properties = [IntrNoMem]> + : Hexagon_Intrinsic; // tag : F2_sfadd @@ -141,6 +246,27 @@ class Hexagon_float_floatfloat_Intrinsic; +// tag : F2_sfclass +class Hexagon_i32_floati32_Intrinsic intr_properties = [IntrNoMem]> + : Hexagon_Intrinsic; + +// tag : F2_sfcmpeq +class Hexagon_i32_floatfloat_Intrinsic intr_properties = [IntrNoMem]> + : Hexagon_Intrinsic; + +// tag : F2_sffixupr +class Hexagon_float_float_Intrinsic intr_properties = [IntrNoMem]> + : Hexagon_Intrinsic; + // tag : F2_sffma class Hexagon_float_floatfloatfloat_Intrinsic intr_properties = [IntrNoMem]> @@ -155,123 +281,25 @@ class Hexagon_float_floatfloatfloati32_Intrinsic; -// tag : F2_sfcmpeq -class Hexagon_i32_floatfloat_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : F2_sfclass -class Hexagon_i32_floati32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; -// tag : F2_sfimm_p -class Hexagon_float_i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : F2_sffixupr -class Hexagon_float_float_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : F2_dfadd -class Hexagon_double_doubledouble_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : F2_dfmpylh -class Hexagon_double_doubledoubledouble_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : F2_dfcmpeq -class Hexagon_i32_doubledouble_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : F2_dfclass -class Hexagon_i32_doublei32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : F2_dfimm_p -class Hexagon_double_i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : F2_conv_sf2df -class Hexagon_double_float_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : F2_conv_df2sf -class Hexagon_float_double_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : F2_conv_ud2sf -class Hexagon_float_i64_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : F2_conv_ud2df -class Hexagon_double_i64_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : F2_conv_sf2uw -class Hexagon_i32_float_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : F2_conv_sf2ud -class Hexagon_i64_float_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : F2_conv_df2uw -class Hexagon_i32_double_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : F2_conv_df2ud -class Hexagon_i64_double_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; // tag : S2_insert @@ -288,389 +316,186 @@ class Hexagon_i32_i32i32i64_Intrinsic; -// tag : Y2_dcfetch -class Hexagon__ptr_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : Y4_l2fetch -class Hexagon__ptri32_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : Y5_l2fetch -class Hexagon__ptri64_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : -class Hexagon_v32i32_v32i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : -class Hexagon_v64i32_v64i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : -class Hexagon_v32i32__Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : -class Hexagon_v64i32__Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : +// tag : V6_extractw class Hexagon_i32_v32i32i32_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : -class Hexagon_v32i32_v32i32i64_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : -class Hexagon_i64_v32i32i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : -class Hexagon_v64i32_v32i32v32i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : -class Hexagon_v32i32_i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : -class Hexagon_v64i32_i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : -class Hexagon_v64i32_i64_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : -class Hexagon_v32i32_v32i32v32i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : -class Hexagon_v32i32_v32i32i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : -class Hexagon_v64i32_v64i32i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : -class Hexagon_v64i32_v64i32v64i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : -class Hexagon_v64i32_v32i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : +// tag : V6_hi class Hexagon_v32i32_v64i32_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : -class Hexagon_v4i32_v32i32v32i32_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : -class Hexagon_v4i32_v32i32i32_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : -class Hexagon_v32i32_v4i32v32i32v32i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; -// tag : -class Hexagon_v64i32_v8i32v64i32v64i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; -// tag : -class Hexagon_v32i32_v64i32i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; -// tag : -class Hexagon_v32i32_v64i32v64i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; -// tag : +// tag : V6_pred_scalar2 +class Hexagon_custom_v64i1_i32_Intrinsic< + list intr_properties = [IntrNoMem]> + : Hexagon_NonGCC_Intrinsic< + [llvm_v64i1_ty], [llvm_i32_ty], + intr_properties>; + +// tag : V6_pred_scalar2 +class Hexagon_custom_v128i1_i32_Intrinsic_128B< + list intr_properties = [IntrNoMem]> + : Hexagon_NonGCC_Intrinsic< + [llvm_v128i1_ty], [llvm_i32_ty], + intr_properties>; + +// tag : V6_v6mpyhubs10 class Hexagon_v32i32_v32i32v32i32i32_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : -class Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : -class Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : -class Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : -class Hexagon_v32i32_v32i32v64i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : -class Hexagon_v64i32_v64i32v4i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : +// tag : V6_v6mpyhubs10 class Hexagon_v64i32_v64i32v64i32i32_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : -class Hexagon_v64i32_v32i32v32i32i32_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : -class Hexagon_v32i32_v32i32v32i32i64_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : -class Hexagon_v64i32_v64i32v32i32v32i32i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : -class Hexagon_v64i32_v64i32v32i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : V6_vS32b_qpred_ai +// tag : V6_vS32b_nqpred_ai class Hexagon_custom__v64i1ptrv16i32_Intrinsic< list intr_properties = [IntrNoMem]> : Hexagon_NonGCC_Intrinsic< [], [llvm_v64i1_ty,llvm_ptr_ty,llvm_v16i32_ty], intr_properties>; -// tag : V6_vS32b_qpred_ai +// tag : V6_vS32b_nqpred_ai class Hexagon_custom__v128i1ptrv32i32_Intrinsic_128B< list intr_properties = [IntrNoMem]> : Hexagon_NonGCC_Intrinsic< [], [llvm_v128i1_ty,llvm_ptr_ty,llvm_v32i32_ty], intr_properties>; -// tag : V6_valignb -class Hexagon_v16i32_v16i32v16i32i32_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : V6_vror -class Hexagon_v16i32_v16i32i32_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : V6_vunpackub -class Hexagon_v32i32_v16i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : V6_vunpackob -class Hexagon_v32i32_v32i32v16i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : V6_vpackeb +// tag : V6_vabsdiffh class Hexagon_v16i32_v16i32v16i32_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : V6_vdmpyhvsat_acc -class Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : V6_vdmpyhisat -class Hexagon_v16i32_v32i32i32_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : V6_vdmpyhisat_acc -class Hexagon_v16i32_v16i32v32i32i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : V6_vdmpyhisat_acc -class Hexagon_v32i32_v32i32v64i32i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : V6_vrmpyubi -class Hexagon_v32i32_v32i32i32i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : V6_vrmpyubi -class Hexagon_v64i32_v64i32i32i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : V6_vrmpyubi_acc -class Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : V6_vrmpyubi_acc -class Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : V6_vasr_into -class Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : V6_vaddcarrysat -class Hexagon_custom_v16i32_v16i32v16i32v64i1_Intrinsic< +// tag : V6_vaddbnq +class Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic< list intr_properties = [IntrNoMem]> : Hexagon_NonGCC_Intrinsic< - [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v64i1_ty], + [llvm_v16i32_ty], [llvm_v64i1_ty,llvm_v16i32_ty,llvm_v16i32_ty], intr_properties>; -// tag : V6_vaddcarrysat -class Hexagon_custom_v32i32_v32i32v32i32v128i1_Intrinsic_128B< +// tag : V6_vaddbnq +class Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B< list intr_properties = [IntrNoMem]> : Hexagon_NonGCC_Intrinsic< - [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v128i1_ty], + [llvm_v32i32_ty], [llvm_v128i1_ty,llvm_v32i32_ty,llvm_v32i32_ty], intr_properties>; // tag : V6_vaddcarry @@ -687,97 +512,97 @@ class Hexagon_custom_v32i32v128i1_v32i32v32i32v128i1_Intrinsic_128B< [llvm_v32i32_ty,llvm_v128i1_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v128i1_ty], intr_properties>; -// tag : V6_vaddubh +// tag : V6_vaddcarrysat +class Hexagon_custom_v16i32_v16i32v16i32v64i1_Intrinsic< + list intr_properties = [IntrNoMem]> + : Hexagon_NonGCC_Intrinsic< + [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v64i1_ty], + intr_properties>; + +// tag : V6_vaddcarrysat +class Hexagon_custom_v32i32_v32i32v32i32v128i1_Intrinsic_128B< + list intr_properties = [IntrNoMem]> + : Hexagon_NonGCC_Intrinsic< + [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v128i1_ty], + intr_properties>; + +// tag : V6_vaddhw class Hexagon_v32i32_v16i32v16i32_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : V6_vd0 -class Hexagon_v16i32__Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : V6_vaddbq -class Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic< - list intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< - [llvm_v16i32_ty], [llvm_v64i1_ty,llvm_v16i32_ty,llvm_v16i32_ty], - intr_properties>; - -// tag : V6_vaddbq -class Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B< - list intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< - [llvm_v32i32_ty], [llvm_v128i1_ty,llvm_v32i32_ty,llvm_v32i32_ty], - intr_properties>; - -// tag : V6_vabsb -class Hexagon_v16i32_v16i32_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : V6_vmpyub -class Hexagon_v32i32_v16i32i32_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : V6_vmpyub -class Hexagon_v64i32_v32i32i32_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : V6_vmpyub_acc -class Hexagon_v32i32_v32i32v16i32i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : V6_vmpyub_acc -class Hexagon_v64i32_v64i32v32i32i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_Intrinsic; - -// tag : V6_vandqrt +// tag : V6_vandnqrt class Hexagon_custom_v16i32_v64i1i32_Intrinsic< list intr_properties = [IntrNoMem]> : Hexagon_NonGCC_Intrinsic< [llvm_v16i32_ty], [llvm_v64i1_ty,llvm_i32_ty], intr_properties>; -// tag : V6_vandqrt +// tag : V6_vandnqrt class Hexagon_custom_v32i32_v128i1i32_Intrinsic_128B< list intr_properties = [IntrNoMem]> : Hexagon_NonGCC_Intrinsic< [llvm_v32i32_ty], [llvm_v128i1_ty,llvm_i32_ty], intr_properties>; -// tag : V6_vandqrt_acc +// tag : V6_vandnqrt_acc class Hexagon_custom_v16i32_v16i32v64i1i32_Intrinsic< list intr_properties = [IntrNoMem]> : Hexagon_NonGCC_Intrinsic< [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v64i1_ty,llvm_i32_ty], intr_properties>; -// tag : V6_vandqrt_acc +// tag : V6_vandnqrt_acc class Hexagon_custom_v32i32_v32i32v128i1i32_Intrinsic_128B< list intr_properties = [IntrNoMem]> : Hexagon_NonGCC_Intrinsic< [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v128i1_ty,llvm_i32_ty], intr_properties>; +// tag : V6_vandvnqv +class Hexagon_custom_v16i32_v64i1v16i32_Intrinsic< + list intr_properties = [IntrNoMem]> + : Hexagon_NonGCC_Intrinsic< + [llvm_v16i32_ty], [llvm_v64i1_ty,llvm_v16i32_ty], + intr_properties>; + +// tag : V6_vandvnqv +class Hexagon_custom_v32i32_v128i1v32i32_Intrinsic_128B< + list intr_properties = [IntrNoMem]> + : Hexagon_NonGCC_Intrinsic< + [llvm_v32i32_ty], [llvm_v128i1_ty,llvm_v32i32_ty], + intr_properties>; + // tag : V6_vandvrt class Hexagon_custom_v64i1_v16i32i32_Intrinsic< list intr_properties = [IntrNoMem]> @@ -806,174 +631,167 @@ class Hexagon_custom_v128i1_v128i1v32i32i32_Intrinsic_128B< [llvm_v128i1_ty], [llvm_v128i1_ty,llvm_v32i32_ty,llvm_i32_ty], intr_properties>; -// tag : V6_vandvqv -class Hexagon_custom_v16i32_v64i1v16i32_Intrinsic< +// tag : V6_vaslh +class Hexagon_v16i32_v16i32i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< - [llvm_v16i32_ty], [llvm_v64i1_ty,llvm_v16i32_ty], + : Hexagon_Intrinsic; -// tag : V6_vandvqv -class Hexagon_custom_v32i32_v128i1v32i32_Intrinsic_128B< +// tag : V6_vaslh +class Hexagon_v32i32_v32i32i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< - [llvm_v32i32_ty], [llvm_v128i1_ty,llvm_v32i32_ty], + : Hexagon_Intrinsic; -// tag : V6_vgtw -class Hexagon_custom_v64i1_v16i32v16i32_Intrinsic< +// tag : V6_vassignp +class Hexagon_v64i32_v64i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< - [llvm_v64i1_ty], [llvm_v16i32_ty,llvm_v16i32_ty], + : Hexagon_Intrinsic; -// tag : V6_vgtw -class Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B< +// tag : V6_vd0 +class Hexagon_v16i32__Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< - [llvm_v128i1_ty], [llvm_v32i32_ty,llvm_v32i32_ty], + : Hexagon_Intrinsic; -// tag : V6_vgtw_and -class Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic< +// tag : V6_vd0 +class Hexagon_v32i32__Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< - [llvm_v64i1_ty], [llvm_v64i1_ty,llvm_v16i32_ty,llvm_v16i32_ty], + : Hexagon_Intrinsic; -// tag : V6_vgtw_and -class Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B< +// tag : V6_vdd0 +class Hexagon_v64i32__Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< - [llvm_v128i1_ty], [llvm_v128i1_ty,llvm_v32i32_ty,llvm_v32i32_ty], + : Hexagon_Intrinsic; -// tag : V6_pred_scalar2 -class Hexagon_custom_v64i1_i32_Intrinsic< - list intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< - [llvm_v64i1_ty], [llvm_i32_ty], - intr_properties>; - -// tag : V6_pred_scalar2 -class Hexagon_custom_v128i1_i32_Intrinsic_128B< - list intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< - [llvm_v128i1_ty], [llvm_i32_ty], - intr_properties>; - -// tag : V6_shuffeqw -class Hexagon_custom_v64i1_v64i1v64i1_Intrinsic< - list intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< - [llvm_v64i1_ty], [llvm_v64i1_ty,llvm_v64i1_ty], - intr_properties>; - -// tag : V6_shuffeqw -class Hexagon_custom_v128i1_v128i1v128i1_Intrinsic_128B< - list intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< - [llvm_v128i1_ty], [llvm_v128i1_ty,llvm_v128i1_ty], - intr_properties>; - -// tag : V6_pred_not -class Hexagon_custom_v64i1_v64i1_Intrinsic< - list intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< - [llvm_v64i1_ty], [llvm_v64i1_ty], - intr_properties>; - -// tag : V6_pred_not -class Hexagon_custom_v128i1_v128i1_Intrinsic_128B< - list intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< - [llvm_v128i1_ty], [llvm_v128i1_ty], - intr_properties>; - -// tag : V6_vswap -class Hexagon_custom_v32i32_v64i1v16i32v16i32_Intrinsic< - list intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< - [llvm_v32i32_ty], [llvm_v64i1_ty,llvm_v16i32_ty,llvm_v16i32_ty], - intr_properties>; - -// tag : V6_vswap -class Hexagon_custom_v64i32_v128i1v32i32v32i32_Intrinsic_128B< - list intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< - [llvm_v64i32_ty], [llvm_v128i1_ty,llvm_v32i32_ty,llvm_v32i32_ty], - intr_properties>; - -// tag : V6_vshuffvdd +// tag : V6_vdealvdd class Hexagon_v32i32_v16i32v16i32i32_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : V6_extractw -class Hexagon_i32_v16i32i32_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : V6_lvsplatw -class Hexagon_v16i32_i32_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : V6_vlutvvb_oracc -class Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : V6_vlutvwh_oracc -class Hexagon_v32i32_v32i32v16i32v16i32i32_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : V6_vmpahhsat -class Hexagon_v16i32_v16i32v16i32i64_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : V6_vlut4 -class Hexagon_v16i32_v16i32i64_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : V6_hi -class Hexagon_v16i32_v32i32_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : V6_vgathermw +// tag : V6_vdmpyhvsat_acc +class Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic intr_properties = [IntrNoMem]> + : Hexagon_Intrinsic; + +// tag : V6_veqb +class Hexagon_custom_v64i1_v16i32v16i32_Intrinsic< + list intr_properties = [IntrNoMem]> + : Hexagon_NonGCC_Intrinsic< + [llvm_v64i1_ty], [llvm_v16i32_ty,llvm_v16i32_ty], + intr_properties>; + +// tag : V6_veqb +class Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B< + list intr_properties = [IntrNoMem]> + : Hexagon_NonGCC_Intrinsic< + [llvm_v128i1_ty], [llvm_v32i32_ty,llvm_v32i32_ty], + intr_properties>; + +// tag : V6_veqb_and +class Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic< + list intr_properties = [IntrNoMem]> + : Hexagon_NonGCC_Intrinsic< + [llvm_v64i1_ty], [llvm_v64i1_ty,llvm_v16i32_ty,llvm_v16i32_ty], + intr_properties>; + +// tag : V6_veqb_and +class Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B< + list intr_properties = [IntrNoMem]> + : Hexagon_NonGCC_Intrinsic< + [llvm_v128i1_ty], [llvm_v128i1_ty,llvm_v32i32_ty,llvm_v32i32_ty], + intr_properties>; + +// tag : V6_vgathermh class Hexagon__ptri32i32v16i32_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : V6_vgathermw +// tag : V6_vgathermh class Hexagon__ptri32i32v32i32_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; +// tag : V6_vgathermhq +class Hexagon_custom__ptrv64i1i32i32v16i32_Intrinsic< + list intr_properties = [IntrNoMem]> + : Hexagon_NonGCC_Intrinsic< + [], [llvm_ptr_ty,llvm_v64i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v16i32_ty], + intr_properties>; + +// tag : V6_vgathermhq +class Hexagon_custom__ptrv128i1i32i32v32i32_Intrinsic_128B< + list intr_properties = [IntrNoMem]> + : Hexagon_NonGCC_Intrinsic< + [], [llvm_ptr_ty,llvm_v128i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v32i32_ty], + intr_properties>; + // tag : V6_vgathermhw class Hexagon__ptri32i32v64i32_Intrinsic intr_properties = [IntrNoMem]> @@ -981,20 +799,6 @@ class Hexagon__ptri32i32v64i32_Intrinsic; -// tag : V6_vgathermwq -class Hexagon_custom__ptrv64i1i32i32v16i32_Intrinsic< - list intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< - [], [llvm_ptr_ty,llvm_v64i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v16i32_ty], - intr_properties>; - -// tag : V6_vgathermwq -class Hexagon_custom__ptrv128i1i32i32v32i32_Intrinsic_128B< - list intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< - [], [llvm_ptr_ty,llvm_v128i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v32i32_ty], - intr_properties>; - // tag : V6_vgathermhwq class Hexagon_custom__ptrv64i1i32i32v32i32_Intrinsic< list intr_properties = [IntrNoMem]> @@ -1009,28 +813,161 @@ class Hexagon_custom__ptrv128i1i32i32v64i32_Intrinsic_128B< [], [llvm_ptr_ty,llvm_v128i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v64i32_ty], intr_properties>; -// tag : V6_vscattermw +// tag : V6_vlut4 +class Hexagon_v16i32_v16i32i64_Intrinsic intr_properties = [IntrNoMem]> + : Hexagon_Intrinsic; + +// tag : V6_vlut4 +class Hexagon_v32i32_v32i32i64_Intrinsic intr_properties = [IntrNoMem]> + : Hexagon_Intrinsic; + +// tag : V6_vlutvvb_oracc +class Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic intr_properties = [IntrNoMem]> + : Hexagon_Intrinsic; + +// tag : V6_vlutvwh_oracc +class Hexagon_v32i32_v32i32v16i32v16i32i32_Intrinsic intr_properties = [IntrNoMem]> + : Hexagon_Intrinsic; + +// tag : V6_vlutvwh_oracc +class Hexagon_v64i32_v64i32v32i32v32i32i32_Intrinsic intr_properties = [IntrNoMem]> + : Hexagon_Intrinsic; + +// tag : V6_vmpahhsat +class Hexagon_v16i32_v16i32v16i32i64_Intrinsic intr_properties = [IntrNoMem]> + : Hexagon_Intrinsic; + +// tag : V6_vmpahhsat +class Hexagon_v32i32_v32i32v32i32i64_Intrinsic intr_properties = [IntrNoMem]> + : Hexagon_Intrinsic; + +// tag : V6_vmpybus +class Hexagon_v32i32_v16i32i32_Intrinsic intr_properties = [IntrNoMem]> + : Hexagon_Intrinsic; + +// tag : V6_vmpybus +class Hexagon_v64i32_v32i32i32_Intrinsic intr_properties = [IntrNoMem]> + : Hexagon_Intrinsic; + +// tag : V6_vmpybus_acc +class Hexagon_v32i32_v32i32v16i32i32_Intrinsic intr_properties = [IntrNoMem]> + : Hexagon_Intrinsic; + +// tag : V6_vmpybus_acc +class Hexagon_v64i32_v64i32v32i32i32_Intrinsic intr_properties = [IntrNoMem]> + : Hexagon_Intrinsic; + +// tag : V6_vprefixqb +class Hexagon_custom_v16i32_v64i1_Intrinsic< + list intr_properties = [IntrNoMem]> + : Hexagon_NonGCC_Intrinsic< + [llvm_v16i32_ty], [llvm_v64i1_ty], + intr_properties>; + +// tag : V6_vprefixqb +class Hexagon_custom_v32i32_v128i1_Intrinsic_128B< + list intr_properties = [IntrNoMem]> + : Hexagon_NonGCC_Intrinsic< + [llvm_v32i32_ty], [llvm_v128i1_ty], + intr_properties>; + +// tag : V6_vrmpybusi +class Hexagon_v32i32_v32i32i32i32_Intrinsic intr_properties = [IntrNoMem]> + : Hexagon_Intrinsic; + +// tag : V6_vrmpybusi +class Hexagon_v64i32_v64i32i32i32_Intrinsic intr_properties = [IntrNoMem]> + : Hexagon_Intrinsic; + +// tag : V6_vrmpybusi_acc +class Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic intr_properties = [IntrNoMem]> + : Hexagon_Intrinsic; + +// tag : V6_vrmpybusi_acc +class Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic intr_properties = [IntrNoMem]> + : Hexagon_Intrinsic; + +// tag : V6_vsb +class Hexagon_v32i32_v16i32_Intrinsic intr_properties = [IntrNoMem]> + : Hexagon_Intrinsic; + +// tag : V6_vsb +class Hexagon_v64i32_v32i32_Intrinsic intr_properties = [IntrNoMem]> + : Hexagon_Intrinsic; + +// tag : V6_vscattermh class Hexagon__i32i32v16i32v16i32_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : V6_vscattermw +// tag : V6_vscattermh class Hexagon__i32i32v32i32v32i32_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : V6_vscattermwq +// tag : V6_vscattermhq class Hexagon_custom__v64i1i32i32v16i32v16i32_Intrinsic< list intr_properties = [IntrNoMem]> : Hexagon_NonGCC_Intrinsic< [], [llvm_v64i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v16i32_ty,llvm_v16i32_ty], intr_properties>; -// tag : V6_vscattermwq +// tag : V6_vscattermhq class Hexagon_custom__v128i1i32i32v32i32v32i32_Intrinsic_128B< list intr_properties = [IntrNoMem]> : Hexagon_NonGCC_Intrinsic< @@ -1065,72 +1002,727 @@ class Hexagon_custom__v128i1i32i32v64i32v32i32_Intrinsic_128B< [], [llvm_v128i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v64i32_ty,llvm_v32i32_ty], intr_properties>; -// tag : V6_vprefixqb -class Hexagon_custom_v16i32_v64i1_Intrinsic< +// tag : V6_vswap +class Hexagon_custom_v32i32_v64i1v16i32v16i32_Intrinsic< list intr_properties = [IntrNoMem]> : Hexagon_NonGCC_Intrinsic< - [llvm_v16i32_ty], [llvm_v64i1_ty], + [llvm_v32i32_ty], [llvm_v64i1_ty,llvm_v16i32_ty,llvm_v16i32_ty], intr_properties>; -// tag : V6_vprefixqb -class Hexagon_custom_v32i32_v128i1_Intrinsic_128B< +// tag : V6_vswap +class Hexagon_custom_v64i32_v128i1v32i32v32i32_Intrinsic_128B< list intr_properties = [IntrNoMem]> : Hexagon_NonGCC_Intrinsic< - [llvm_v32i32_ty], [llvm_v128i1_ty], + [llvm_v64i32_ty], [llvm_v128i1_ty,llvm_v32i32_ty,llvm_v32i32_ty], + intr_properties>; + +// tag : V6_vunpackob +class Hexagon_v32i32_v32i32v16i32_Intrinsic intr_properties = [IntrNoMem]> + : Hexagon_Intrinsic; + +// tag : V6_vunpackob +class Hexagon_v64i32_v64i32v32i32_Intrinsic intr_properties = [IntrNoMem]> + : Hexagon_Intrinsic; + +// tag : Y2_dccleana +class Hexagon__ptr_Intrinsic intr_properties = [IntrNoMem]> + : Hexagon_Intrinsic; + +// tag : Y4_l2fetch +class Hexagon__ptri32_Intrinsic intr_properties = [IntrNoMem]> + : Hexagon_Intrinsic; + +// tag : Y5_l2fetch +class Hexagon__ptri64_Intrinsic intr_properties = [IntrNoMem]> + : Hexagon_Intrinsic; + +// tag : Y6_dmlink +class Hexagon__ptrptr_Intrinsic intr_properties = [IntrNoMem]> + : Hexagon_Intrinsic; + +// tag : Y6_dmpause +class Hexagon_i32__Intrinsic intr_properties = [IntrNoMem]> + : Hexagon_Intrinsic; // V5 Scalar Instructions. -def int_hexagon_C2_cmpeq : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpeq">; +def int_hexagon_A2_abs : +Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_abs">; -def int_hexagon_C2_cmpgt : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgt">; +def int_hexagon_A2_absp : +Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_absp">; -def int_hexagon_C2_cmpgtu : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgtu">; +def int_hexagon_A2_abssat : +Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_abssat">; -def int_hexagon_C2_cmpeqp : -Hexagon_i32_i64i64_Intrinsic<"HEXAGON_C2_cmpeqp">; +def int_hexagon_A2_add : +Hexagon_custom_i32_i32i32_Intrinsic; -def int_hexagon_C2_cmpgtp : -Hexagon_i32_i64i64_Intrinsic<"HEXAGON_C2_cmpgtp">; +def int_hexagon_A2_addh_h16_hh : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_hh">; -def int_hexagon_C2_cmpgtup : -Hexagon_i32_i64i64_Intrinsic<"HEXAGON_C2_cmpgtup">; +def int_hexagon_A2_addh_h16_hl : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_hl">; -def int_hexagon_A4_rcmpeqi : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpeqi", [IntrNoMem, ImmArg>]>; +def int_hexagon_A2_addh_h16_lh : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_lh">; -def int_hexagon_A4_rcmpneqi : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpneqi", [IntrNoMem, ImmArg>]>; +def int_hexagon_A2_addh_h16_ll : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_ll">; + +def int_hexagon_A2_addh_h16_sat_hh : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_hh">; + +def int_hexagon_A2_addh_h16_sat_hl : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_hl">; + +def int_hexagon_A2_addh_h16_sat_lh : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_lh">; + +def int_hexagon_A2_addh_h16_sat_ll : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_ll">; + +def int_hexagon_A2_addh_l16_hl : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_hl">; + +def int_hexagon_A2_addh_l16_ll : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_ll">; + +def int_hexagon_A2_addh_l16_sat_hl : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_sat_hl">; + +def int_hexagon_A2_addh_l16_sat_ll : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_sat_ll">; + +def int_hexagon_A2_addi : +Hexagon_custom_i32_i32i32_Intrinsic<[IntrNoMem, ImmArg>]>; + +def int_hexagon_A2_addp : +Hexagon_custom_i64_i64i64_Intrinsic; + +def int_hexagon_A2_addpsat : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_addpsat">; + +def int_hexagon_A2_addsat : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addsat">; + +def int_hexagon_A2_addsp : +Hexagon_i64_i32i64_Intrinsic<"HEXAGON_A2_addsp">; + +def int_hexagon_A2_and : +Hexagon_custom_i32_i32i32_Intrinsic; + +def int_hexagon_A2_andir : +Hexagon_custom_i32_i32i32_Intrinsic<[IntrNoMem, ImmArg>]>; + +def int_hexagon_A2_andp : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_andp">; + +def int_hexagon_A2_aslh : +Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_aslh">; + +def int_hexagon_A2_asrh : +Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_asrh">; + +def int_hexagon_A2_combine_hh : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_hh">; + +def int_hexagon_A2_combine_hl : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_hl">; + +def int_hexagon_A2_combine_lh : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_lh">; + +def int_hexagon_A2_combine_ll : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_ll">; + +def int_hexagon_A2_combineii : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A2_combineii", [IntrNoMem, ImmArg>, ImmArg>]>; + +def int_hexagon_A2_combinew : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A2_combinew">; + +def int_hexagon_A2_max : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_max">; + +def int_hexagon_A2_maxp : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_maxp">; + +def int_hexagon_A2_maxu : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_maxu">; + +def int_hexagon_A2_maxup : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_maxup">; + +def int_hexagon_A2_min : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_min">; + +def int_hexagon_A2_minp : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_minp">; + +def int_hexagon_A2_minu : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_minu">; + +def int_hexagon_A2_minup : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_minup">; + +def int_hexagon_A2_neg : +Hexagon_custom_i32_i32_Intrinsic; + +def int_hexagon_A2_negp : +Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_negp">; + +def int_hexagon_A2_negsat : +Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_negsat">; + +def int_hexagon_A2_not : +Hexagon_custom_i32_i32_Intrinsic; + +def int_hexagon_A2_notp : +Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_notp">; + +def int_hexagon_A2_or : +Hexagon_custom_i32_i32i32_Intrinsic; + +def int_hexagon_A2_orir : +Hexagon_custom_i32_i32i32_Intrinsic<[IntrNoMem, ImmArg>]>; + +def int_hexagon_A2_orp : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_orp">; + +def int_hexagon_A2_roundsat : +Hexagon_i32_i64_Intrinsic<"HEXAGON_A2_roundsat">; + +def int_hexagon_A2_sat : +Hexagon_i32_i64_Intrinsic<"HEXAGON_A2_sat">; + +def int_hexagon_A2_satb : +Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_satb">; + +def int_hexagon_A2_sath : +Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_sath">; + +def int_hexagon_A2_satub : +Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_satub">; + +def int_hexagon_A2_satuh : +Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_satuh">; + +def int_hexagon_A2_sub : +Hexagon_custom_i32_i32i32_Intrinsic; + +def int_hexagon_A2_subh_h16_hh : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_hh">; + +def int_hexagon_A2_subh_h16_hl : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_hl">; + +def int_hexagon_A2_subh_h16_lh : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_lh">; + +def int_hexagon_A2_subh_h16_ll : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_ll">; + +def int_hexagon_A2_subh_h16_sat_hh : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_hh">; + +def int_hexagon_A2_subh_h16_sat_hl : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_hl">; + +def int_hexagon_A2_subh_h16_sat_lh : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_lh">; + +def int_hexagon_A2_subh_h16_sat_ll : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_ll">; + +def int_hexagon_A2_subh_l16_hl : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_hl">; + +def int_hexagon_A2_subh_l16_ll : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_ll">; + +def int_hexagon_A2_subh_l16_sat_hl : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_sat_hl">; + +def int_hexagon_A2_subh_l16_sat_ll : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_sat_ll">; + +def int_hexagon_A2_subp : +Hexagon_custom_i64_i64i64_Intrinsic; + +def int_hexagon_A2_subri : +Hexagon_custom_i32_i32i32_Intrinsic<[IntrNoMem, ImmArg>]>; + +def int_hexagon_A2_subsat : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subsat">; + +def int_hexagon_A2_svaddh : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svaddh">; + +def int_hexagon_A2_svaddhs : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svaddhs">; + +def int_hexagon_A2_svadduhs : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svadduhs">; + +def int_hexagon_A2_svavgh : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svavgh">; + +def int_hexagon_A2_svavghs : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svavghs">; + +def int_hexagon_A2_svnavgh : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svnavgh">; + +def int_hexagon_A2_svsubh : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svsubh">; + +def int_hexagon_A2_svsubhs : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svsubhs">; + +def int_hexagon_A2_svsubuhs : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svsubuhs">; + +def int_hexagon_A2_swiz : +Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_swiz">; + +def int_hexagon_A2_sxtb : +Hexagon_custom_i32_i32_Intrinsic; + +def int_hexagon_A2_sxth : +Hexagon_custom_i32_i32_Intrinsic; + +def int_hexagon_A2_sxtw : +Hexagon_i64_i32_Intrinsic<"HEXAGON_A2_sxtw">; + +def int_hexagon_A2_tfr : +Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_tfr">; + +def int_hexagon_A2_tfrih : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_tfrih", [IntrNoMem, ImmArg>]>; + +def int_hexagon_A2_tfril : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_tfril", [IntrNoMem, ImmArg>]>; + +def int_hexagon_A2_tfrp : +Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_tfrp">; + +def int_hexagon_A2_tfrpi : +Hexagon_i64_i32_Intrinsic<"HEXAGON_A2_tfrpi", [IntrNoMem, ImmArg>]>; + +def int_hexagon_A2_tfrsi : +Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_tfrsi", [IntrNoMem, ImmArg>]>; + +def int_hexagon_A2_vabsh : +Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabsh">; + +def int_hexagon_A2_vabshsat : +Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabshsat">; + +def int_hexagon_A2_vabsw : +Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabsw">; + +def int_hexagon_A2_vabswsat : +Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabswsat">; + +def int_hexagon_A2_vaddb_map : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddb_map">; + +def int_hexagon_A2_vaddh : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddh">; + +def int_hexagon_A2_vaddhs : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddhs">; + +def int_hexagon_A2_vaddub : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddub">; + +def int_hexagon_A2_vaddubs : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddubs">; + +def int_hexagon_A2_vadduhs : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vadduhs">; + +def int_hexagon_A2_vaddw : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddw">; + +def int_hexagon_A2_vaddws : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddws">; + +def int_hexagon_A2_vavgh : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgh">; + +def int_hexagon_A2_vavghcr : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavghcr">; + +def int_hexagon_A2_vavghr : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavghr">; + +def int_hexagon_A2_vavgub : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgub">; + +def int_hexagon_A2_vavgubr : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgubr">; + +def int_hexagon_A2_vavguh : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguh">; + +def int_hexagon_A2_vavguhr : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguhr">; + +def int_hexagon_A2_vavguw : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguw">; + +def int_hexagon_A2_vavguwr : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguwr">; + +def int_hexagon_A2_vavgw : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgw">; + +def int_hexagon_A2_vavgwcr : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgwcr">; + +def int_hexagon_A2_vavgwr : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgwr">; + +def int_hexagon_A2_vcmpbeq : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpbeq">; + +def int_hexagon_A2_vcmpbgtu : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpbgtu">; + +def int_hexagon_A2_vcmpheq : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpheq">; + +def int_hexagon_A2_vcmphgt : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmphgt">; + +def int_hexagon_A2_vcmphgtu : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmphgtu">; + +def int_hexagon_A2_vcmpweq : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpweq">; + +def int_hexagon_A2_vcmpwgt : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpwgt">; + +def int_hexagon_A2_vcmpwgtu : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpwgtu">; + +def int_hexagon_A2_vconj : +Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vconj">; + +def int_hexagon_A2_vmaxb : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxb">; + +def int_hexagon_A2_vmaxh : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxh">; + +def int_hexagon_A2_vmaxub : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxub">; + +def int_hexagon_A2_vmaxuh : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxuh">; + +def int_hexagon_A2_vmaxuw : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxuw">; + +def int_hexagon_A2_vmaxw : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxw">; + +def int_hexagon_A2_vminb : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminb">; + +def int_hexagon_A2_vminh : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminh">; + +def int_hexagon_A2_vminub : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminub">; + +def int_hexagon_A2_vminuh : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminuh">; + +def int_hexagon_A2_vminuw : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminuw">; + +def int_hexagon_A2_vminw : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminw">; + +def int_hexagon_A2_vnavgh : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgh">; + +def int_hexagon_A2_vnavghcr : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavghcr">; + +def int_hexagon_A2_vnavghr : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavghr">; + +def int_hexagon_A2_vnavgw : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgw">; + +def int_hexagon_A2_vnavgwcr : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgwcr">; + +def int_hexagon_A2_vnavgwr : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgwr">; + +def int_hexagon_A2_vraddub : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vraddub">; + +def int_hexagon_A2_vraddub_acc : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_A2_vraddub_acc">; + +def int_hexagon_A2_vrsadub : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vrsadub">; + +def int_hexagon_A2_vrsadub_acc : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_A2_vrsadub_acc">; + +def int_hexagon_A2_vsubb_map : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubb_map">; + +def int_hexagon_A2_vsubh : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubh">; + +def int_hexagon_A2_vsubhs : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubhs">; + +def int_hexagon_A2_vsubub : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubub">; + +def int_hexagon_A2_vsububs : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsububs">; + +def int_hexagon_A2_vsubuhs : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubuhs">; + +def int_hexagon_A2_vsubw : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubw">; + +def int_hexagon_A2_vsubws : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubws">; + +def int_hexagon_A2_xor : +Hexagon_custom_i32_i32i32_Intrinsic; + +def int_hexagon_A2_xorp : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_xorp">; + +def int_hexagon_A2_zxtb : +Hexagon_custom_i32_i32_Intrinsic; + +def int_hexagon_A2_zxth : +Hexagon_custom_i32_i32_Intrinsic; + +def int_hexagon_A4_andn : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_andn">; + +def int_hexagon_A4_andnp : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A4_andnp">; + +def int_hexagon_A4_bitsplit : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_bitsplit">; + +def int_hexagon_A4_bitspliti : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_bitspliti", [IntrNoMem, ImmArg>]>; + +def int_hexagon_A4_boundscheck : +Hexagon_i32_i32i64_Intrinsic<"HEXAGON_A4_boundscheck">; + +def int_hexagon_A4_cmpbeq : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbeq">; + +def int_hexagon_A4_cmpbeqi : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbeqi", [IntrNoMem, ImmArg>]>; + +def int_hexagon_A4_cmpbgt : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgt">; + +def int_hexagon_A4_cmpbgti : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgti", [IntrNoMem, ImmArg>]>; + +def int_hexagon_A4_cmpbgtu : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgtu">; + +def int_hexagon_A4_cmpbgtui : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgtui", [IntrNoMem, ImmArg>]>; + +def int_hexagon_A4_cmpheq : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpheq">; + +def int_hexagon_A4_cmpheqi : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpheqi", [IntrNoMem, ImmArg>]>; + +def int_hexagon_A4_cmphgt : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgt">; + +def int_hexagon_A4_cmphgti : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgti", [IntrNoMem, ImmArg>]>; + +def int_hexagon_A4_cmphgtu : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgtu">; + +def int_hexagon_A4_cmphgtui : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgtui", [IntrNoMem, ImmArg>]>; + +def int_hexagon_A4_combineir : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_combineir", [IntrNoMem, ImmArg>]>; + +def int_hexagon_A4_combineri : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_combineri", [IntrNoMem, ImmArg>]>; + +def int_hexagon_A4_cround_ri : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cround_ri", [IntrNoMem, ImmArg>]>; + +def int_hexagon_A4_cround_rr : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cround_rr">; + +def int_hexagon_A4_modwrapu : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_modwrapu">; + +def int_hexagon_A4_orn : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_orn">; + +def int_hexagon_A4_ornp : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A4_ornp">; def int_hexagon_A4_rcmpeq : Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpeq">; +def int_hexagon_A4_rcmpeqi : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpeqi", [IntrNoMem, ImmArg>]>; + def int_hexagon_A4_rcmpneq : Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpneq">; -def int_hexagon_C2_bitsset : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_bitsset">; +def int_hexagon_A4_rcmpneqi : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpneqi", [IntrNoMem, ImmArg>]>; + +def int_hexagon_A4_round_ri : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_ri", [IntrNoMem, ImmArg>]>; + +def int_hexagon_A4_round_ri_sat : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_ri_sat", [IntrNoMem, ImmArg>]>; + +def int_hexagon_A4_round_rr : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_rr">; + +def int_hexagon_A4_round_rr_sat : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_rr_sat">; + +def int_hexagon_A4_tlbmatch : +Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_tlbmatch">; + +def int_hexagon_A4_vcmpbeq_any : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A4_vcmpbeq_any">; + +def int_hexagon_A4_vcmpbeqi : +Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbeqi", [IntrNoMem, ImmArg>]>; + +def int_hexagon_A4_vcmpbgt : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A4_vcmpbgt">; + +def int_hexagon_A4_vcmpbgti : +Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbgti", [IntrNoMem, ImmArg>]>; + +def int_hexagon_A4_vcmpbgtui : +Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbgtui", [IntrNoMem, ImmArg>]>; + +def int_hexagon_A4_vcmpheqi : +Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpheqi", [IntrNoMem, ImmArg>]>; + +def int_hexagon_A4_vcmphgti : +Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmphgti", [IntrNoMem, ImmArg>]>; + +def int_hexagon_A4_vcmphgtui : +Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmphgtui", [IntrNoMem, ImmArg>]>; + +def int_hexagon_A4_vcmpweqi : +Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpweqi", [IntrNoMem, ImmArg>]>; + +def int_hexagon_A4_vcmpwgti : +Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpwgti", [IntrNoMem, ImmArg>]>; + +def int_hexagon_A4_vcmpwgtui : +Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpwgtui", [IntrNoMem, ImmArg>]>; + +def int_hexagon_A4_vrmaxh : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxh">; + +def int_hexagon_A4_vrmaxuh : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxuh">; + +def int_hexagon_A4_vrmaxuw : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxuw">; + +def int_hexagon_A4_vrmaxw : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxw">; + +def int_hexagon_A4_vrminh : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminh">; + +def int_hexagon_A4_vrminuh : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminuh">; + +def int_hexagon_A4_vrminuw : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminuw">; + +def int_hexagon_A4_vrminw : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminw">; + +def int_hexagon_A5_vaddhubs : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A5_vaddhubs">; + +def int_hexagon_C2_all8 : +Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_all8">; + +def int_hexagon_C2_and : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_and">; + +def int_hexagon_C2_andn : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_andn">; + +def int_hexagon_C2_any8 : +Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_any8">; def int_hexagon_C2_bitsclr : Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_bitsclr">; -def int_hexagon_C4_nbitsset : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_nbitsset">; +def int_hexagon_C2_bitsclri : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_bitsclri", [IntrNoMem, ImmArg>]>; -def int_hexagon_C4_nbitsclr : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_nbitsclr">; +def int_hexagon_C2_bitsset : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_bitsset">; + +def int_hexagon_C2_cmpeq : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpeq">; def int_hexagon_C2_cmpeqi : Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpeqi", [IntrNoMem, ImmArg>]>; -def int_hexagon_C2_cmpgti : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgti", [IntrNoMem, ImmArg>]>; - -def int_hexagon_C2_cmpgtui : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgtui", [IntrNoMem, ImmArg>]>; +def int_hexagon_C2_cmpeqp : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_C2_cmpeqp">; def int_hexagon_C2_cmpgei : Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgei", [IntrNoMem, ImmArg>]>; @@ -1138,89 +1730,32 @@ Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgei", [IntrNoMem, ImmArg def int_hexagon_C2_cmpgeui : Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgeui", [IntrNoMem, ImmArg>]>; +def int_hexagon_C2_cmpgt : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgt">; + +def int_hexagon_C2_cmpgti : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgti", [IntrNoMem, ImmArg>]>; + +def int_hexagon_C2_cmpgtp : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_C2_cmpgtp">; + +def int_hexagon_C2_cmpgtu : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgtu">; + +def int_hexagon_C2_cmpgtui : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgtui", [IntrNoMem, ImmArg>]>; + +def int_hexagon_C2_cmpgtup : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_C2_cmpgtup">; + def int_hexagon_C2_cmplt : Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmplt">; def int_hexagon_C2_cmpltu : Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpltu">; -def int_hexagon_C2_bitsclri : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_bitsclri", [IntrNoMem, ImmArg>]>; - -def int_hexagon_C4_nbitsclri : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_nbitsclri", [IntrNoMem, ImmArg>]>; - -def int_hexagon_C4_cmpneqi : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmpneqi", [IntrNoMem, ImmArg>]>; - -def int_hexagon_C4_cmpltei : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmpltei", [IntrNoMem, ImmArg>]>; - -def int_hexagon_C4_cmplteui : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmplteui", [IntrNoMem, ImmArg>]>; - -def int_hexagon_C4_cmpneq : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmpneq">; - -def int_hexagon_C4_cmplte : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmplte">; - -def int_hexagon_C4_cmplteu : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmplteu">; - -def int_hexagon_C2_and : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_and">; - -def int_hexagon_C2_or : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_or">; - -def int_hexagon_C2_xor : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_xor">; - -def int_hexagon_C2_andn : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_andn">; - -def int_hexagon_C2_not : -Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_not">; - -def int_hexagon_C2_orn : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_orn">; - -def int_hexagon_C4_and_and : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_and">; - -def int_hexagon_C4_and_or : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_or">; - -def int_hexagon_C4_or_and : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_and">; - -def int_hexagon_C4_or_or : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_or">; - -def int_hexagon_C4_and_andn : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_andn">; - -def int_hexagon_C4_and_orn : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_orn">; - -def int_hexagon_C4_or_andn : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_andn">; - -def int_hexagon_C4_or_orn : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_orn">; - -def int_hexagon_C2_pxfer_map : -Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_pxfer_map">; - -def int_hexagon_C2_any8 : -Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_any8">; - -def int_hexagon_C2_all8 : -Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_all8">; - -def int_hexagon_C2_vitpack : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_vitpack">; +def int_hexagon_C2_mask : +Hexagon_i64_i32_Intrinsic<"HEXAGON_C2_mask">; def int_hexagon_C2_mux : Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_mux">; @@ -1234,110 +1769,17 @@ Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_muxir", [IntrNoMem, ImmArg>]>; -def int_hexagon_C2_vmux : -Hexagon_i64_i32i64i64_Intrinsic<"HEXAGON_C2_vmux">; +def int_hexagon_C2_not : +Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_not">; -def int_hexagon_C2_mask : -Hexagon_i64_i32_Intrinsic<"HEXAGON_C2_mask">; +def int_hexagon_C2_or : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_or">; -def int_hexagon_A2_vcmpbeq : -Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpbeq">; +def int_hexagon_C2_orn : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_orn">; -def int_hexagon_A4_vcmpbeqi : -Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbeqi", [IntrNoMem, ImmArg>]>; - -def int_hexagon_A4_vcmpbeq_any : -Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A4_vcmpbeq_any">; - -def int_hexagon_A2_vcmpbgtu : -Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpbgtu">; - -def int_hexagon_A4_vcmpbgtui : -Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbgtui", [IntrNoMem, ImmArg>]>; - -def int_hexagon_A4_vcmpbgt : -Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A4_vcmpbgt">; - -def int_hexagon_A4_vcmpbgti : -Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbgti", [IntrNoMem, ImmArg>]>; - -def int_hexagon_A4_cmpbeq : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbeq">; - -def int_hexagon_A4_cmpbeqi : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbeqi", [IntrNoMem, ImmArg>]>; - -def int_hexagon_A4_cmpbgtu : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgtu">; - -def int_hexagon_A4_cmpbgtui : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgtui", [IntrNoMem, ImmArg>]>; - -def int_hexagon_A4_cmpbgt : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgt">; - -def int_hexagon_A4_cmpbgti : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgti", [IntrNoMem, ImmArg>]>; - -def int_hexagon_A2_vcmpheq : -Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpheq">; - -def int_hexagon_A2_vcmphgt : -Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmphgt">; - -def int_hexagon_A2_vcmphgtu : -Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmphgtu">; - -def int_hexagon_A4_vcmpheqi : -Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpheqi", [IntrNoMem, ImmArg>]>; - -def int_hexagon_A4_vcmphgti : -Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmphgti", [IntrNoMem, ImmArg>]>; - -def int_hexagon_A4_vcmphgtui : -Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmphgtui", [IntrNoMem, ImmArg>]>; - -def int_hexagon_A4_cmpheq : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpheq">; - -def int_hexagon_A4_cmphgt : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgt">; - -def int_hexagon_A4_cmphgtu : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgtu">; - -def int_hexagon_A4_cmpheqi : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpheqi", [IntrNoMem, ImmArg>]>; - -def int_hexagon_A4_cmphgti : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgti", [IntrNoMem, ImmArg>]>; - -def int_hexagon_A4_cmphgtui : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgtui", [IntrNoMem, ImmArg>]>; - -def int_hexagon_A2_vcmpweq : -Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpweq">; - -def int_hexagon_A2_vcmpwgt : -Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpwgt">; - -def int_hexagon_A2_vcmpwgtu : -Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpwgtu">; - -def int_hexagon_A4_vcmpweqi : -Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpweqi", [IntrNoMem, ImmArg>]>; - -def int_hexagon_A4_vcmpwgti : -Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpwgti", [IntrNoMem, ImmArg>]>; - -def int_hexagon_A4_vcmpwgtui : -Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpwgtui", [IntrNoMem, ImmArg>]>; - -def int_hexagon_A4_boundscheck : -Hexagon_i32_i32i64_Intrinsic<"HEXAGON_A4_boundscheck">; - -def int_hexagon_A4_tlbmatch : -Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_tlbmatch">; +def int_hexagon_C2_pxfer_map : +Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_pxfer_map">; def int_hexagon_C2_tfrpr : Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_tfrpr">; @@ -1345,503 +1787,230 @@ Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_tfrpr">; def int_hexagon_C2_tfrrp : Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_tfrrp">; +def int_hexagon_C2_vitpack : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_vitpack">; + +def int_hexagon_C2_vmux : +Hexagon_i64_i32i64i64_Intrinsic<"HEXAGON_C2_vmux">; + +def int_hexagon_C2_xor : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_xor">; + +def int_hexagon_C4_and_and : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_and">; + +def int_hexagon_C4_and_andn : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_andn">; + +def int_hexagon_C4_and_or : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_or">; + +def int_hexagon_C4_and_orn : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_orn">; + +def int_hexagon_C4_cmplte : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmplte">; + +def int_hexagon_C4_cmpltei : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmpltei", [IntrNoMem, ImmArg>]>; + +def int_hexagon_C4_cmplteu : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmplteu">; + +def int_hexagon_C4_cmplteui : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmplteui", [IntrNoMem, ImmArg>]>; + +def int_hexagon_C4_cmpneq : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmpneq">; + +def int_hexagon_C4_cmpneqi : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmpneqi", [IntrNoMem, ImmArg>]>; + def int_hexagon_C4_fastcorner9 : Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_fastcorner9">; def int_hexagon_C4_fastcorner9_not : Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_fastcorner9_not">; -def int_hexagon_M2_mpy_acc_hh_s0 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hh_s0">; +def int_hexagon_C4_nbitsclr : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_nbitsclr">; -def int_hexagon_M2_mpy_acc_hh_s1 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hh_s1">; +def int_hexagon_C4_nbitsclri : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_nbitsclri", [IntrNoMem, ImmArg>]>; -def int_hexagon_M2_mpy_acc_hl_s0 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hl_s0">; +def int_hexagon_C4_nbitsset : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_nbitsset">; -def int_hexagon_M2_mpy_acc_hl_s1 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hl_s1">; +def int_hexagon_C4_or_and : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_and">; -def int_hexagon_M2_mpy_acc_lh_s0 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_lh_s0">; +def int_hexagon_C4_or_andn : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_andn">; -def int_hexagon_M2_mpy_acc_lh_s1 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_lh_s1">; +def int_hexagon_C4_or_or : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_or">; -def int_hexagon_M2_mpy_acc_ll_s0 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_ll_s0">; +def int_hexagon_C4_or_orn : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_orn">; -def int_hexagon_M2_mpy_acc_ll_s1 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_ll_s1">; +def int_hexagon_F2_conv_d2df : +Hexagon_double_i64_Intrinsic<"HEXAGON_F2_conv_d2df">; -def int_hexagon_M2_mpy_nac_hh_s0 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hh_s0">; +def int_hexagon_F2_conv_d2sf : +Hexagon_float_i64_Intrinsic<"HEXAGON_F2_conv_d2sf">; -def int_hexagon_M2_mpy_nac_hh_s1 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hh_s1">; +def int_hexagon_F2_conv_df2d : +Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2d">; -def int_hexagon_M2_mpy_nac_hl_s0 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hl_s0">; +def int_hexagon_F2_conv_df2d_chop : +Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2d_chop">; -def int_hexagon_M2_mpy_nac_hl_s1 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hl_s1">; +def int_hexagon_F2_conv_df2sf : +Hexagon_float_double_Intrinsic<"HEXAGON_F2_conv_df2sf">; -def int_hexagon_M2_mpy_nac_lh_s0 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_lh_s0">; +def int_hexagon_F2_conv_df2ud : +Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2ud">; -def int_hexagon_M2_mpy_nac_lh_s1 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_lh_s1">; +def int_hexagon_F2_conv_df2ud_chop : +Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2ud_chop">; -def int_hexagon_M2_mpy_nac_ll_s0 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_ll_s0">; +def int_hexagon_F2_conv_df2uw : +Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2uw">; -def int_hexagon_M2_mpy_nac_ll_s1 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_ll_s1">; +def int_hexagon_F2_conv_df2uw_chop : +Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2uw_chop">; -def int_hexagon_M2_mpy_acc_sat_hh_s0 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hh_s0">; +def int_hexagon_F2_conv_df2w : +Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2w">; -def int_hexagon_M2_mpy_acc_sat_hh_s1 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hh_s1">; +def int_hexagon_F2_conv_df2w_chop : +Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2w_chop">; -def int_hexagon_M2_mpy_acc_sat_hl_s0 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hl_s0">; +def int_hexagon_F2_conv_sf2d : +Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2d">; -def int_hexagon_M2_mpy_acc_sat_hl_s1 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hl_s1">; +def int_hexagon_F2_conv_sf2d_chop : +Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2d_chop">; -def int_hexagon_M2_mpy_acc_sat_lh_s0 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_lh_s0">; +def int_hexagon_F2_conv_sf2df : +Hexagon_double_float_Intrinsic<"HEXAGON_F2_conv_sf2df">; -def int_hexagon_M2_mpy_acc_sat_lh_s1 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_lh_s1">; +def int_hexagon_F2_conv_sf2ud : +Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2ud">; -def int_hexagon_M2_mpy_acc_sat_ll_s0 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_ll_s0">; +def int_hexagon_F2_conv_sf2ud_chop : +Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2ud_chop">; -def int_hexagon_M2_mpy_acc_sat_ll_s1 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_ll_s1">; +def int_hexagon_F2_conv_sf2uw : +Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2uw">; -def int_hexagon_M2_mpy_nac_sat_hh_s0 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hh_s0">; +def int_hexagon_F2_conv_sf2uw_chop : +Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2uw_chop">; -def int_hexagon_M2_mpy_nac_sat_hh_s1 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hh_s1">; +def int_hexagon_F2_conv_sf2w : +Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2w">; -def int_hexagon_M2_mpy_nac_sat_hl_s0 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hl_s0">; +def int_hexagon_F2_conv_sf2w_chop : +Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2w_chop">; -def int_hexagon_M2_mpy_nac_sat_hl_s1 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hl_s1">; +def int_hexagon_F2_conv_ud2df : +Hexagon_double_i64_Intrinsic<"HEXAGON_F2_conv_ud2df">; -def int_hexagon_M2_mpy_nac_sat_lh_s0 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_lh_s0">; +def int_hexagon_F2_conv_ud2sf : +Hexagon_float_i64_Intrinsic<"HEXAGON_F2_conv_ud2sf">; -def int_hexagon_M2_mpy_nac_sat_lh_s1 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_lh_s1">; +def int_hexagon_F2_conv_uw2df : +Hexagon_double_i32_Intrinsic<"HEXAGON_F2_conv_uw2df">; -def int_hexagon_M2_mpy_nac_sat_ll_s0 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_ll_s0">; +def int_hexagon_F2_conv_uw2sf : +Hexagon_float_i32_Intrinsic<"HEXAGON_F2_conv_uw2sf">; -def int_hexagon_M2_mpy_nac_sat_ll_s1 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_ll_s1">; +def int_hexagon_F2_conv_w2df : +Hexagon_double_i32_Intrinsic<"HEXAGON_F2_conv_w2df">; -def int_hexagon_M2_mpy_hh_s0 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hh_s0">; +def int_hexagon_F2_conv_w2sf : +Hexagon_float_i32_Intrinsic<"HEXAGON_F2_conv_w2sf">; -def int_hexagon_M2_mpy_hh_s1 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hh_s1">; +def int_hexagon_F2_dfclass : +Hexagon_i32_doublei32_Intrinsic<"HEXAGON_F2_dfclass", [IntrNoMem, Throws, ImmArg>]>; -def int_hexagon_M2_mpy_hl_s0 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hl_s0">; +def int_hexagon_F2_dfcmpeq : +Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpeq", [IntrNoMem, Throws]>; -def int_hexagon_M2_mpy_hl_s1 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hl_s1">; +def int_hexagon_F2_dfcmpge : +Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpge", [IntrNoMem, Throws]>; -def int_hexagon_M2_mpy_lh_s0 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_lh_s0">; +def int_hexagon_F2_dfcmpgt : +Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpgt", [IntrNoMem, Throws]>; -def int_hexagon_M2_mpy_lh_s1 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_lh_s1">; +def int_hexagon_F2_dfcmpuo : +Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpuo", [IntrNoMem, Throws]>; -def int_hexagon_M2_mpy_ll_s0 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_ll_s0">; +def int_hexagon_F2_dfimm_n : +Hexagon_double_i32_Intrinsic<"HEXAGON_F2_dfimm_n", [IntrNoMem, Throws, ImmArg>]>; -def int_hexagon_M2_mpy_ll_s1 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_ll_s1">; +def int_hexagon_F2_dfimm_p : +Hexagon_double_i32_Intrinsic<"HEXAGON_F2_dfimm_p", [IntrNoMem, Throws, ImmArg>]>; -def int_hexagon_M2_mpy_sat_hh_s0 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hh_s0">; +def int_hexagon_F2_sfadd : +Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfadd", [IntrNoMem, Throws]>; -def int_hexagon_M2_mpy_sat_hh_s1 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hh_s1">; +def int_hexagon_F2_sfclass : +Hexagon_i32_floati32_Intrinsic<"HEXAGON_F2_sfclass", [IntrNoMem, Throws, ImmArg>]>; -def int_hexagon_M2_mpy_sat_hl_s0 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hl_s0">; +def int_hexagon_F2_sfcmpeq : +Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpeq", [IntrNoMem, Throws]>; -def int_hexagon_M2_mpy_sat_hl_s1 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hl_s1">; +def int_hexagon_F2_sfcmpge : +Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpge", [IntrNoMem, Throws]>; -def int_hexagon_M2_mpy_sat_lh_s0 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_lh_s0">; +def int_hexagon_F2_sfcmpgt : +Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpgt", [IntrNoMem, Throws]>; -def int_hexagon_M2_mpy_sat_lh_s1 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_lh_s1">; +def int_hexagon_F2_sfcmpuo : +Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpuo", [IntrNoMem, Throws]>; -def int_hexagon_M2_mpy_sat_ll_s0 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_ll_s0">; +def int_hexagon_F2_sffixupd : +Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sffixupd", [IntrNoMem, Throws]>; -def int_hexagon_M2_mpy_sat_ll_s1 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_ll_s1">; +def int_hexagon_F2_sffixupn : +Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sffixupn", [IntrNoMem, Throws]>; -def int_hexagon_M2_mpy_rnd_hh_s0 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hh_s0">; +def int_hexagon_F2_sffixupr : +Hexagon_float_float_Intrinsic<"HEXAGON_F2_sffixupr", [IntrNoMem, Throws]>; -def int_hexagon_M2_mpy_rnd_hh_s1 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hh_s1">; +def int_hexagon_F2_sffma : +Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffma", [IntrNoMem, Throws]>; -def int_hexagon_M2_mpy_rnd_hl_s0 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hl_s0">; +def int_hexagon_F2_sffma_lib : +Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffma_lib", [IntrNoMem, Throws]>; -def int_hexagon_M2_mpy_rnd_hl_s1 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hl_s1">; +def int_hexagon_F2_sffma_sc : +Hexagon_float_floatfloatfloati32_Intrinsic<"HEXAGON_F2_sffma_sc", [IntrNoMem, Throws]>; -def int_hexagon_M2_mpy_rnd_lh_s0 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_lh_s0">; +def int_hexagon_F2_sffms : +Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffms", [IntrNoMem, Throws]>; -def int_hexagon_M2_mpy_rnd_lh_s1 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_lh_s1">; +def int_hexagon_F2_sffms_lib : +Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffms_lib", [IntrNoMem, Throws]>; -def int_hexagon_M2_mpy_rnd_ll_s0 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_ll_s0">; +def int_hexagon_F2_sfimm_n : +Hexagon_float_i32_Intrinsic<"HEXAGON_F2_sfimm_n", [IntrNoMem, Throws, ImmArg>]>; -def int_hexagon_M2_mpy_rnd_ll_s1 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_ll_s1">; +def int_hexagon_F2_sfimm_p : +Hexagon_float_i32_Intrinsic<"HEXAGON_F2_sfimm_p", [IntrNoMem, Throws, ImmArg>]>; -def int_hexagon_M2_mpy_sat_rnd_hh_s0 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hh_s0">; +def int_hexagon_F2_sfmax : +Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfmax", [IntrNoMem, Throws]>; -def int_hexagon_M2_mpy_sat_rnd_hh_s1 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hh_s1">; +def int_hexagon_F2_sfmin : +Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfmin", [IntrNoMem, Throws]>; -def int_hexagon_M2_mpy_sat_rnd_hl_s0 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hl_s0">; +def int_hexagon_F2_sfmpy : +Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfmpy", [IntrNoMem, Throws]>; -def int_hexagon_M2_mpy_sat_rnd_hl_s1 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hl_s1">; - -def int_hexagon_M2_mpy_sat_rnd_lh_s0 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_lh_s0">; - -def int_hexagon_M2_mpy_sat_rnd_lh_s1 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_lh_s1">; - -def int_hexagon_M2_mpy_sat_rnd_ll_s0 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_ll_s0">; - -def int_hexagon_M2_mpy_sat_rnd_ll_s1 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_ll_s1">; - -def int_hexagon_M2_mpyd_acc_hh_s0 : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hh_s0">; - -def int_hexagon_M2_mpyd_acc_hh_s1 : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hh_s1">; - -def int_hexagon_M2_mpyd_acc_hl_s0 : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hl_s0">; - -def int_hexagon_M2_mpyd_acc_hl_s1 : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hl_s1">; - -def int_hexagon_M2_mpyd_acc_lh_s0 : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_lh_s0">; - -def int_hexagon_M2_mpyd_acc_lh_s1 : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_lh_s1">; - -def int_hexagon_M2_mpyd_acc_ll_s0 : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_ll_s0">; - -def int_hexagon_M2_mpyd_acc_ll_s1 : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_ll_s1">; - -def int_hexagon_M2_mpyd_nac_hh_s0 : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hh_s0">; - -def int_hexagon_M2_mpyd_nac_hh_s1 : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hh_s1">; - -def int_hexagon_M2_mpyd_nac_hl_s0 : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hl_s0">; - -def int_hexagon_M2_mpyd_nac_hl_s1 : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hl_s1">; - -def int_hexagon_M2_mpyd_nac_lh_s0 : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_lh_s0">; - -def int_hexagon_M2_mpyd_nac_lh_s1 : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_lh_s1">; - -def int_hexagon_M2_mpyd_nac_ll_s0 : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_ll_s0">; - -def int_hexagon_M2_mpyd_nac_ll_s1 : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_ll_s1">; - -def int_hexagon_M2_mpyd_hh_s0 : -Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hh_s0">; - -def int_hexagon_M2_mpyd_hh_s1 : -Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hh_s1">; - -def int_hexagon_M2_mpyd_hl_s0 : -Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hl_s0">; - -def int_hexagon_M2_mpyd_hl_s1 : -Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hl_s1">; - -def int_hexagon_M2_mpyd_lh_s0 : -Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_lh_s0">; - -def int_hexagon_M2_mpyd_lh_s1 : -Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_lh_s1">; - -def int_hexagon_M2_mpyd_ll_s0 : -Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_ll_s0">; - -def int_hexagon_M2_mpyd_ll_s1 : -Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_ll_s1">; - -def int_hexagon_M2_mpyd_rnd_hh_s0 : -Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hh_s0">; - -def int_hexagon_M2_mpyd_rnd_hh_s1 : -Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hh_s1">; - -def int_hexagon_M2_mpyd_rnd_hl_s0 : -Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hl_s0">; - -def int_hexagon_M2_mpyd_rnd_hl_s1 : -Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hl_s1">; - -def int_hexagon_M2_mpyd_rnd_lh_s0 : -Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_lh_s0">; - -def int_hexagon_M2_mpyd_rnd_lh_s1 : -Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_lh_s1">; - -def int_hexagon_M2_mpyd_rnd_ll_s0 : -Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_ll_s0">; - -def int_hexagon_M2_mpyd_rnd_ll_s1 : -Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_ll_s1">; - -def int_hexagon_M2_mpyu_acc_hh_s0 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hh_s0">; - -def int_hexagon_M2_mpyu_acc_hh_s1 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hh_s1">; - -def int_hexagon_M2_mpyu_acc_hl_s0 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hl_s0">; - -def int_hexagon_M2_mpyu_acc_hl_s1 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hl_s1">; - -def int_hexagon_M2_mpyu_acc_lh_s0 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_lh_s0">; - -def int_hexagon_M2_mpyu_acc_lh_s1 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_lh_s1">; - -def int_hexagon_M2_mpyu_acc_ll_s0 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_ll_s0">; - -def int_hexagon_M2_mpyu_acc_ll_s1 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_ll_s1">; - -def int_hexagon_M2_mpyu_nac_hh_s0 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hh_s0">; - -def int_hexagon_M2_mpyu_nac_hh_s1 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hh_s1">; - -def int_hexagon_M2_mpyu_nac_hl_s0 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hl_s0">; - -def int_hexagon_M2_mpyu_nac_hl_s1 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hl_s1">; - -def int_hexagon_M2_mpyu_nac_lh_s0 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_lh_s0">; - -def int_hexagon_M2_mpyu_nac_lh_s1 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_lh_s1">; - -def int_hexagon_M2_mpyu_nac_ll_s0 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_ll_s0">; - -def int_hexagon_M2_mpyu_nac_ll_s1 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_ll_s1">; - -def int_hexagon_M2_mpyu_hh_s0 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hh_s0">; - -def int_hexagon_M2_mpyu_hh_s1 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hh_s1">; - -def int_hexagon_M2_mpyu_hl_s0 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hl_s0">; - -def int_hexagon_M2_mpyu_hl_s1 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hl_s1">; - -def int_hexagon_M2_mpyu_lh_s0 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_lh_s0">; - -def int_hexagon_M2_mpyu_lh_s1 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_lh_s1">; - -def int_hexagon_M2_mpyu_ll_s0 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_ll_s0">; - -def int_hexagon_M2_mpyu_ll_s1 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_ll_s1">; - -def int_hexagon_M2_mpyud_acc_hh_s0 : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hh_s0">; - -def int_hexagon_M2_mpyud_acc_hh_s1 : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hh_s1">; - -def int_hexagon_M2_mpyud_acc_hl_s0 : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hl_s0">; - -def int_hexagon_M2_mpyud_acc_hl_s1 : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hl_s1">; - -def int_hexagon_M2_mpyud_acc_lh_s0 : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_lh_s0">; - -def int_hexagon_M2_mpyud_acc_lh_s1 : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_lh_s1">; - -def int_hexagon_M2_mpyud_acc_ll_s0 : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_ll_s0">; - -def int_hexagon_M2_mpyud_acc_ll_s1 : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_ll_s1">; - -def int_hexagon_M2_mpyud_nac_hh_s0 : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hh_s0">; - -def int_hexagon_M2_mpyud_nac_hh_s1 : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hh_s1">; - -def int_hexagon_M2_mpyud_nac_hl_s0 : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hl_s0">; - -def int_hexagon_M2_mpyud_nac_hl_s1 : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hl_s1">; - -def int_hexagon_M2_mpyud_nac_lh_s0 : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_lh_s0">; - -def int_hexagon_M2_mpyud_nac_lh_s1 : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_lh_s1">; - -def int_hexagon_M2_mpyud_nac_ll_s0 : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_ll_s0">; - -def int_hexagon_M2_mpyud_nac_ll_s1 : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_ll_s1">; - -def int_hexagon_M2_mpyud_hh_s0 : -Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hh_s0">; - -def int_hexagon_M2_mpyud_hh_s1 : -Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hh_s1">; - -def int_hexagon_M2_mpyud_hl_s0 : -Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hl_s0">; - -def int_hexagon_M2_mpyud_hl_s1 : -Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hl_s1">; - -def int_hexagon_M2_mpyud_lh_s0 : -Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_lh_s0">; - -def int_hexagon_M2_mpyud_lh_s1 : -Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_lh_s1">; - -def int_hexagon_M2_mpyud_ll_s0 : -Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_ll_s0">; - -def int_hexagon_M2_mpyud_ll_s1 : -Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_ll_s1">; - -def int_hexagon_M2_mpysmi : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysmi", [IntrNoMem, ImmArg>]>; - -def int_hexagon_M2_macsip : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_macsip", [IntrNoMem, ImmArg>]>; - -def int_hexagon_M2_macsin : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_macsin", [IntrNoMem, ImmArg>]>; - -def int_hexagon_M2_dpmpyss_s0 : -Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_s0">; - -def int_hexagon_M2_dpmpyss_acc_s0 : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_acc_s0">; - -def int_hexagon_M2_dpmpyss_nac_s0 : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_nac_s0">; - -def int_hexagon_M2_dpmpyuu_s0 : -Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_dpmpyuu_s0">; - -def int_hexagon_M2_dpmpyuu_acc_s0 : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyuu_acc_s0">; - -def int_hexagon_M2_dpmpyuu_nac_s0 : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyuu_nac_s0">; - -def int_hexagon_M2_mpy_up : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_up">; - -def int_hexagon_M2_mpy_up_s1 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_up_s1">; - -def int_hexagon_M2_mpy_up_s1_sat : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_up_s1_sat">; - -def int_hexagon_M2_mpyu_up : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_up">; - -def int_hexagon_M2_mpysu_up : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysu_up">; - -def int_hexagon_M2_dpmpyss_rnd_s0 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_rnd_s0">; - -def int_hexagon_M4_mac_up_s1_sat : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mac_up_s1_sat">; - -def int_hexagon_M4_nac_up_s1_sat : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_nac_up_s1_sat">; - -def int_hexagon_M2_mpyi : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyi">; - -def int_hexagon_M2_mpyui : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyui">; - -def int_hexagon_M2_maci : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_maci">; +def int_hexagon_F2_sfsub : +Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfsub", [IntrNoMem, Throws]>; def int_hexagon_M2_acci : Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_acci">; @@ -1849,143 +2018,11 @@ Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_acci">; def int_hexagon_M2_accii : Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_accii", [IntrNoMem, ImmArg>]>; -def int_hexagon_M2_nacci : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_nacci">; +def int_hexagon_M2_cmaci_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmaci_s0">; -def int_hexagon_M2_naccii : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_naccii", [IntrNoMem, ImmArg>]>; - -def int_hexagon_M2_subacc : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_subacc">; - -def int_hexagon_M4_mpyrr_addr : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyrr_addr">; - -def int_hexagon_M4_mpyri_addr_u2 : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addr_u2", [IntrNoMem, ImmArg>]>; - -def int_hexagon_M4_mpyri_addr : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addr", [IntrNoMem, ImmArg>]>; - -def int_hexagon_M4_mpyri_addi : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addi", [IntrNoMem, ImmArg>, ImmArg>]>; - -def int_hexagon_M4_mpyrr_addi : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyrr_addi", [IntrNoMem, ImmArg>]>; - -def int_hexagon_M2_vmpy2s_s0 : -Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s0">; - -def int_hexagon_M2_vmpy2s_s1 : -Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s1">; - -def int_hexagon_M2_vmac2s_s0 : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2s_s0">; - -def int_hexagon_M2_vmac2s_s1 : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2s_s1">; - -def int_hexagon_M2_vmpy2su_s0 : -Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2su_s0">; - -def int_hexagon_M2_vmpy2su_s1 : -Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2su_s1">; - -def int_hexagon_M2_vmac2su_s0 : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2su_s0">; - -def int_hexagon_M2_vmac2su_s1 : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2su_s1">; - -def int_hexagon_M2_vmpy2s_s0pack : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s0pack">; - -def int_hexagon_M2_vmpy2s_s1pack : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s1pack">; - -def int_hexagon_M2_vmac2 : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2">; - -def int_hexagon_M2_vmpy2es_s0 : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vmpy2es_s0">; - -def int_hexagon_M2_vmpy2es_s1 : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vmpy2es_s1">; - -def int_hexagon_M2_vmac2es_s0 : -Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vmac2es_s0">; - -def int_hexagon_M2_vmac2es_s1 : -Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vmac2es_s1">; - -def int_hexagon_M2_vmac2es : -Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vmac2es">; - -def int_hexagon_M2_vrmac_s0 : -Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrmac_s0">; - -def int_hexagon_M2_vrmpy_s0 : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrmpy_s0">; - -def int_hexagon_M2_vdmpyrs_s0 : -Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vdmpyrs_s0">; - -def int_hexagon_M2_vdmpyrs_s1 : -Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vdmpyrs_s1">; - -def int_hexagon_M5_vrmpybuu : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M5_vrmpybuu">; - -def int_hexagon_M5_vrmacbuu : -Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M5_vrmacbuu">; - -def int_hexagon_M5_vrmpybsu : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M5_vrmpybsu">; - -def int_hexagon_M5_vrmacbsu : -Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M5_vrmacbsu">; - -def int_hexagon_M5_vmpybuu : -Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M5_vmpybuu">; - -def int_hexagon_M5_vmpybsu : -Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M5_vmpybsu">; - -def int_hexagon_M5_vmacbuu : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M5_vmacbuu">; - -def int_hexagon_M5_vmacbsu : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M5_vmacbsu">; - -def int_hexagon_M5_vdmpybsu : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M5_vdmpybsu">; - -def int_hexagon_M5_vdmacbsu : -Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M5_vdmacbsu">; - -def int_hexagon_M2_vdmacs_s0 : -Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vdmacs_s0">; - -def int_hexagon_M2_vdmacs_s1 : -Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vdmacs_s1">; - -def int_hexagon_M2_vdmpys_s0 : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vdmpys_s0">; - -def int_hexagon_M2_vdmpys_s1 : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vdmpys_s1">; - -def int_hexagon_M2_cmpyrs_s0 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrs_s0">; - -def int_hexagon_M2_cmpyrs_s1 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrs_s1">; - -def int_hexagon_M2_cmpyrsc_s0 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrsc_s0">; - -def int_hexagon_M2_cmpyrsc_s1 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrsc_s1">; +def int_hexagon_M2_cmacr_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacr_s0">; def int_hexagon_M2_cmacs_s0 : Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacs_s0">; @@ -1999,6 +2036,24 @@ Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacsc_s0">; def int_hexagon_M2_cmacsc_s1 : Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacsc_s1">; +def int_hexagon_M2_cmpyi_s0 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpyi_s0">; + +def int_hexagon_M2_cmpyr_s0 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpyr_s0">; + +def int_hexagon_M2_cmpyrs_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrs_s0">; + +def int_hexagon_M2_cmpyrs_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrs_s1">; + +def int_hexagon_M2_cmpyrsc_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrsc_s0">; + +def int_hexagon_M2_cmpyrsc_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrsc_s1">; + def int_hexagon_M2_cmpys_s0 : Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpys_s0">; @@ -2023,44 +2078,47 @@ Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacsc_s0">; def int_hexagon_M2_cnacsc_s1 : Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacsc_s1">; -def int_hexagon_M2_vrcmpys_s1 : -Hexagon_i64_i64i32_Intrinsic<"HEXAGON_M2_vrcmpys_s1">; +def int_hexagon_M2_dpmpyss_acc_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_acc_s0">; -def int_hexagon_M2_vrcmpys_acc_s1 : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_M2_vrcmpys_acc_s1">; +def int_hexagon_M2_dpmpyss_nac_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_nac_s0">; -def int_hexagon_M2_vrcmpys_s1rp : -Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M2_vrcmpys_s1rp">; +def int_hexagon_M2_dpmpyss_rnd_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_rnd_s0">; -def int_hexagon_M2_mmacls_s0 : -Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_s0">; +def int_hexagon_M2_dpmpyss_s0 : +Hexagon_custom_i64_i32i32_Intrinsic; -def int_hexagon_M2_mmacls_s1 : -Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_s1">; +def int_hexagon_M2_dpmpyuu_acc_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyuu_acc_s0">; -def int_hexagon_M2_mmachs_s0 : -Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_s0">; +def int_hexagon_M2_dpmpyuu_nac_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyuu_nac_s0">; -def int_hexagon_M2_mmachs_s1 : -Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_s1">; +def int_hexagon_M2_dpmpyuu_s0 : +Hexagon_custom_i64_i32i32_Intrinsic; -def int_hexagon_M2_mmpyl_s0 : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_s0">; +def int_hexagon_M2_hmmpyh_rs1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyh_rs1">; -def int_hexagon_M2_mmpyl_s1 : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_s1">; +def int_hexagon_M2_hmmpyh_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyh_s1">; -def int_hexagon_M2_mmpyh_s0 : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_s0">; +def int_hexagon_M2_hmmpyl_rs1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyl_rs1">; -def int_hexagon_M2_mmpyh_s1 : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_s1">; +def int_hexagon_M2_hmmpyl_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyl_s1">; -def int_hexagon_M2_mmacls_rs0 : -Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_rs0">; +def int_hexagon_M2_maci : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_maci">; -def int_hexagon_M2_mmacls_rs1 : -Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_rs1">; +def int_hexagon_M2_macsin : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_macsin", [IntrNoMem, ImmArg>]>; + +def int_hexagon_M2_macsip : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_macsip", [IntrNoMem, ImmArg>]>; def int_hexagon_M2_mmachs_rs0 : Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_rs0">; @@ -2068,83 +2126,23 @@ Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_rs0">; def int_hexagon_M2_mmachs_rs1 : Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_rs1">; -def int_hexagon_M2_mmpyl_rs0 : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_rs0">; +def int_hexagon_M2_mmachs_s0 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_s0">; -def int_hexagon_M2_mmpyl_rs1 : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_rs1">; +def int_hexagon_M2_mmachs_s1 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_s1">; -def int_hexagon_M2_mmpyh_rs0 : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_rs0">; +def int_hexagon_M2_mmacls_rs0 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_rs0">; -def int_hexagon_M2_mmpyh_rs1 : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_rs1">; +def int_hexagon_M2_mmacls_rs1 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_rs1">; -def int_hexagon_M4_vrmpyeh_s0 : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_s0">; +def int_hexagon_M2_mmacls_s0 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_s0">; -def int_hexagon_M4_vrmpyeh_s1 : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_s1">; - -def int_hexagon_M4_vrmpyeh_acc_s0 : -Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_acc_s0">; - -def int_hexagon_M4_vrmpyeh_acc_s1 : -Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_acc_s1">; - -def int_hexagon_M4_vrmpyoh_s0 : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_s0">; - -def int_hexagon_M4_vrmpyoh_s1 : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_s1">; - -def int_hexagon_M4_vrmpyoh_acc_s0 : -Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_acc_s0">; - -def int_hexagon_M4_vrmpyoh_acc_s1 : -Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_acc_s1">; - -def int_hexagon_M2_hmmpyl_rs1 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyl_rs1">; - -def int_hexagon_M2_hmmpyh_rs1 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyh_rs1">; - -def int_hexagon_M2_hmmpyl_s1 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyl_s1">; - -def int_hexagon_M2_hmmpyh_s1 : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyh_s1">; - -def int_hexagon_M2_mmaculs_s0 : -Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_s0">; - -def int_hexagon_M2_mmaculs_s1 : -Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_s1">; - -def int_hexagon_M2_mmacuhs_s0 : -Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_s0">; - -def int_hexagon_M2_mmacuhs_s1 : -Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_s1">; - -def int_hexagon_M2_mmpyul_s0 : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_s0">; - -def int_hexagon_M2_mmpyul_s1 : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_s1">; - -def int_hexagon_M2_mmpyuh_s0 : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_s0">; - -def int_hexagon_M2_mmpyuh_s1 : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_s1">; - -def int_hexagon_M2_mmaculs_rs0 : -Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_rs0">; - -def int_hexagon_M2_mmaculs_rs1 : -Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_rs1">; +def int_hexagon_M2_mmacls_s1 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_s1">; def int_hexagon_M2_mmacuhs_rs0 : Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_rs0">; @@ -2152,11 +2150,47 @@ Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_rs0">; def int_hexagon_M2_mmacuhs_rs1 : Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_rs1">; -def int_hexagon_M2_mmpyul_rs0 : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_rs0">; +def int_hexagon_M2_mmacuhs_s0 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_s0">; -def int_hexagon_M2_mmpyul_rs1 : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_rs1">; +def int_hexagon_M2_mmacuhs_s1 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_s1">; + +def int_hexagon_M2_mmaculs_rs0 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_rs0">; + +def int_hexagon_M2_mmaculs_rs1 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_rs1">; + +def int_hexagon_M2_mmaculs_s0 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_s0">; + +def int_hexagon_M2_mmaculs_s1 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_s1">; + +def int_hexagon_M2_mmpyh_rs0 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_rs0">; + +def int_hexagon_M2_mmpyh_rs1 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_rs1">; + +def int_hexagon_M2_mmpyh_s0 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_s0">; + +def int_hexagon_M2_mmpyh_s1 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_s1">; + +def int_hexagon_M2_mmpyl_rs0 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_rs0">; + +def int_hexagon_M2_mmpyl_rs1 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_rs1">; + +def int_hexagon_M2_mmpyl_s0 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_s0">; + +def int_hexagon_M2_mmpyl_s1 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_s1">; def int_hexagon_M2_mmpyuh_rs0 : Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_rs0">; @@ -2164,53 +2198,500 @@ Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_rs0">; def int_hexagon_M2_mmpyuh_rs1 : Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_rs1">; -def int_hexagon_M2_vrcmaci_s0 : -Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmaci_s0">; +def int_hexagon_M2_mmpyuh_s0 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_s0">; -def int_hexagon_M2_vrcmacr_s0 : -Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmacr_s0">; +def int_hexagon_M2_mmpyuh_s1 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_s1">; -def int_hexagon_M2_vrcmaci_s0c : -Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmaci_s0c">; +def int_hexagon_M2_mmpyul_rs0 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_rs0">; -def int_hexagon_M2_vrcmacr_s0c : -Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmacr_s0c">; +def int_hexagon_M2_mmpyul_rs1 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_rs1">; -def int_hexagon_M2_cmaci_s0 : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmaci_s0">; +def int_hexagon_M2_mmpyul_s0 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_s0">; -def int_hexagon_M2_cmacr_s0 : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacr_s0">; +def int_hexagon_M2_mmpyul_s1 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_s1">; -def int_hexagon_M2_vrcmpyi_s0 : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyi_s0">; +def int_hexagon_M2_mpy_acc_hh_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hh_s0">; -def int_hexagon_M2_vrcmpyr_s0 : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyr_s0">; +def int_hexagon_M2_mpy_acc_hh_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hh_s1">; -def int_hexagon_M2_vrcmpyi_s0c : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyi_s0c">; +def int_hexagon_M2_mpy_acc_hl_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hl_s0">; -def int_hexagon_M2_vrcmpyr_s0c : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyr_s0c">; +def int_hexagon_M2_mpy_acc_hl_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hl_s1">; -def int_hexagon_M2_cmpyi_s0 : -Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpyi_s0">; +def int_hexagon_M2_mpy_acc_lh_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_lh_s0">; -def int_hexagon_M2_cmpyr_s0 : -Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpyr_s0">; +def int_hexagon_M2_mpy_acc_lh_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_lh_s1">; -def int_hexagon_M4_cmpyi_wh : -Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyi_wh">; +def int_hexagon_M2_mpy_acc_ll_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_ll_s0">; -def int_hexagon_M4_cmpyr_wh : -Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyr_wh">; +def int_hexagon_M2_mpy_acc_ll_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_ll_s1">; -def int_hexagon_M4_cmpyi_whc : -Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyi_whc">; +def int_hexagon_M2_mpy_acc_sat_hh_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hh_s0">; -def int_hexagon_M4_cmpyr_whc : -Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyr_whc">; +def int_hexagon_M2_mpy_acc_sat_hh_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hh_s1">; + +def int_hexagon_M2_mpy_acc_sat_hl_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hl_s0">; + +def int_hexagon_M2_mpy_acc_sat_hl_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hl_s1">; + +def int_hexagon_M2_mpy_acc_sat_lh_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_lh_s0">; + +def int_hexagon_M2_mpy_acc_sat_lh_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_lh_s1">; + +def int_hexagon_M2_mpy_acc_sat_ll_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_ll_s0">; + +def int_hexagon_M2_mpy_acc_sat_ll_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_ll_s1">; + +def int_hexagon_M2_mpy_hh_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hh_s0">; + +def int_hexagon_M2_mpy_hh_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hh_s1">; + +def int_hexagon_M2_mpy_hl_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hl_s0">; + +def int_hexagon_M2_mpy_hl_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hl_s1">; + +def int_hexagon_M2_mpy_lh_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_lh_s0">; + +def int_hexagon_M2_mpy_lh_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_lh_s1">; + +def int_hexagon_M2_mpy_ll_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_ll_s0">; + +def int_hexagon_M2_mpy_ll_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_ll_s1">; + +def int_hexagon_M2_mpy_nac_hh_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hh_s0">; + +def int_hexagon_M2_mpy_nac_hh_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hh_s1">; + +def int_hexagon_M2_mpy_nac_hl_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hl_s0">; + +def int_hexagon_M2_mpy_nac_hl_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hl_s1">; + +def int_hexagon_M2_mpy_nac_lh_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_lh_s0">; + +def int_hexagon_M2_mpy_nac_lh_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_lh_s1">; + +def int_hexagon_M2_mpy_nac_ll_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_ll_s0">; + +def int_hexagon_M2_mpy_nac_ll_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_ll_s1">; + +def int_hexagon_M2_mpy_nac_sat_hh_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hh_s0">; + +def int_hexagon_M2_mpy_nac_sat_hh_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hh_s1">; + +def int_hexagon_M2_mpy_nac_sat_hl_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hl_s0">; + +def int_hexagon_M2_mpy_nac_sat_hl_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hl_s1">; + +def int_hexagon_M2_mpy_nac_sat_lh_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_lh_s0">; + +def int_hexagon_M2_mpy_nac_sat_lh_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_lh_s1">; + +def int_hexagon_M2_mpy_nac_sat_ll_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_ll_s0">; + +def int_hexagon_M2_mpy_nac_sat_ll_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_ll_s1">; + +def int_hexagon_M2_mpy_rnd_hh_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hh_s0">; + +def int_hexagon_M2_mpy_rnd_hh_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hh_s1">; + +def int_hexagon_M2_mpy_rnd_hl_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hl_s0">; + +def int_hexagon_M2_mpy_rnd_hl_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hl_s1">; + +def int_hexagon_M2_mpy_rnd_lh_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_lh_s0">; + +def int_hexagon_M2_mpy_rnd_lh_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_lh_s1">; + +def int_hexagon_M2_mpy_rnd_ll_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_ll_s0">; + +def int_hexagon_M2_mpy_rnd_ll_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_ll_s1">; + +def int_hexagon_M2_mpy_sat_hh_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hh_s0">; + +def int_hexagon_M2_mpy_sat_hh_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hh_s1">; + +def int_hexagon_M2_mpy_sat_hl_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hl_s0">; + +def int_hexagon_M2_mpy_sat_hl_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hl_s1">; + +def int_hexagon_M2_mpy_sat_lh_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_lh_s0">; + +def int_hexagon_M2_mpy_sat_lh_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_lh_s1">; + +def int_hexagon_M2_mpy_sat_ll_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_ll_s0">; + +def int_hexagon_M2_mpy_sat_ll_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_ll_s1">; + +def int_hexagon_M2_mpy_sat_rnd_hh_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hh_s0">; + +def int_hexagon_M2_mpy_sat_rnd_hh_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hh_s1">; + +def int_hexagon_M2_mpy_sat_rnd_hl_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hl_s0">; + +def int_hexagon_M2_mpy_sat_rnd_hl_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hl_s1">; + +def int_hexagon_M2_mpy_sat_rnd_lh_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_lh_s0">; + +def int_hexagon_M2_mpy_sat_rnd_lh_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_lh_s1">; + +def int_hexagon_M2_mpy_sat_rnd_ll_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_ll_s0">; + +def int_hexagon_M2_mpy_sat_rnd_ll_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_ll_s1">; + +def int_hexagon_M2_mpy_up : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_up">; + +def int_hexagon_M2_mpy_up_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_up_s1">; + +def int_hexagon_M2_mpy_up_s1_sat : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_up_s1_sat">; + +def int_hexagon_M2_mpyd_acc_hh_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hh_s0">; + +def int_hexagon_M2_mpyd_acc_hh_s1 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hh_s1">; + +def int_hexagon_M2_mpyd_acc_hl_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hl_s0">; + +def int_hexagon_M2_mpyd_acc_hl_s1 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hl_s1">; + +def int_hexagon_M2_mpyd_acc_lh_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_lh_s0">; + +def int_hexagon_M2_mpyd_acc_lh_s1 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_lh_s1">; + +def int_hexagon_M2_mpyd_acc_ll_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_ll_s0">; + +def int_hexagon_M2_mpyd_acc_ll_s1 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_ll_s1">; + +def int_hexagon_M2_mpyd_hh_s0 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hh_s0">; + +def int_hexagon_M2_mpyd_hh_s1 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hh_s1">; + +def int_hexagon_M2_mpyd_hl_s0 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hl_s0">; + +def int_hexagon_M2_mpyd_hl_s1 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hl_s1">; + +def int_hexagon_M2_mpyd_lh_s0 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_lh_s0">; + +def int_hexagon_M2_mpyd_lh_s1 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_lh_s1">; + +def int_hexagon_M2_mpyd_ll_s0 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_ll_s0">; + +def int_hexagon_M2_mpyd_ll_s1 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_ll_s1">; + +def int_hexagon_M2_mpyd_nac_hh_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hh_s0">; + +def int_hexagon_M2_mpyd_nac_hh_s1 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hh_s1">; + +def int_hexagon_M2_mpyd_nac_hl_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hl_s0">; + +def int_hexagon_M2_mpyd_nac_hl_s1 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hl_s1">; + +def int_hexagon_M2_mpyd_nac_lh_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_lh_s0">; + +def int_hexagon_M2_mpyd_nac_lh_s1 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_lh_s1">; + +def int_hexagon_M2_mpyd_nac_ll_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_ll_s0">; + +def int_hexagon_M2_mpyd_nac_ll_s1 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_ll_s1">; + +def int_hexagon_M2_mpyd_rnd_hh_s0 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hh_s0">; + +def int_hexagon_M2_mpyd_rnd_hh_s1 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hh_s1">; + +def int_hexagon_M2_mpyd_rnd_hl_s0 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hl_s0">; + +def int_hexagon_M2_mpyd_rnd_hl_s1 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hl_s1">; + +def int_hexagon_M2_mpyd_rnd_lh_s0 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_lh_s0">; + +def int_hexagon_M2_mpyd_rnd_lh_s1 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_lh_s1">; + +def int_hexagon_M2_mpyd_rnd_ll_s0 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_ll_s0">; + +def int_hexagon_M2_mpyd_rnd_ll_s1 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_ll_s1">; + +def int_hexagon_M2_mpyi : +Hexagon_custom_i32_i32i32_Intrinsic; + +def int_hexagon_M2_mpysmi : +Hexagon_custom_i32_i32i32_Intrinsic<[IntrNoMem, ImmArg>]>; + +def int_hexagon_M2_mpysu_up : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysu_up">; + +def int_hexagon_M2_mpyu_acc_hh_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hh_s0">; + +def int_hexagon_M2_mpyu_acc_hh_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hh_s1">; + +def int_hexagon_M2_mpyu_acc_hl_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hl_s0">; + +def int_hexagon_M2_mpyu_acc_hl_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hl_s1">; + +def int_hexagon_M2_mpyu_acc_lh_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_lh_s0">; + +def int_hexagon_M2_mpyu_acc_lh_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_lh_s1">; + +def int_hexagon_M2_mpyu_acc_ll_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_ll_s0">; + +def int_hexagon_M2_mpyu_acc_ll_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_ll_s1">; + +def int_hexagon_M2_mpyu_hh_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hh_s0">; + +def int_hexagon_M2_mpyu_hh_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hh_s1">; + +def int_hexagon_M2_mpyu_hl_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hl_s0">; + +def int_hexagon_M2_mpyu_hl_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hl_s1">; + +def int_hexagon_M2_mpyu_lh_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_lh_s0">; + +def int_hexagon_M2_mpyu_lh_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_lh_s1">; + +def int_hexagon_M2_mpyu_ll_s0 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_ll_s0">; + +def int_hexagon_M2_mpyu_ll_s1 : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_ll_s1">; + +def int_hexagon_M2_mpyu_nac_hh_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hh_s0">; + +def int_hexagon_M2_mpyu_nac_hh_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hh_s1">; + +def int_hexagon_M2_mpyu_nac_hl_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hl_s0">; + +def int_hexagon_M2_mpyu_nac_hl_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hl_s1">; + +def int_hexagon_M2_mpyu_nac_lh_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_lh_s0">; + +def int_hexagon_M2_mpyu_nac_lh_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_lh_s1">; + +def int_hexagon_M2_mpyu_nac_ll_s0 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_ll_s0">; + +def int_hexagon_M2_mpyu_nac_ll_s1 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_ll_s1">; + +def int_hexagon_M2_mpyu_up : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_up">; + +def int_hexagon_M2_mpyud_acc_hh_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hh_s0">; + +def int_hexagon_M2_mpyud_acc_hh_s1 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hh_s1">; + +def int_hexagon_M2_mpyud_acc_hl_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hl_s0">; + +def int_hexagon_M2_mpyud_acc_hl_s1 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hl_s1">; + +def int_hexagon_M2_mpyud_acc_lh_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_lh_s0">; + +def int_hexagon_M2_mpyud_acc_lh_s1 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_lh_s1">; + +def int_hexagon_M2_mpyud_acc_ll_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_ll_s0">; + +def int_hexagon_M2_mpyud_acc_ll_s1 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_ll_s1">; + +def int_hexagon_M2_mpyud_hh_s0 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hh_s0">; + +def int_hexagon_M2_mpyud_hh_s1 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hh_s1">; + +def int_hexagon_M2_mpyud_hl_s0 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hl_s0">; + +def int_hexagon_M2_mpyud_hl_s1 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hl_s1">; + +def int_hexagon_M2_mpyud_lh_s0 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_lh_s0">; + +def int_hexagon_M2_mpyud_lh_s1 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_lh_s1">; + +def int_hexagon_M2_mpyud_ll_s0 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_ll_s0">; + +def int_hexagon_M2_mpyud_ll_s1 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_ll_s1">; + +def int_hexagon_M2_mpyud_nac_hh_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hh_s0">; + +def int_hexagon_M2_mpyud_nac_hh_s1 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hh_s1">; + +def int_hexagon_M2_mpyud_nac_hl_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hl_s0">; + +def int_hexagon_M2_mpyud_nac_hl_s1 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hl_s1">; + +def int_hexagon_M2_mpyud_nac_lh_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_lh_s0">; + +def int_hexagon_M2_mpyud_nac_lh_s1 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_lh_s1">; + +def int_hexagon_M2_mpyud_nac_ll_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_ll_s0">; + +def int_hexagon_M2_mpyud_nac_ll_s1 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_ll_s1">; + +def int_hexagon_M2_mpyui : +Hexagon_custom_i32_i32i32_Intrinsic; + +def int_hexagon_M2_nacci : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_nacci">; + +def int_hexagon_M2_naccii : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_naccii", [IntrNoMem, ImmArg>]>; + +def int_hexagon_M2_subacc : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_subacc">; + +def int_hexagon_M2_vabsdiffh : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vabsdiffh">; + +def int_hexagon_M2_vabsdiffw : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vabsdiffw">; + +def int_hexagon_M2_vcmac_s0_sat_i : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vcmac_s0_sat_i">; + +def int_hexagon_M2_vcmac_s0_sat_r : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vcmac_s0_sat_r">; def int_hexagon_M2_vcmpy_s0_sat_i : Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s0_sat_i">; @@ -2224,279 +2705,120 @@ Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s1_sat_i">; def int_hexagon_M2_vcmpy_s1_sat_r : Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s1_sat_r">; -def int_hexagon_M2_vcmac_s0_sat_i : -Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vcmac_s0_sat_i">; +def int_hexagon_M2_vdmacs_s0 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vdmacs_s0">; -def int_hexagon_M2_vcmac_s0_sat_r : -Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vcmac_s0_sat_r">; +def int_hexagon_M2_vdmacs_s1 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vdmacs_s1">; -def int_hexagon_S2_vcrotate : -Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_vcrotate">; +def int_hexagon_M2_vdmpyrs_s0 : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vdmpyrs_s0">; -def int_hexagon_S4_vrcrotate_acc : -Hexagon_i64_i64i64i32i32_Intrinsic<"HEXAGON_S4_vrcrotate_acc", [IntrNoMem, ImmArg>]>; +def int_hexagon_M2_vdmpyrs_s1 : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vdmpyrs_s1">; -def int_hexagon_S4_vrcrotate : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S4_vrcrotate", [IntrNoMem, ImmArg>]>; +def int_hexagon_M2_vdmpys_s0 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vdmpys_s0">; -def int_hexagon_S2_vcnegh : -Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_vcnegh">; +def int_hexagon_M2_vdmpys_s1 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vdmpys_s1">; -def int_hexagon_S2_vrcnegh : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_vrcnegh">; +def int_hexagon_M2_vmac2 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2">; -def int_hexagon_M4_pmpyw : -Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M4_pmpyw">; +def int_hexagon_M2_vmac2es : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vmac2es">; -def int_hexagon_M4_vpmpyh : -Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M4_vpmpyh">; +def int_hexagon_M2_vmac2es_s0 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vmac2es_s0">; -def int_hexagon_M4_pmpyw_acc : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M4_pmpyw_acc">; +def int_hexagon_M2_vmac2es_s1 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vmac2es_s1">; -def int_hexagon_M4_vpmpyh_acc : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M4_vpmpyh_acc">; +def int_hexagon_M2_vmac2s_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2s_s0">; -def int_hexagon_A2_add : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_add">; +def int_hexagon_M2_vmac2s_s1 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2s_s1">; -def int_hexagon_A2_sub : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_sub">; +def int_hexagon_M2_vmac2su_s0 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2su_s0">; -def int_hexagon_A2_addsat : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addsat">; +def int_hexagon_M2_vmac2su_s1 : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2su_s1">; -def int_hexagon_A2_subsat : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subsat">; +def int_hexagon_M2_vmpy2es_s0 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vmpy2es_s0">; -def int_hexagon_A2_addi : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addi", [IntrNoMem, ImmArg>]>; +def int_hexagon_M2_vmpy2es_s1 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vmpy2es_s1">; -def int_hexagon_A2_addh_l16_ll : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_ll">; +def int_hexagon_M2_vmpy2s_s0 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s0">; -def int_hexagon_A2_addh_l16_hl : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_hl">; +def int_hexagon_M2_vmpy2s_s0pack : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s0pack">; -def int_hexagon_A2_addh_l16_sat_ll : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_sat_ll">; +def int_hexagon_M2_vmpy2s_s1 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s1">; -def int_hexagon_A2_addh_l16_sat_hl : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_sat_hl">; +def int_hexagon_M2_vmpy2s_s1pack : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s1pack">; -def int_hexagon_A2_subh_l16_ll : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_ll">; +def int_hexagon_M2_vmpy2su_s0 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2su_s0">; -def int_hexagon_A2_subh_l16_hl : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_hl">; +def int_hexagon_M2_vmpy2su_s1 : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2su_s1">; -def int_hexagon_A2_subh_l16_sat_ll : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_sat_ll">; +def int_hexagon_M2_vraddh : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vraddh">; -def int_hexagon_A2_subh_l16_sat_hl : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_sat_hl">; +def int_hexagon_M2_vradduh : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vradduh">; -def int_hexagon_A2_addh_h16_ll : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_ll">; +def int_hexagon_M2_vrcmaci_s0 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmaci_s0">; -def int_hexagon_A2_addh_h16_lh : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_lh">; +def int_hexagon_M2_vrcmaci_s0c : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmaci_s0c">; -def int_hexagon_A2_addh_h16_hl : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_hl">; +def int_hexagon_M2_vrcmacr_s0 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmacr_s0">; -def int_hexagon_A2_addh_h16_hh : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_hh">; +def int_hexagon_M2_vrcmacr_s0c : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmacr_s0c">; -def int_hexagon_A2_addh_h16_sat_ll : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_ll">; +def int_hexagon_M2_vrcmpyi_s0 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyi_s0">; -def int_hexagon_A2_addh_h16_sat_lh : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_lh">; +def int_hexagon_M2_vrcmpyi_s0c : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyi_s0c">; -def int_hexagon_A2_addh_h16_sat_hl : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_hl">; +def int_hexagon_M2_vrcmpyr_s0 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyr_s0">; -def int_hexagon_A2_addh_h16_sat_hh : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_hh">; +def int_hexagon_M2_vrcmpyr_s0c : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyr_s0c">; -def int_hexagon_A2_subh_h16_ll : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_ll">; +def int_hexagon_M2_vrcmpys_acc_s1 : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_M2_vrcmpys_acc_s1">; -def int_hexagon_A2_subh_h16_lh : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_lh">; +def int_hexagon_M2_vrcmpys_s1 : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_M2_vrcmpys_s1">; -def int_hexagon_A2_subh_h16_hl : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_hl">; +def int_hexagon_M2_vrcmpys_s1rp : +Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M2_vrcmpys_s1rp">; -def int_hexagon_A2_subh_h16_hh : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_hh">; +def int_hexagon_M2_vrmac_s0 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrmac_s0">; -def int_hexagon_A2_subh_h16_sat_ll : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_ll">; - -def int_hexagon_A2_subh_h16_sat_lh : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_lh">; - -def int_hexagon_A2_subh_h16_sat_hl : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_hl">; - -def int_hexagon_A2_subh_h16_sat_hh : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_hh">; - -def int_hexagon_A2_aslh : -Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_aslh">; - -def int_hexagon_A2_asrh : -Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_asrh">; - -def int_hexagon_A2_addp : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_addp">; - -def int_hexagon_A2_addpsat : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_addpsat">; - -def int_hexagon_A2_addsp : -Hexagon_i64_i32i64_Intrinsic<"HEXAGON_A2_addsp">; - -def int_hexagon_A2_subp : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_subp">; - -def int_hexagon_A2_neg : -Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_neg">; - -def int_hexagon_A2_negsat : -Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_negsat">; - -def int_hexagon_A2_abs : -Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_abs">; - -def int_hexagon_A2_abssat : -Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_abssat">; - -def int_hexagon_A2_vconj : -Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vconj">; - -def int_hexagon_A2_negp : -Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_negp">; - -def int_hexagon_A2_absp : -Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_absp">; - -def int_hexagon_A2_max : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_max">; - -def int_hexagon_A2_maxu : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_maxu">; - -def int_hexagon_A2_min : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_min">; - -def int_hexagon_A2_minu : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_minu">; - -def int_hexagon_A2_maxp : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_maxp">; - -def int_hexagon_A2_maxup : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_maxup">; - -def int_hexagon_A2_minp : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_minp">; - -def int_hexagon_A2_minup : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_minup">; - -def int_hexagon_A2_tfr : -Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_tfr">; - -def int_hexagon_A2_tfrsi : -Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_tfrsi", [IntrNoMem, ImmArg>]>; - -def int_hexagon_A2_tfrp : -Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_tfrp">; - -def int_hexagon_A2_tfrpi : -Hexagon_i64_i32_Intrinsic<"HEXAGON_A2_tfrpi", [IntrNoMem, ImmArg>]>; - -def int_hexagon_A2_zxtb : -Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_zxtb">; - -def int_hexagon_A2_sxtb : -Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_sxtb">; - -def int_hexagon_A2_zxth : -Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_zxth">; - -def int_hexagon_A2_sxth : -Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_sxth">; - -def int_hexagon_A2_combinew : -Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A2_combinew">; - -def int_hexagon_A4_combineri : -Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_combineri", [IntrNoMem, ImmArg>]>; - -def int_hexagon_A4_combineir : -Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_combineir", [IntrNoMem, ImmArg>]>; - -def int_hexagon_A2_combineii : -Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A2_combineii", [IntrNoMem, ImmArg>, ImmArg>]>; - -def int_hexagon_A2_combine_hh : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_hh">; - -def int_hexagon_A2_combine_hl : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_hl">; - -def int_hexagon_A2_combine_lh : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_lh">; - -def int_hexagon_A2_combine_ll : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_ll">; - -def int_hexagon_A2_tfril : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_tfril", [IntrNoMem, ImmArg>]>; - -def int_hexagon_A2_tfrih : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_tfrih", [IntrNoMem, ImmArg>]>; - -def int_hexagon_A2_and : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_and">; - -def int_hexagon_A2_or : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_or">; - -def int_hexagon_A2_xor : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_xor">; - -def int_hexagon_A2_not : -Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_not">; +def int_hexagon_M2_vrmpy_s0 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrmpy_s0">; def int_hexagon_M2_xor_xacc : Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_xor_xacc">; -def int_hexagon_M4_xor_xacc : -Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_xor_xacc">; - -def int_hexagon_A4_andn : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_andn">; - -def int_hexagon_A4_orn : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_orn">; - -def int_hexagon_A4_andnp : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A4_andnp">; - -def int_hexagon_A4_ornp : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A4_ornp">; - -def int_hexagon_S4_addaddi : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addaddi", [IntrNoMem, ImmArg>]>; - -def int_hexagon_S4_subaddi : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subaddi", [IntrNoMem, ImmArg>]>; - def int_hexagon_M4_and_and : Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_and">; @@ -2509,6 +2831,39 @@ Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_or">; def int_hexagon_M4_and_xor : Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_xor">; +def int_hexagon_M4_cmpyi_wh : +Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyi_wh">; + +def int_hexagon_M4_cmpyi_whc : +Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyi_whc">; + +def int_hexagon_M4_cmpyr_wh : +Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyr_wh">; + +def int_hexagon_M4_cmpyr_whc : +Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyr_whc">; + +def int_hexagon_M4_mac_up_s1_sat : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mac_up_s1_sat">; + +def int_hexagon_M4_mpyri_addi : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addi", [IntrNoMem, ImmArg>, ImmArg>]>; + +def int_hexagon_M4_mpyri_addr : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addr", [IntrNoMem, ImmArg>]>; + +def int_hexagon_M4_mpyri_addr_u2 : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addr_u2", [IntrNoMem, ImmArg>]>; + +def int_hexagon_M4_mpyrr_addi : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyrr_addi", [IntrNoMem, ImmArg>]>; + +def int_hexagon_M4_mpyrr_addr : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyrr_addr">; + +def int_hexagon_M4_nac_up_s1_sat : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_nac_up_s1_sat">; + def int_hexagon_M4_or_and : Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_and">; @@ -2521,740 +2876,188 @@ Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_or">; def int_hexagon_M4_or_xor : Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_xor">; -def int_hexagon_S4_or_andix : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_andix", [IntrNoMem, ImmArg>]>; +def int_hexagon_M4_pmpyw : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M4_pmpyw">; -def int_hexagon_S4_or_andi : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_andi", [IntrNoMem, ImmArg>]>; +def int_hexagon_M4_pmpyw_acc : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M4_pmpyw_acc">; -def int_hexagon_S4_or_ori : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_ori", [IntrNoMem, ImmArg>]>; +def int_hexagon_M4_vpmpyh : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M4_vpmpyh">; + +def int_hexagon_M4_vpmpyh_acc : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M4_vpmpyh_acc">; + +def int_hexagon_M4_vrmpyeh_acc_s0 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_acc_s0">; + +def int_hexagon_M4_vrmpyeh_acc_s1 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_acc_s1">; + +def int_hexagon_M4_vrmpyeh_s0 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_s0">; + +def int_hexagon_M4_vrmpyeh_s1 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_s1">; + +def int_hexagon_M4_vrmpyoh_acc_s0 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_acc_s0">; + +def int_hexagon_M4_vrmpyoh_acc_s1 : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_acc_s1">; + +def int_hexagon_M4_vrmpyoh_s0 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_s0">; + +def int_hexagon_M4_vrmpyoh_s1 : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_s1">; def int_hexagon_M4_xor_and : Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_xor_and">; -def int_hexagon_M4_xor_or : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_xor_or">; - def int_hexagon_M4_xor_andn : Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_xor_andn">; -def int_hexagon_A2_subri : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subri", [IntrNoMem, ImmArg>]>; +def int_hexagon_M4_xor_or : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_xor_or">; -def int_hexagon_A2_andir : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_andir", [IntrNoMem, ImmArg>]>; +def int_hexagon_M4_xor_xacc : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_xor_xacc">; -def int_hexagon_A2_orir : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_orir", [IntrNoMem, ImmArg>]>; +def int_hexagon_M5_vdmacbsu : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M5_vdmacbsu">; -def int_hexagon_A2_andp : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_andp">; +def int_hexagon_M5_vdmpybsu : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M5_vdmpybsu">; -def int_hexagon_A2_orp : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_orp">; +def int_hexagon_M5_vmacbsu : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M5_vmacbsu">; -def int_hexagon_A2_xorp : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_xorp">; +def int_hexagon_M5_vmacbuu : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M5_vmacbuu">; -def int_hexagon_A2_notp : -Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_notp">; +def int_hexagon_M5_vmpybsu : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M5_vmpybsu">; -def int_hexagon_A2_sxtw : -Hexagon_i64_i32_Intrinsic<"HEXAGON_A2_sxtw">; +def int_hexagon_M5_vmpybuu : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M5_vmpybuu">; -def int_hexagon_A2_sat : -Hexagon_i32_i64_Intrinsic<"HEXAGON_A2_sat">; +def int_hexagon_M5_vrmacbsu : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M5_vrmacbsu">; -def int_hexagon_A2_roundsat : -Hexagon_i32_i64_Intrinsic<"HEXAGON_A2_roundsat">; +def int_hexagon_M5_vrmacbuu : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M5_vrmacbuu">; -def int_hexagon_A2_sath : -Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_sath">; +def int_hexagon_M5_vrmpybsu : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M5_vrmpybsu">; -def int_hexagon_A2_satuh : -Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_satuh">; +def int_hexagon_M5_vrmpybuu : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M5_vrmpybuu">; -def int_hexagon_A2_satub : -Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_satub">; - -def int_hexagon_A2_satb : -Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_satb">; - -def int_hexagon_A2_vaddub : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddub">; - -def int_hexagon_A2_vaddb_map : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddb_map">; - -def int_hexagon_A2_vaddubs : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddubs">; - -def int_hexagon_A2_vaddh : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddh">; - -def int_hexagon_A2_vaddhs : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddhs">; - -def int_hexagon_A2_vadduhs : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vadduhs">; - -def int_hexagon_A5_vaddhubs : -Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A5_vaddhubs">; - -def int_hexagon_A2_vaddw : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddw">; - -def int_hexagon_A2_vaddws : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddws">; - -def int_hexagon_S4_vxaddsubw : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxaddsubw">; - -def int_hexagon_S4_vxsubaddw : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxsubaddw">; - -def int_hexagon_S4_vxaddsubh : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxaddsubh">; - -def int_hexagon_S4_vxsubaddh : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxsubaddh">; - -def int_hexagon_S4_vxaddsubhr : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxaddsubhr">; - -def int_hexagon_S4_vxsubaddhr : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxsubaddhr">; - -def int_hexagon_A2_svavgh : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svavgh">; - -def int_hexagon_A2_svavghs : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svavghs">; - -def int_hexagon_A2_svnavgh : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svnavgh">; - -def int_hexagon_A2_svaddh : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svaddh">; - -def int_hexagon_A2_svaddhs : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svaddhs">; - -def int_hexagon_A2_svadduhs : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svadduhs">; - -def int_hexagon_A2_svsubh : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svsubh">; - -def int_hexagon_A2_svsubhs : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svsubhs">; - -def int_hexagon_A2_svsubuhs : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svsubuhs">; - -def int_hexagon_A2_vraddub : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vraddub">; - -def int_hexagon_A2_vraddub_acc : -Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_A2_vraddub_acc">; - -def int_hexagon_M2_vraddh : -Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vraddh">; - -def int_hexagon_M2_vradduh : -Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vradduh">; - -def int_hexagon_A2_vsubub : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubub">; - -def int_hexagon_A2_vsubb_map : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubb_map">; - -def int_hexagon_A2_vsububs : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsububs">; - -def int_hexagon_A2_vsubh : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubh">; - -def int_hexagon_A2_vsubhs : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubhs">; - -def int_hexagon_A2_vsubuhs : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubuhs">; - -def int_hexagon_A2_vsubw : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubw">; - -def int_hexagon_A2_vsubws : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubws">; - -def int_hexagon_A2_vabsh : -Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabsh">; - -def int_hexagon_A2_vabshsat : -Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabshsat">; - -def int_hexagon_A2_vabsw : -Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabsw">; - -def int_hexagon_A2_vabswsat : -Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabswsat">; - -def int_hexagon_M2_vabsdiffw : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vabsdiffw">; - -def int_hexagon_M2_vabsdiffh : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vabsdiffh">; - -def int_hexagon_A2_vrsadub : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vrsadub">; - -def int_hexagon_A2_vrsadub_acc : -Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_A2_vrsadub_acc">; - -def int_hexagon_A2_vavgub : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgub">; - -def int_hexagon_A2_vavguh : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguh">; - -def int_hexagon_A2_vavgh : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgh">; - -def int_hexagon_A2_vnavgh : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgh">; - -def int_hexagon_A2_vavgw : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgw">; - -def int_hexagon_A2_vnavgw : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgw">; - -def int_hexagon_A2_vavgwr : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgwr">; - -def int_hexagon_A2_vnavgwr : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgwr">; - -def int_hexagon_A2_vavgwcr : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgwcr">; - -def int_hexagon_A2_vnavgwcr : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgwcr">; - -def int_hexagon_A2_vavghcr : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavghcr">; - -def int_hexagon_A2_vnavghcr : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavghcr">; - -def int_hexagon_A2_vavguw : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguw">; - -def int_hexagon_A2_vavguwr : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguwr">; - -def int_hexagon_A2_vavgubr : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgubr">; - -def int_hexagon_A2_vavguhr : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguhr">; - -def int_hexagon_A2_vavghr : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavghr">; - -def int_hexagon_A2_vnavghr : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavghr">; - -def int_hexagon_A4_round_ri : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_ri", [IntrNoMem, ImmArg>]>; - -def int_hexagon_A4_round_rr : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_rr">; - -def int_hexagon_A4_round_ri_sat : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_ri_sat", [IntrNoMem, ImmArg>]>; - -def int_hexagon_A4_round_rr_sat : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_rr_sat">; - -def int_hexagon_A4_cround_ri : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cround_ri", [IntrNoMem, ImmArg>]>; - -def int_hexagon_A4_cround_rr : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cround_rr">; - -def int_hexagon_A4_vrminh : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminh">; - -def int_hexagon_A4_vrmaxh : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxh">; - -def int_hexagon_A4_vrminuh : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminuh">; - -def int_hexagon_A4_vrmaxuh : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxuh">; - -def int_hexagon_A4_vrminw : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminw">; - -def int_hexagon_A4_vrmaxw : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxw">; - -def int_hexagon_A4_vrminuw : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminuw">; - -def int_hexagon_A4_vrmaxuw : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxuw">; - -def int_hexagon_A2_vminb : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminb">; - -def int_hexagon_A2_vmaxb : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxb">; - -def int_hexagon_A2_vminub : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminub">; - -def int_hexagon_A2_vmaxub : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxub">; - -def int_hexagon_A2_vminh : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminh">; - -def int_hexagon_A2_vmaxh : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxh">; - -def int_hexagon_A2_vminuh : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminuh">; - -def int_hexagon_A2_vmaxuh : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxuh">; - -def int_hexagon_A2_vminw : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminw">; - -def int_hexagon_A2_vmaxw : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxw">; - -def int_hexagon_A2_vminuw : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminuw">; - -def int_hexagon_A2_vmaxuw : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxuw">; - -def int_hexagon_A4_modwrapu : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_modwrapu">; - -def int_hexagon_F2_sfadd : -Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfadd", [IntrNoMem, Throws]>; - -def int_hexagon_F2_sfsub : -Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfsub", [IntrNoMem, Throws]>; - -def int_hexagon_F2_sfmpy : -Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfmpy", [IntrNoMem, Throws]>; - -def int_hexagon_F2_sffma : -Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffma", [IntrNoMem, Throws]>; - -def int_hexagon_F2_sffma_sc : -Hexagon_float_floatfloatfloati32_Intrinsic<"HEXAGON_F2_sffma_sc", [IntrNoMem, Throws]>; - -def int_hexagon_F2_sffms : -Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffms", [IntrNoMem, Throws]>; - -def int_hexagon_F2_sffma_lib : -Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffma_lib", [IntrNoMem, Throws]>; - -def int_hexagon_F2_sffms_lib : -Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffms_lib", [IntrNoMem, Throws]>; - -def int_hexagon_F2_sfcmpeq : -Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpeq", [IntrNoMem, Throws]>; - -def int_hexagon_F2_sfcmpgt : -Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpgt", [IntrNoMem, Throws]>; - -def int_hexagon_F2_sfcmpge : -Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpge", [IntrNoMem, Throws]>; - -def int_hexagon_F2_sfcmpuo : -Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpuo", [IntrNoMem, Throws]>; - -def int_hexagon_F2_sfmax : -Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfmax", [IntrNoMem, Throws]>; - -def int_hexagon_F2_sfmin : -Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfmin", [IntrNoMem, Throws]>; - -def int_hexagon_F2_sfclass : -Hexagon_i32_floati32_Intrinsic<"HEXAGON_F2_sfclass", [IntrNoMem, Throws, ImmArg>]>; - -def int_hexagon_F2_sfimm_p : -Hexagon_float_i32_Intrinsic<"HEXAGON_F2_sfimm_p", [IntrNoMem, Throws, ImmArg>]>; - -def int_hexagon_F2_sfimm_n : -Hexagon_float_i32_Intrinsic<"HEXAGON_F2_sfimm_n", [IntrNoMem, Throws, ImmArg>]>; - -def int_hexagon_F2_sffixupn : -Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sffixupn", [IntrNoMem, Throws]>; - -def int_hexagon_F2_sffixupd : -Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sffixupd", [IntrNoMem, Throws]>; - -def int_hexagon_F2_sffixupr : -Hexagon_float_float_Intrinsic<"HEXAGON_F2_sffixupr", [IntrNoMem, Throws]>; - -def int_hexagon_F2_dfcmpeq : -Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpeq", [IntrNoMem, Throws]>; - -def int_hexagon_F2_dfcmpgt : -Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpgt", [IntrNoMem, Throws]>; - -def int_hexagon_F2_dfcmpge : -Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpge", [IntrNoMem, Throws]>; - -def int_hexagon_F2_dfcmpuo : -Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpuo", [IntrNoMem, Throws]>; - -def int_hexagon_F2_dfclass : -Hexagon_i32_doublei32_Intrinsic<"HEXAGON_F2_dfclass", [IntrNoMem, Throws, ImmArg>]>; - -def int_hexagon_F2_dfimm_p : -Hexagon_double_i32_Intrinsic<"HEXAGON_F2_dfimm_p", [IntrNoMem, Throws, ImmArg>]>; - -def int_hexagon_F2_dfimm_n : -Hexagon_double_i32_Intrinsic<"HEXAGON_F2_dfimm_n", [IntrNoMem, Throws, ImmArg>]>; - -def int_hexagon_F2_conv_sf2df : -Hexagon_double_float_Intrinsic<"HEXAGON_F2_conv_sf2df">; - -def int_hexagon_F2_conv_df2sf : -Hexagon_float_double_Intrinsic<"HEXAGON_F2_conv_df2sf">; - -def int_hexagon_F2_conv_uw2sf : -Hexagon_float_i32_Intrinsic<"HEXAGON_F2_conv_uw2sf">; - -def int_hexagon_F2_conv_uw2df : -Hexagon_double_i32_Intrinsic<"HEXAGON_F2_conv_uw2df">; - -def int_hexagon_F2_conv_w2sf : -Hexagon_float_i32_Intrinsic<"HEXAGON_F2_conv_w2sf">; - -def int_hexagon_F2_conv_w2df : -Hexagon_double_i32_Intrinsic<"HEXAGON_F2_conv_w2df">; - -def int_hexagon_F2_conv_ud2sf : -Hexagon_float_i64_Intrinsic<"HEXAGON_F2_conv_ud2sf">; - -def int_hexagon_F2_conv_ud2df : -Hexagon_double_i64_Intrinsic<"HEXAGON_F2_conv_ud2df">; - -def int_hexagon_F2_conv_d2sf : -Hexagon_float_i64_Intrinsic<"HEXAGON_F2_conv_d2sf">; - -def int_hexagon_F2_conv_d2df : -Hexagon_double_i64_Intrinsic<"HEXAGON_F2_conv_d2df">; - -def int_hexagon_F2_conv_sf2uw : -Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2uw">; - -def int_hexagon_F2_conv_sf2w : -Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2w">; - -def int_hexagon_F2_conv_sf2ud : -Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2ud">; - -def int_hexagon_F2_conv_sf2d : -Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2d">; - -def int_hexagon_F2_conv_df2uw : -Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2uw">; - -def int_hexagon_F2_conv_df2w : -Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2w">; - -def int_hexagon_F2_conv_df2ud : -Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2ud">; - -def int_hexagon_F2_conv_df2d : -Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2d">; - -def int_hexagon_F2_conv_sf2uw_chop : -Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2uw_chop">; - -def int_hexagon_F2_conv_sf2w_chop : -Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2w_chop">; - -def int_hexagon_F2_conv_sf2ud_chop : -Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2ud_chop">; - -def int_hexagon_F2_conv_sf2d_chop : -Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2d_chop">; - -def int_hexagon_F2_conv_df2uw_chop : -Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2uw_chop">; - -def int_hexagon_F2_conv_df2w_chop : -Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2w_chop">; - -def int_hexagon_F2_conv_df2ud_chop : -Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2ud_chop">; - -def int_hexagon_F2_conv_df2d_chop : -Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2d_chop">; - -def int_hexagon_S2_asr_r_r : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_r_r">; - -def int_hexagon_S2_asl_r_r : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_r_r">; - -def int_hexagon_S2_lsr_r_r : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r">; - -def int_hexagon_S2_lsl_r_r : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r">; - -def int_hexagon_S2_asr_r_p : -Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_r_p">; - -def int_hexagon_S2_asl_r_p : -Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_r_p">; - -def int_hexagon_S2_lsr_r_p : -Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p">; - -def int_hexagon_S2_lsl_r_p : -Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p">; - -def int_hexagon_S2_asr_r_r_acc : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_acc">; - -def int_hexagon_S2_asl_r_r_acc : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_acc">; - -def int_hexagon_S2_lsr_r_r_acc : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_acc">; - -def int_hexagon_S2_lsl_r_r_acc : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_acc">; - -def int_hexagon_S2_asr_r_p_acc : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_acc">; - -def int_hexagon_S2_asl_r_p_acc : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_acc">; - -def int_hexagon_S2_lsr_r_p_acc : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_acc">; - -def int_hexagon_S2_lsl_r_p_acc : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_acc">; - -def int_hexagon_S2_asr_r_r_nac : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_nac">; - -def int_hexagon_S2_asl_r_r_nac : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_nac">; - -def int_hexagon_S2_lsr_r_r_nac : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_nac">; - -def int_hexagon_S2_lsl_r_r_nac : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_nac">; - -def int_hexagon_S2_asr_r_p_nac : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_nac">; - -def int_hexagon_S2_asl_r_p_nac : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_nac">; - -def int_hexagon_S2_lsr_r_p_nac : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_nac">; - -def int_hexagon_S2_lsl_r_p_nac : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_nac">; - -def int_hexagon_S2_asr_r_r_and : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_and">; - -def int_hexagon_S2_asl_r_r_and : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_and">; - -def int_hexagon_S2_lsr_r_r_and : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_and">; - -def int_hexagon_S2_lsl_r_r_and : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_and">; - -def int_hexagon_S2_asr_r_r_or : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_or">; - -def int_hexagon_S2_asl_r_r_or : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_or">; - -def int_hexagon_S2_lsr_r_r_or : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_or">; - -def int_hexagon_S2_lsl_r_r_or : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_or">; - -def int_hexagon_S2_asr_r_p_and : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_and">; - -def int_hexagon_S2_asl_r_p_and : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_and">; - -def int_hexagon_S2_lsr_r_p_and : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_and">; - -def int_hexagon_S2_lsl_r_p_and : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_and">; - -def int_hexagon_S2_asr_r_p_or : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_or">; - -def int_hexagon_S2_asl_r_p_or : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_or">; - -def int_hexagon_S2_lsr_r_p_or : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_or">; - -def int_hexagon_S2_lsl_r_p_or : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_or">; - -def int_hexagon_S2_asr_r_p_xor : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_xor">; - -def int_hexagon_S2_asl_r_p_xor : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_xor">; - -def int_hexagon_S2_lsr_r_p_xor : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_xor">; - -def int_hexagon_S2_lsl_r_p_xor : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_xor">; - -def int_hexagon_S2_asr_r_r_sat : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_sat">; - -def int_hexagon_S2_asl_r_r_sat : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_sat">; - -def int_hexagon_S2_asr_i_r : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r", [IntrNoMem, ImmArg>]>; - -def int_hexagon_S2_lsr_i_r : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r", [IntrNoMem, ImmArg>]>; - -def int_hexagon_S2_asl_i_r : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_i_r", [IntrNoMem, ImmArg>]>; - -def int_hexagon_S2_asr_i_p : -Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p", [IntrNoMem, ImmArg>]>; - -def int_hexagon_S2_lsr_i_p : -Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p", [IntrNoMem, ImmArg>]>; +def int_hexagon_S2_addasl_rrri : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_addasl_rrri", [IntrNoMem, ImmArg>]>; def int_hexagon_S2_asl_i_p : -Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_p", [IntrNoMem, ImmArg>]>; - -def int_hexagon_S2_asr_i_r_acc : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_acc", [IntrNoMem, ImmArg>]>; - -def int_hexagon_S2_lsr_i_r_acc : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_acc", [IntrNoMem, ImmArg>]>; - -def int_hexagon_S2_asl_i_r_acc : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_acc", [IntrNoMem, ImmArg>]>; - -def int_hexagon_S2_asr_i_p_acc : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_acc", [IntrNoMem, ImmArg>]>; - -def int_hexagon_S2_lsr_i_p_acc : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_acc", [IntrNoMem, ImmArg>]>; +Hexagon_custom_i64_i64i32_Intrinsic<[IntrNoMem, ImmArg>]>; def int_hexagon_S2_asl_i_p_acc : Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_acc", [IntrNoMem, ImmArg>]>; -def int_hexagon_S2_asr_i_r_nac : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_nac", [IntrNoMem, ImmArg>]>; - -def int_hexagon_S2_lsr_i_r_nac : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_nac", [IntrNoMem, ImmArg>]>; - -def int_hexagon_S2_asl_i_r_nac : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_nac", [IntrNoMem, ImmArg>]>; - -def int_hexagon_S2_asr_i_p_nac : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_nac", [IntrNoMem, ImmArg>]>; - -def int_hexagon_S2_lsr_i_p_nac : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_nac", [IntrNoMem, ImmArg>]>; +def int_hexagon_S2_asl_i_p_and : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_and", [IntrNoMem, ImmArg>]>; def int_hexagon_S2_asl_i_p_nac : Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_nac", [IntrNoMem, ImmArg>]>; -def int_hexagon_S2_lsr_i_r_xacc : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_xacc", [IntrNoMem, ImmArg>]>; - -def int_hexagon_S2_asl_i_r_xacc : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_xacc", [IntrNoMem, ImmArg>]>; - -def int_hexagon_S2_lsr_i_p_xacc : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_xacc", [IntrNoMem, ImmArg>]>; +def int_hexagon_S2_asl_i_p_or : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_or", [IntrNoMem, ImmArg>]>; def int_hexagon_S2_asl_i_p_xacc : Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_xacc", [IntrNoMem, ImmArg>]>; -def int_hexagon_S2_asr_i_r_and : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_and", [IntrNoMem, ImmArg>]>; +def int_hexagon_S2_asl_i_r : +Hexagon_custom_i32_i32i32_Intrinsic<[IntrNoMem, ImmArg>]>; -def int_hexagon_S2_lsr_i_r_and : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_and", [IntrNoMem, ImmArg>]>; +def int_hexagon_S2_asl_i_r_acc : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_acc", [IntrNoMem, ImmArg>]>; def int_hexagon_S2_asl_i_r_and : Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_and", [IntrNoMem, ImmArg>]>; -def int_hexagon_S2_asr_i_r_or : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_or", [IntrNoMem, ImmArg>]>; - -def int_hexagon_S2_lsr_i_r_or : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_or", [IntrNoMem, ImmArg>]>; +def int_hexagon_S2_asl_i_r_nac : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_nac", [IntrNoMem, ImmArg>]>; def int_hexagon_S2_asl_i_r_or : Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_or", [IntrNoMem, ImmArg>]>; -def int_hexagon_S2_asr_i_p_and : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_and", [IntrNoMem, ImmArg>]>; - -def int_hexagon_S2_lsr_i_p_and : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_and", [IntrNoMem, ImmArg>]>; - -def int_hexagon_S2_asl_i_p_and : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_and", [IntrNoMem, ImmArg>]>; - -def int_hexagon_S2_asr_i_p_or : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_or", [IntrNoMem, ImmArg>]>; - -def int_hexagon_S2_lsr_i_p_or : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_or", [IntrNoMem, ImmArg>]>; - -def int_hexagon_S2_asl_i_p_or : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_or", [IntrNoMem, ImmArg>]>; - def int_hexagon_S2_asl_i_r_sat : Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_sat", [IntrNoMem, ImmArg>]>; -def int_hexagon_S2_asr_i_r_rnd : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_rnd", [IntrNoMem, ImmArg>]>; +def int_hexagon_S2_asl_i_r_xacc : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_xacc", [IntrNoMem, ImmArg>]>; -def int_hexagon_S2_asr_i_r_rnd_goodsyntax : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_rnd_goodsyntax", [IntrNoMem, ImmArg>]>; +def int_hexagon_S2_asl_i_vh : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_vh", [IntrNoMem, ImmArg>]>; + +def int_hexagon_S2_asl_i_vw : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_vw", [IntrNoMem, ImmArg>]>; + +def int_hexagon_S2_asl_r_p : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_r_p">; + +def int_hexagon_S2_asl_r_p_acc : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_acc">; + +def int_hexagon_S2_asl_r_p_and : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_and">; + +def int_hexagon_S2_asl_r_p_nac : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_nac">; + +def int_hexagon_S2_asl_r_p_or : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_or">; + +def int_hexagon_S2_asl_r_p_xor : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_xor">; + +def int_hexagon_S2_asl_r_r : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_r_r">; + +def int_hexagon_S2_asl_r_r_acc : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_acc">; + +def int_hexagon_S2_asl_r_r_and : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_and">; + +def int_hexagon_S2_asl_r_r_nac : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_nac">; + +def int_hexagon_S2_asl_r_r_or : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_or">; + +def int_hexagon_S2_asl_r_r_sat : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_sat">; + +def int_hexagon_S2_asl_r_vh : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_r_vh">; + +def int_hexagon_S2_asl_r_vw : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_r_vw">; + +def int_hexagon_S2_asr_i_p : +Hexagon_custom_i64_i64i32_Intrinsic<[IntrNoMem, ImmArg>]>; + +def int_hexagon_S2_asr_i_p_acc : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_acc", [IntrNoMem, ImmArg>]>; + +def int_hexagon_S2_asr_i_p_and : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_and", [IntrNoMem, ImmArg>]>; + +def int_hexagon_S2_asr_i_p_nac : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_nac", [IntrNoMem, ImmArg>]>; + +def int_hexagon_S2_asr_i_p_or : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_or", [IntrNoMem, ImmArg>]>; def int_hexagon_S2_asr_i_p_rnd : Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_rnd", [IntrNoMem, ImmArg>]>; @@ -3262,344 +3065,521 @@ Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_rnd", [IntrNoMem, ImmArg>]>; -def int_hexagon_S4_lsli : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_lsli", [IntrNoMem, ImmArg>]>; +def int_hexagon_S2_asr_i_r : +Hexagon_custom_i32_i32i32_Intrinsic<[IntrNoMem, ImmArg>]>; -def int_hexagon_S2_addasl_rrri : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_addasl_rrri", [IntrNoMem, ImmArg>]>; +def int_hexagon_S2_asr_i_r_acc : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_acc", [IntrNoMem, ImmArg>]>; -def int_hexagon_S4_andi_asl_ri : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_andi_asl_ri", [IntrNoMem, ImmArg>, ImmArg>]>; +def int_hexagon_S2_asr_i_r_and : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_and", [IntrNoMem, ImmArg>]>; -def int_hexagon_S4_ori_asl_ri : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_ori_asl_ri", [IntrNoMem, ImmArg>, ImmArg>]>; +def int_hexagon_S2_asr_i_r_nac : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_nac", [IntrNoMem, ImmArg>]>; -def int_hexagon_S4_addi_asl_ri : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addi_asl_ri", [IntrNoMem, ImmArg>, ImmArg>]>; +def int_hexagon_S2_asr_i_r_or : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_or", [IntrNoMem, ImmArg>]>; -def int_hexagon_S4_subi_asl_ri : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subi_asl_ri", [IntrNoMem, ImmArg>, ImmArg>]>; +def int_hexagon_S2_asr_i_r_rnd : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_rnd", [IntrNoMem, ImmArg>]>; -def int_hexagon_S4_andi_lsr_ri : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_andi_lsr_ri", [IntrNoMem, ImmArg>, ImmArg>]>; - -def int_hexagon_S4_ori_lsr_ri : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_ori_lsr_ri", [IntrNoMem, ImmArg>, ImmArg>]>; - -def int_hexagon_S4_addi_lsr_ri : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addi_lsr_ri", [IntrNoMem, ImmArg>, ImmArg>]>; - -def int_hexagon_S4_subi_lsr_ri : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subi_lsr_ri", [IntrNoMem, ImmArg>, ImmArg>]>; - -def int_hexagon_S2_valignib : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_valignib", [IntrNoMem, ImmArg>]>; - -def int_hexagon_S2_valignrb : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_valignrb">; - -def int_hexagon_S2_vspliceib : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_vspliceib", [IntrNoMem, ImmArg>]>; - -def int_hexagon_S2_vsplicerb : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_vsplicerb">; - -def int_hexagon_S2_vsplatrh : -Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vsplatrh">; - -def int_hexagon_S2_vsplatrb : -Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_vsplatrb">; - -def int_hexagon_S2_insert : -Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_insert", [IntrNoMem, ImmArg>, ImmArg>]>; - -def int_hexagon_S2_tableidxb_goodsyntax : -Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxb_goodsyntax", [IntrNoMem, ImmArg>, ImmArg>]>; - -def int_hexagon_S2_tableidxh_goodsyntax : -Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxh_goodsyntax", [IntrNoMem, ImmArg>, ImmArg>]>; - -def int_hexagon_S2_tableidxw_goodsyntax : -Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxw_goodsyntax", [IntrNoMem, ImmArg>, ImmArg>]>; - -def int_hexagon_S2_tableidxd_goodsyntax : -Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxd_goodsyntax", [IntrNoMem, ImmArg>, ImmArg>]>; - -def int_hexagon_A4_bitspliti : -Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_bitspliti", [IntrNoMem, ImmArg>]>; - -def int_hexagon_A4_bitsplit : -Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_bitsplit">; - -def int_hexagon_S4_extract : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_extract", [IntrNoMem, ImmArg>, ImmArg>]>; - -def int_hexagon_S2_extractu : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_extractu", [IntrNoMem, ImmArg>, ImmArg>]>; - -def int_hexagon_S2_insertp : -Hexagon_i64_i64i64i32i32_Intrinsic<"HEXAGON_S2_insertp", [IntrNoMem, ImmArg>, ImmArg>]>; - -def int_hexagon_S4_extractp : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S4_extractp", [IntrNoMem, ImmArg>, ImmArg>]>; - -def int_hexagon_S2_extractup : -Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S2_extractup", [IntrNoMem, ImmArg>, ImmArg>]>; - -def int_hexagon_S2_insert_rp : -Hexagon_i32_i32i32i64_Intrinsic<"HEXAGON_S2_insert_rp">; - -def int_hexagon_S4_extract_rp : -Hexagon_i32_i32i64_Intrinsic<"HEXAGON_S4_extract_rp">; - -def int_hexagon_S2_extractu_rp : -Hexagon_i32_i32i64_Intrinsic<"HEXAGON_S2_extractu_rp">; - -def int_hexagon_S2_insertp_rp : -Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_S2_insertp_rp">; - -def int_hexagon_S4_extractp_rp : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_extractp_rp">; - -def int_hexagon_S2_extractup_rp : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_extractup_rp">; - -def int_hexagon_S2_tstbit_i : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_tstbit_i", [IntrNoMem, ImmArg>]>; - -def int_hexagon_S4_ntstbit_i : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_ntstbit_i", [IntrNoMem, ImmArg>]>; - -def int_hexagon_S2_setbit_i : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_setbit_i", [IntrNoMem, ImmArg>]>; - -def int_hexagon_S2_togglebit_i : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_togglebit_i", [IntrNoMem, ImmArg>]>; - -def int_hexagon_S2_clrbit_i : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_clrbit_i", [IntrNoMem, ImmArg>]>; - -def int_hexagon_S2_tstbit_r : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_tstbit_r">; - -def int_hexagon_S4_ntstbit_r : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_ntstbit_r">; - -def int_hexagon_S2_setbit_r : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_setbit_r">; - -def int_hexagon_S2_togglebit_r : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_togglebit_r">; - -def int_hexagon_S2_clrbit_r : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_clrbit_r">; - -def int_hexagon_S2_asr_i_vh : -Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_vh", [IntrNoMem, ImmArg>]>; - -def int_hexagon_S2_lsr_i_vh : -Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_vh", [IntrNoMem, ImmArg>]>; - -def int_hexagon_S2_asl_i_vh : -Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_vh", [IntrNoMem, ImmArg>]>; - -def int_hexagon_S2_asr_r_vh : -Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_r_vh">; - -def int_hexagon_S5_asrhub_rnd_sat_goodsyntax : -Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S5_asrhub_rnd_sat_goodsyntax", [IntrNoMem, ImmArg>]>; - -def int_hexagon_S5_asrhub_sat : -Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S5_asrhub_sat", [IntrNoMem, ImmArg>]>; - -def int_hexagon_S5_vasrhrnd_goodsyntax : -Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S5_vasrhrnd_goodsyntax", [IntrNoMem, ImmArg>]>; - -def int_hexagon_S2_asl_r_vh : -Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_r_vh">; - -def int_hexagon_S2_lsr_r_vh : -Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_r_vh">; - -def int_hexagon_S2_lsl_r_vh : -Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsl_r_vh">; - -def int_hexagon_S2_asr_i_vw : -Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_vw", [IntrNoMem, ImmArg>]>; +def int_hexagon_S2_asr_i_r_rnd_goodsyntax : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_rnd_goodsyntax", [IntrNoMem, ImmArg>]>; def int_hexagon_S2_asr_i_svw_trun : Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S2_asr_i_svw_trun", [IntrNoMem, ImmArg>]>; +def int_hexagon_S2_asr_i_vh : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_vh", [IntrNoMem, ImmArg>]>; + +def int_hexagon_S2_asr_i_vw : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_vw", [IntrNoMem, ImmArg>]>; + +def int_hexagon_S2_asr_r_p : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_r_p">; + +def int_hexagon_S2_asr_r_p_acc : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_acc">; + +def int_hexagon_S2_asr_r_p_and : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_and">; + +def int_hexagon_S2_asr_r_p_nac : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_nac">; + +def int_hexagon_S2_asr_r_p_or : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_or">; + +def int_hexagon_S2_asr_r_p_xor : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_xor">; + +def int_hexagon_S2_asr_r_r : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_r_r">; + +def int_hexagon_S2_asr_r_r_acc : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_acc">; + +def int_hexagon_S2_asr_r_r_and : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_and">; + +def int_hexagon_S2_asr_r_r_nac : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_nac">; + +def int_hexagon_S2_asr_r_r_or : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_or">; + +def int_hexagon_S2_asr_r_r_sat : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_sat">; + def int_hexagon_S2_asr_r_svw_trun : Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S2_asr_r_svw_trun">; -def int_hexagon_S2_lsr_i_vw : -Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_vw", [IntrNoMem, ImmArg>]>; - -def int_hexagon_S2_asl_i_vw : -Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_vw", [IntrNoMem, ImmArg>]>; +def int_hexagon_S2_asr_r_vh : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_r_vh">; def int_hexagon_S2_asr_r_vw : Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_r_vw">; -def int_hexagon_S2_asl_r_vw : -Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_r_vw">; - -def int_hexagon_S2_lsr_r_vw : -Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_r_vw">; - -def int_hexagon_S2_lsl_r_vw : -Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsl_r_vw">; - -def int_hexagon_S2_vrndpackwh : -Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vrndpackwh">; - -def int_hexagon_S2_vrndpackwhs : -Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vrndpackwhs">; - -def int_hexagon_S2_vsxtbh : -Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vsxtbh">; - -def int_hexagon_S2_vzxtbh : -Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vzxtbh">; - -def int_hexagon_S2_vsathub : -Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsathub">; - -def int_hexagon_S2_svsathub : -Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_svsathub">; - -def int_hexagon_S2_svsathb : -Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_svsathb">; - -def int_hexagon_S2_vsathb : -Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsathb">; - -def int_hexagon_S2_vtrunohb : -Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vtrunohb">; - -def int_hexagon_S2_vtrunewh : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_vtrunewh">; - -def int_hexagon_S2_vtrunowh : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_vtrunowh">; - -def int_hexagon_S2_vtrunehb : -Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vtrunehb">; - -def int_hexagon_S2_vsxthw : -Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vsxthw">; - -def int_hexagon_S2_vzxthw : -Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vzxthw">; - -def int_hexagon_S2_vsatwh : -Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsatwh">; - -def int_hexagon_S2_vsatwuh : -Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsatwuh">; - -def int_hexagon_S2_packhl : -Hexagon_i64_i32i32_Intrinsic<"HEXAGON_S2_packhl">; - -def int_hexagon_A2_swiz : -Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_swiz">; - -def int_hexagon_S2_vsathub_nopack : -Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsathub_nopack">; - -def int_hexagon_S2_vsathb_nopack : -Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsathb_nopack">; - -def int_hexagon_S2_vsatwh_nopack : -Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsatwh_nopack">; - -def int_hexagon_S2_vsatwuh_nopack : -Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsatwuh_nopack">; - -def int_hexagon_S2_shuffob : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffob">; - -def int_hexagon_S2_shuffeb : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffeb">; - -def int_hexagon_S2_shuffoh : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffoh">; - -def int_hexagon_S2_shuffeh : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffeh">; - -def int_hexagon_S5_popcountp : -Hexagon_i32_i64_Intrinsic<"HEXAGON_S5_popcountp">; - -def int_hexagon_S4_parity : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_parity">; - -def int_hexagon_S2_parityp : -Hexagon_i32_i64i64_Intrinsic<"HEXAGON_S2_parityp">; - -def int_hexagon_S2_lfsp : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_lfsp">; - -def int_hexagon_S2_clbnorm : -Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_clbnorm">; - -def int_hexagon_S4_clbaddi : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_clbaddi", [IntrNoMem, ImmArg>]>; - -def int_hexagon_S4_clbpnorm : -Hexagon_i32_i64_Intrinsic<"HEXAGON_S4_clbpnorm">; - -def int_hexagon_S4_clbpaddi : -Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S4_clbpaddi", [IntrNoMem, ImmArg>]>; - -def int_hexagon_S2_clb : -Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_clb">; - -def int_hexagon_S2_cl0 : -Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_cl0">; - -def int_hexagon_S2_cl1 : -Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_cl1">; - -def int_hexagon_S2_clbp : -Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_clbp">; - -def int_hexagon_S2_cl0p : -Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_cl0p">; - -def int_hexagon_S2_cl1p : -Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_cl1p">; - def int_hexagon_S2_brev : Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_brev">; def int_hexagon_S2_brevp : Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_brevp">; +def int_hexagon_S2_cl0 : +Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_cl0">; + +def int_hexagon_S2_cl0p : +Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_cl0p">; + +def int_hexagon_S2_cl1 : +Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_cl1">; + +def int_hexagon_S2_cl1p : +Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_cl1p">; + +def int_hexagon_S2_clb : +Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_clb">; + +def int_hexagon_S2_clbnorm : +Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_clbnorm">; + +def int_hexagon_S2_clbp : +Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_clbp">; + +def int_hexagon_S2_clrbit_i : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_clrbit_i", [IntrNoMem, ImmArg>]>; + +def int_hexagon_S2_clrbit_r : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_clrbit_r">; + def int_hexagon_S2_ct0 : Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_ct0">; -def int_hexagon_S2_ct1 : -Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_ct1">; - def int_hexagon_S2_ct0p : Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_ct0p">; +def int_hexagon_S2_ct1 : +Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_ct1">; + def int_hexagon_S2_ct1p : Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_ct1p">; -def int_hexagon_S2_interleave : -Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_interleave">; - def int_hexagon_S2_deinterleave : Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_deinterleave">; -def int_hexagon_Y2_dcfetch : -Hexagon__ptr_Intrinsic<"HEXAGON_Y2_dcfetch", []>; +def int_hexagon_S2_extractu : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_extractu", [IntrNoMem, ImmArg>, ImmArg>]>; -def int_hexagon_Y2_dczeroa : -Hexagon__ptr_Intrinsic<"HEXAGON_Y2_dczeroa", []>; +def int_hexagon_S2_extractu_rp : +Hexagon_i32_i32i64_Intrinsic<"HEXAGON_S2_extractu_rp">; + +def int_hexagon_S2_extractup : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S2_extractup", [IntrNoMem, ImmArg>, ImmArg>]>; + +def int_hexagon_S2_extractup_rp : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_extractup_rp">; + +def int_hexagon_S2_insert : +Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_insert", [IntrNoMem, ImmArg>, ImmArg>]>; + +def int_hexagon_S2_insert_rp : +Hexagon_i32_i32i32i64_Intrinsic<"HEXAGON_S2_insert_rp">; + +def int_hexagon_S2_insertp : +Hexagon_i64_i64i64i32i32_Intrinsic<"HEXAGON_S2_insertp", [IntrNoMem, ImmArg>, ImmArg>]>; + +def int_hexagon_S2_insertp_rp : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_S2_insertp_rp">; + +def int_hexagon_S2_interleave : +Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_interleave">; + +def int_hexagon_S2_lfsp : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_lfsp">; + +def int_hexagon_S2_lsl_r_p : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p">; + +def int_hexagon_S2_lsl_r_p_acc : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_acc">; + +def int_hexagon_S2_lsl_r_p_and : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_and">; + +def int_hexagon_S2_lsl_r_p_nac : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_nac">; + +def int_hexagon_S2_lsl_r_p_or : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_or">; + +def int_hexagon_S2_lsl_r_p_xor : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_xor">; + +def int_hexagon_S2_lsl_r_r : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r">; + +def int_hexagon_S2_lsl_r_r_acc : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_acc">; + +def int_hexagon_S2_lsl_r_r_and : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_and">; + +def int_hexagon_S2_lsl_r_r_nac : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_nac">; + +def int_hexagon_S2_lsl_r_r_or : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_or">; + +def int_hexagon_S2_lsl_r_vh : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsl_r_vh">; + +def int_hexagon_S2_lsl_r_vw : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsl_r_vw">; + +def int_hexagon_S2_lsr_i_p : +Hexagon_custom_i64_i64i32_Intrinsic<[IntrNoMem, ImmArg>]>; + +def int_hexagon_S2_lsr_i_p_acc : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_acc", [IntrNoMem, ImmArg>]>; + +def int_hexagon_S2_lsr_i_p_and : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_and", [IntrNoMem, ImmArg>]>; + +def int_hexagon_S2_lsr_i_p_nac : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_nac", [IntrNoMem, ImmArg>]>; + +def int_hexagon_S2_lsr_i_p_or : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_or", [IntrNoMem, ImmArg>]>; + +def int_hexagon_S2_lsr_i_p_xacc : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_xacc", [IntrNoMem, ImmArg>]>; + +def int_hexagon_S2_lsr_i_r : +Hexagon_custom_i32_i32i32_Intrinsic<[IntrNoMem, ImmArg>]>; + +def int_hexagon_S2_lsr_i_r_acc : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_acc", [IntrNoMem, ImmArg>]>; + +def int_hexagon_S2_lsr_i_r_and : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_and", [IntrNoMem, ImmArg>]>; + +def int_hexagon_S2_lsr_i_r_nac : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_nac", [IntrNoMem, ImmArg>]>; + +def int_hexagon_S2_lsr_i_r_or : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_or", [IntrNoMem, ImmArg>]>; + +def int_hexagon_S2_lsr_i_r_xacc : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_xacc", [IntrNoMem, ImmArg>]>; + +def int_hexagon_S2_lsr_i_vh : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_vh", [IntrNoMem, ImmArg>]>; + +def int_hexagon_S2_lsr_i_vw : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_vw", [IntrNoMem, ImmArg>]>; + +def int_hexagon_S2_lsr_r_p : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p">; + +def int_hexagon_S2_lsr_r_p_acc : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_acc">; + +def int_hexagon_S2_lsr_r_p_and : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_and">; + +def int_hexagon_S2_lsr_r_p_nac : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_nac">; + +def int_hexagon_S2_lsr_r_p_or : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_or">; + +def int_hexagon_S2_lsr_r_p_xor : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_xor">; + +def int_hexagon_S2_lsr_r_r : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r">; + +def int_hexagon_S2_lsr_r_r_acc : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_acc">; + +def int_hexagon_S2_lsr_r_r_and : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_and">; + +def int_hexagon_S2_lsr_r_r_nac : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_nac">; + +def int_hexagon_S2_lsr_r_r_or : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_or">; + +def int_hexagon_S2_lsr_r_vh : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_r_vh">; + +def int_hexagon_S2_lsr_r_vw : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_r_vw">; + +def int_hexagon_S2_packhl : +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_S2_packhl">; + +def int_hexagon_S2_parityp : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_S2_parityp">; + +def int_hexagon_S2_setbit_i : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_setbit_i", [IntrNoMem, ImmArg>]>; + +def int_hexagon_S2_setbit_r : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_setbit_r">; + +def int_hexagon_S2_shuffeb : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffeb">; + +def int_hexagon_S2_shuffeh : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffeh">; + +def int_hexagon_S2_shuffob : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffob">; + +def int_hexagon_S2_shuffoh : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffoh">; + +def int_hexagon_S2_svsathb : +Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_svsathb">; + +def int_hexagon_S2_svsathub : +Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_svsathub">; + +def int_hexagon_S2_tableidxb_goodsyntax : +Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxb_goodsyntax", [IntrNoMem, ImmArg>, ImmArg>]>; + +def int_hexagon_S2_tableidxd_goodsyntax : +Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxd_goodsyntax", [IntrNoMem, ImmArg>, ImmArg>]>; + +def int_hexagon_S2_tableidxh_goodsyntax : +Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxh_goodsyntax", [IntrNoMem, ImmArg>, ImmArg>]>; + +def int_hexagon_S2_tableidxw_goodsyntax : +Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxw_goodsyntax", [IntrNoMem, ImmArg>, ImmArg>]>; + +def int_hexagon_S2_togglebit_i : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_togglebit_i", [IntrNoMem, ImmArg>]>; + +def int_hexagon_S2_togglebit_r : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_togglebit_r">; + +def int_hexagon_S2_tstbit_i : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_tstbit_i", [IntrNoMem, ImmArg>]>; + +def int_hexagon_S2_tstbit_r : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_tstbit_r">; + +def int_hexagon_S2_valignib : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_valignib", [IntrNoMem, ImmArg>]>; + +def int_hexagon_S2_valignrb : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_valignrb">; + +def int_hexagon_S2_vcnegh : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_vcnegh">; + +def int_hexagon_S2_vcrotate : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_vcrotate">; + +def int_hexagon_S2_vrcnegh : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_vrcnegh">; + +def int_hexagon_S2_vrndpackwh : +Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vrndpackwh">; + +def int_hexagon_S2_vrndpackwhs : +Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vrndpackwhs">; + +def int_hexagon_S2_vsathb : +Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsathb">; + +def int_hexagon_S2_vsathb_nopack : +Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsathb_nopack">; + +def int_hexagon_S2_vsathub : +Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsathub">; + +def int_hexagon_S2_vsathub_nopack : +Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsathub_nopack">; + +def int_hexagon_S2_vsatwh : +Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsatwh">; + +def int_hexagon_S2_vsatwh_nopack : +Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsatwh_nopack">; + +def int_hexagon_S2_vsatwuh : +Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsatwuh">; + +def int_hexagon_S2_vsatwuh_nopack : +Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsatwuh_nopack">; + +def int_hexagon_S2_vsplatrb : +Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_vsplatrb">; + +def int_hexagon_S2_vsplatrh : +Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vsplatrh">; + +def int_hexagon_S2_vspliceib : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_vspliceib", [IntrNoMem, ImmArg>]>; + +def int_hexagon_S2_vsplicerb : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_vsplicerb">; + +def int_hexagon_S2_vsxtbh : +Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vsxtbh">; + +def int_hexagon_S2_vsxthw : +Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vsxthw">; + +def int_hexagon_S2_vtrunehb : +Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vtrunehb">; + +def int_hexagon_S2_vtrunewh : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_vtrunewh">; + +def int_hexagon_S2_vtrunohb : +Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vtrunohb">; + +def int_hexagon_S2_vtrunowh : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_vtrunowh">; + +def int_hexagon_S2_vzxtbh : +Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vzxtbh">; + +def int_hexagon_S2_vzxthw : +Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vzxthw">; + +def int_hexagon_S4_addaddi : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addaddi", [IntrNoMem, ImmArg>]>; + +def int_hexagon_S4_addi_asl_ri : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addi_asl_ri", [IntrNoMem, ImmArg>, ImmArg>]>; + +def int_hexagon_S4_addi_lsr_ri : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addi_lsr_ri", [IntrNoMem, ImmArg>, ImmArg>]>; + +def int_hexagon_S4_andi_asl_ri : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_andi_asl_ri", [IntrNoMem, ImmArg>, ImmArg>]>; + +def int_hexagon_S4_andi_lsr_ri : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_andi_lsr_ri", [IntrNoMem, ImmArg>, ImmArg>]>; + +def int_hexagon_S4_clbaddi : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_clbaddi", [IntrNoMem, ImmArg>]>; + +def int_hexagon_S4_clbpaddi : +Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S4_clbpaddi", [IntrNoMem, ImmArg>]>; + +def int_hexagon_S4_clbpnorm : +Hexagon_i32_i64_Intrinsic<"HEXAGON_S4_clbpnorm">; + +def int_hexagon_S4_extract : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_extract", [IntrNoMem, ImmArg>, ImmArg>]>; + +def int_hexagon_S4_extract_rp : +Hexagon_i32_i32i64_Intrinsic<"HEXAGON_S4_extract_rp">; + +def int_hexagon_S4_extractp : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S4_extractp", [IntrNoMem, ImmArg>, ImmArg>]>; + +def int_hexagon_S4_extractp_rp : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_extractp_rp">; + +def int_hexagon_S4_lsli : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_lsli", [IntrNoMem, ImmArg>]>; + +def int_hexagon_S4_ntstbit_i : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_ntstbit_i", [IntrNoMem, ImmArg>]>; + +def int_hexagon_S4_ntstbit_r : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_ntstbit_r">; + +def int_hexagon_S4_or_andi : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_andi", [IntrNoMem, ImmArg>]>; + +def int_hexagon_S4_or_andix : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_andix", [IntrNoMem, ImmArg>]>; + +def int_hexagon_S4_or_ori : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_ori", [IntrNoMem, ImmArg>]>; + +def int_hexagon_S4_ori_asl_ri : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_ori_asl_ri", [IntrNoMem, ImmArg>, ImmArg>]>; + +def int_hexagon_S4_ori_lsr_ri : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_ori_lsr_ri", [IntrNoMem, ImmArg>, ImmArg>]>; + +def int_hexagon_S4_parity : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_parity">; + +def int_hexagon_S4_subaddi : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subaddi", [IntrNoMem, ImmArg>]>; + +def int_hexagon_S4_subi_asl_ri : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subi_asl_ri", [IntrNoMem, ImmArg>, ImmArg>]>; + +def int_hexagon_S4_subi_lsr_ri : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subi_lsr_ri", [IntrNoMem, ImmArg>, ImmArg>]>; + +def int_hexagon_S4_vrcrotate : +Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S4_vrcrotate", [IntrNoMem, ImmArg>]>; + +def int_hexagon_S4_vrcrotate_acc : +Hexagon_i64_i64i64i32i32_Intrinsic<"HEXAGON_S4_vrcrotate_acc", [IntrNoMem, ImmArg>]>; + +def int_hexagon_S4_vxaddsubh : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxaddsubh">; + +def int_hexagon_S4_vxaddsubhr : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxaddsubhr">; + +def int_hexagon_S4_vxaddsubw : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxaddsubw">; + +def int_hexagon_S4_vxsubaddh : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxsubaddh">; + +def int_hexagon_S4_vxsubaddhr : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxsubaddhr">; + +def int_hexagon_S4_vxsubaddw : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxsubaddw">; + +def int_hexagon_S5_asrhub_rnd_sat_goodsyntax : +Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S5_asrhub_rnd_sat_goodsyntax", [IntrNoMem, ImmArg>]>; + +def int_hexagon_S5_asrhub_sat : +Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S5_asrhub_sat", [IntrNoMem, ImmArg>]>; + +def int_hexagon_S5_popcountp : +Hexagon_i32_i64_Intrinsic<"HEXAGON_S5_popcountp">; + +def int_hexagon_S5_vasrhrnd_goodsyntax : +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S5_vasrhrnd_goodsyntax", [IntrNoMem, ImmArg>]>; def int_hexagon_Y2_dccleana : Hexagon__ptr_Intrinsic<"HEXAGON_Y2_dccleana", []>; @@ -3607,9 +3587,15 @@ Hexagon__ptr_Intrinsic<"HEXAGON_Y2_dccleana", []>; def int_hexagon_Y2_dccleaninva : Hexagon__ptr_Intrinsic<"HEXAGON_Y2_dccleaninva", []>; +def int_hexagon_Y2_dcfetch : +Hexagon__ptr_Intrinsic<"HEXAGON_Y2_dcfetch", []>; + def int_hexagon_Y2_dcinva : Hexagon__ptr_Intrinsic<"HEXAGON_Y2_dcinva", []>; +def int_hexagon_Y2_dczeroa : +Hexagon__ptr_Intrinsic<"HEXAGON_Y2_dczeroa", []>; + def int_hexagon_Y4_l2fetch : Hexagon__ptri32_Intrinsic<"HEXAGON_Y4_l2fetch", []>; @@ -3618,41 +3604,41 @@ Hexagon__ptri64_Intrinsic<"HEXAGON_Y5_l2fetch", []>; // V60 Scalar Instructions. -def int_hexagon_S6_rol_i_r : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S6_rol_i_r", [IntrNoMem, ImmArg>]>; - def int_hexagon_S6_rol_i_p : Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S6_rol_i_p", [IntrNoMem, ImmArg>]>; -def int_hexagon_S6_rol_i_r_acc : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_acc", [IntrNoMem, ImmArg>]>; - def int_hexagon_S6_rol_i_p_acc : Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_acc", [IntrNoMem, ImmArg>]>; -def int_hexagon_S6_rol_i_r_nac : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_nac", [IntrNoMem, ImmArg>]>; +def int_hexagon_S6_rol_i_p_and : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_and", [IntrNoMem, ImmArg>]>; def int_hexagon_S6_rol_i_p_nac : Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_nac", [IntrNoMem, ImmArg>]>; -def int_hexagon_S6_rol_i_r_xacc : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_xacc", [IntrNoMem, ImmArg>]>; +def int_hexagon_S6_rol_i_p_or : +Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_or", [IntrNoMem, ImmArg>]>; def int_hexagon_S6_rol_i_p_xacc : Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_xacc", [IntrNoMem, ImmArg>]>; +def int_hexagon_S6_rol_i_r : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S6_rol_i_r", [IntrNoMem, ImmArg>]>; + +def int_hexagon_S6_rol_i_r_acc : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_acc", [IntrNoMem, ImmArg>]>; + def int_hexagon_S6_rol_i_r_and : Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_and", [IntrNoMem, ImmArg>]>; +def int_hexagon_S6_rol_i_r_nac : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_nac", [IntrNoMem, ImmArg>]>; + def int_hexagon_S6_rol_i_r_or : Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_or", [IntrNoMem, ImmArg>]>; -def int_hexagon_S6_rol_i_p_and : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_and", [IntrNoMem, ImmArg>]>; - -def int_hexagon_S6_rol_i_p_or : -Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_or", [IntrNoMem, ImmArg>]>; +def int_hexagon_S6_rol_i_r_xacc : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_xacc", [IntrNoMem, ImmArg>]>; // V62 Scalar Instructions. @@ -3678,73 +3664,22 @@ Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A6_vcmpbeq_notany">; // V66 Scalar Instructions. -def int_hexagon_M2_mnaci : -Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mnaci">; - def int_hexagon_F2_dfadd : Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfadd", [IntrNoMem, Throws]>; def int_hexagon_F2_dfsub : Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfsub", [IntrNoMem, Throws]>; +def int_hexagon_M2_mnaci : +Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mnaci">; + def int_hexagon_S2_mask : Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_mask", [IntrNoMem, ImmArg>, ImmArg>]>; // V67 Scalar Instructions. -def int_hexagon_M7_dcmpyrw : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M7_dcmpyrw">; - -def int_hexagon_M7_dcmpyrw_acc : -Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M7_dcmpyrw_acc">; - -def int_hexagon_M7_dcmpyrwc : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M7_dcmpyrwc">; - -def int_hexagon_M7_dcmpyrwc_acc : -Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M7_dcmpyrwc_acc">; - -def int_hexagon_M7_dcmpyiw : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M7_dcmpyiw">; - -def int_hexagon_M7_dcmpyiw_acc : -Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M7_dcmpyiw_acc">; - -def int_hexagon_M7_dcmpyiwc : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M7_dcmpyiwc">; - -def int_hexagon_M7_dcmpyiwc_acc : -Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M7_dcmpyiwc_acc">; - -def int_hexagon_M7_vdmpy : -Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M7_vdmpy">; - -def int_hexagon_M7_vdmpy_acc : -Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M7_vdmpy_acc">; - -def int_hexagon_M7_wcmpyrw : -Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyrw">; - -def int_hexagon_M7_wcmpyrwc : -Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyrwc">; - -def int_hexagon_M7_wcmpyiw : -Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyiw">; - -def int_hexagon_M7_wcmpyiwc : -Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyiwc">; - -def int_hexagon_M7_wcmpyrw_rnd : -Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyrw_rnd">; - -def int_hexagon_M7_wcmpyrwc_rnd : -Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyrwc_rnd">; - -def int_hexagon_M7_wcmpyiw_rnd : -Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyiw_rnd">; - -def int_hexagon_M7_wcmpyiwc_rnd : -Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyiwc_rnd">; +def int_hexagon_A7_clip : +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A7_clip", [IntrNoMem, ImmArg>]>; def int_hexagon_A7_croundd_ri : Hexagon_i64_i64i32_Intrinsic<"HEXAGON_A7_croundd_ri", [IntrNoMem, ImmArg>]>; @@ -3752,9 +3687,6 @@ Hexagon_i64_i64i32_Intrinsic<"HEXAGON_A7_croundd_ri", [IntrNoMem, ImmArg; -def int_hexagon_A7_clip : -Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A7_clip", [IntrNoMem, ImmArg>]>; - def int_hexagon_A7_vclip : Hexagon_i64_i64i32_Intrinsic<"HEXAGON_A7_vclip", [IntrNoMem, ImmArg>]>; @@ -3767,22 +3699,156 @@ Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfmin", [IntrNoMem, Throws]>; def int_hexagon_F2_dfmpyfix : Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfmpyfix", [IntrNoMem, Throws]>; -def int_hexagon_F2_dfmpyll : -Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfmpyll", [IntrNoMem, Throws]>; +def int_hexagon_F2_dfmpyhh : +Hexagon_double_doubledoubledouble_Intrinsic<"HEXAGON_F2_dfmpyhh", [IntrNoMem, Throws]>; def int_hexagon_F2_dfmpylh : Hexagon_double_doubledoubledouble_Intrinsic<"HEXAGON_F2_dfmpylh", [IntrNoMem, Throws]>; -def int_hexagon_F2_dfmpyhh : -Hexagon_double_doubledoubledouble_Intrinsic<"HEXAGON_F2_dfmpyhh", [IntrNoMem, Throws]>; +def int_hexagon_F2_dfmpyll : +Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfmpyll", [IntrNoMem, Throws]>; + +def int_hexagon_M7_dcmpyiw : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M7_dcmpyiw">; + +def int_hexagon_M7_dcmpyiw_acc : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M7_dcmpyiw_acc">; + +def int_hexagon_M7_dcmpyiwc : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M7_dcmpyiwc">; + +def int_hexagon_M7_dcmpyiwc_acc : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M7_dcmpyiwc_acc">; + +def int_hexagon_M7_dcmpyrw : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M7_dcmpyrw">; + +def int_hexagon_M7_dcmpyrw_acc : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M7_dcmpyrw_acc">; + +def int_hexagon_M7_dcmpyrwc : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M7_dcmpyrwc">; + +def int_hexagon_M7_dcmpyrwc_acc : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M7_dcmpyrwc_acc">; + +def int_hexagon_M7_vdmpy : +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M7_vdmpy">; + +def int_hexagon_M7_vdmpy_acc : +Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M7_vdmpy_acc">; + +def int_hexagon_M7_wcmpyiw : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyiw">; + +def int_hexagon_M7_wcmpyiw_rnd : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyiw_rnd">; + +def int_hexagon_M7_wcmpyiwc : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyiwc">; + +def int_hexagon_M7_wcmpyiwc_rnd : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyiwc_rnd">; + +def int_hexagon_M7_wcmpyrw : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyrw">; + +def int_hexagon_M7_wcmpyrw_rnd : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyrw_rnd">; + +def int_hexagon_M7_wcmpyrwc : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyrwc">; + +def int_hexagon_M7_wcmpyrwc_rnd : +Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyrwc_rnd">; + +// V68 Scalar Instructions. + +def int_hexagon_Y6_dmlink : +Hexagon__ptrptr_Intrinsic<"HEXAGON_Y6_dmlink", [IntrArgMemOnly, IntrHasSideEffects]>; + +def int_hexagon_Y6_dmpause : +Hexagon_i32__Intrinsic<"HEXAGON_Y6_dmpause", [IntrArgMemOnly, IntrHasSideEffects]>; + +def int_hexagon_Y6_dmpoll : +Hexagon_i32__Intrinsic<"HEXAGON_Y6_dmpoll", [IntrArgMemOnly, IntrHasSideEffects]>; + +def int_hexagon_Y6_dmresume : +Hexagon__ptr_Intrinsic<"HEXAGON_Y6_dmresume", [IntrArgMemOnly, IntrHasSideEffects]>; + +def int_hexagon_Y6_dmstart : +Hexagon__ptr_Intrinsic<"HEXAGON_Y6_dmstart", [IntrArgMemOnly, IntrHasSideEffects]>; + +def int_hexagon_Y6_dmwait : +Hexagon_i32__Intrinsic<"HEXAGON_Y6_dmwait", [IntrArgMemOnly, IntrHasSideEffects]>; // V60 HVX Instructions. -def int_hexagon_V6_vS32b_qpred_ai : -Hexagon_custom__v64i1ptrv16i32_Intrinsic<[IntrWriteMem]>; +def int_hexagon_V6_extractw : +Hexagon_i32_v16i32i32_Intrinsic<"HEXAGON_V6_extractw">; -def int_hexagon_V6_vS32b_qpred_ai_128B : -Hexagon_custom__v128i1ptrv32i32_Intrinsic_128B<[IntrWriteMem]>; +def int_hexagon_V6_extractw_128B : +Hexagon_i32_v32i32i32_Intrinsic<"HEXAGON_V6_extractw_128B">; + +def int_hexagon_V6_hi : +Hexagon_v16i32_v32i32_Intrinsic<"HEXAGON_V6_hi">; + +def int_hexagon_V6_hi_128B : +Hexagon_v32i32_v64i32_Intrinsic<"HEXAGON_V6_hi_128B">; + +def int_hexagon_V6_lo : +Hexagon_v16i32_v32i32_Intrinsic<"HEXAGON_V6_lo">; + +def int_hexagon_V6_lo_128B : +Hexagon_v32i32_v64i32_Intrinsic<"HEXAGON_V6_lo_128B">; + +def int_hexagon_V6_lvsplatw : +Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_lvsplatw">; + +def int_hexagon_V6_lvsplatw_128B : +Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_lvsplatw_128B">; + +def int_hexagon_V6_pred_and : +Hexagon_custom_v64i1_v64i1v64i1_Intrinsic; + +def int_hexagon_V6_pred_and_128B : +Hexagon_custom_v128i1_v128i1v128i1_Intrinsic_128B; + +def int_hexagon_V6_pred_and_n : +Hexagon_custom_v64i1_v64i1v64i1_Intrinsic; + +def int_hexagon_V6_pred_and_n_128B : +Hexagon_custom_v128i1_v128i1v128i1_Intrinsic_128B; + +def int_hexagon_V6_pred_not : +Hexagon_custom_v64i1_v64i1_Intrinsic; + +def int_hexagon_V6_pred_not_128B : +Hexagon_custom_v128i1_v128i1_Intrinsic_128B; + +def int_hexagon_V6_pred_or : +Hexagon_custom_v64i1_v64i1v64i1_Intrinsic; + +def int_hexagon_V6_pred_or_128B : +Hexagon_custom_v128i1_v128i1v128i1_Intrinsic_128B; + +def int_hexagon_V6_pred_or_n : +Hexagon_custom_v64i1_v64i1v64i1_Intrinsic; + +def int_hexagon_V6_pred_or_n_128B : +Hexagon_custom_v128i1_v128i1v128i1_Intrinsic_128B; + +def int_hexagon_V6_pred_scalar2 : +Hexagon_custom_v64i1_i32_Intrinsic; + +def int_hexagon_V6_pred_scalar2_128B : +Hexagon_custom_v128i1_i32_Intrinsic_128B; + +def int_hexagon_V6_pred_xor : +Hexagon_custom_v64i1_v64i1v64i1_Intrinsic; + +def int_hexagon_V6_pred_xor_128B : +Hexagon_custom_v128i1_v128i1v128i1_Intrinsic_128B; def int_hexagon_V6_vS32b_nqpred_ai : Hexagon_custom__v64i1ptrv16i32_Intrinsic<[IntrWriteMem]>; @@ -3790,155 +3856,467 @@ Hexagon_custom__v64i1ptrv16i32_Intrinsic<[IntrWriteMem]>; def int_hexagon_V6_vS32b_nqpred_ai_128B : Hexagon_custom__v128i1ptrv32i32_Intrinsic_128B<[IntrWriteMem]>; -def int_hexagon_V6_vS32b_nt_qpred_ai : -Hexagon_custom__v64i1ptrv16i32_Intrinsic<[IntrWriteMem]>; - -def int_hexagon_V6_vS32b_nt_qpred_ai_128B : -Hexagon_custom__v128i1ptrv32i32_Intrinsic_128B<[IntrWriteMem]>; - def int_hexagon_V6_vS32b_nt_nqpred_ai : Hexagon_custom__v64i1ptrv16i32_Intrinsic<[IntrWriteMem]>; def int_hexagon_V6_vS32b_nt_nqpred_ai_128B : Hexagon_custom__v128i1ptrv32i32_Intrinsic_128B<[IntrWriteMem]>; +def int_hexagon_V6_vS32b_nt_qpred_ai : +Hexagon_custom__v64i1ptrv16i32_Intrinsic<[IntrWriteMem]>; + +def int_hexagon_V6_vS32b_nt_qpred_ai_128B : +Hexagon_custom__v128i1ptrv32i32_Intrinsic_128B<[IntrWriteMem]>; + +def int_hexagon_V6_vS32b_qpred_ai : +Hexagon_custom__v64i1ptrv16i32_Intrinsic<[IntrWriteMem]>; + +def int_hexagon_V6_vS32b_qpred_ai_128B : +Hexagon_custom__v128i1ptrv32i32_Intrinsic_128B<[IntrWriteMem]>; + +def int_hexagon_V6_vabsdiffh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffh">; + +def int_hexagon_V6_vabsdiffh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabsdiffh_128B">; + +def int_hexagon_V6_vabsdiffub : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffub">; + +def int_hexagon_V6_vabsdiffub_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabsdiffub_128B">; + +def int_hexagon_V6_vabsdiffuh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffuh">; + +def int_hexagon_V6_vabsdiffuh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabsdiffuh_128B">; + +def int_hexagon_V6_vabsdiffw : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffw">; + +def int_hexagon_V6_vabsdiffw_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabsdiffw_128B">; + +def int_hexagon_V6_vabsh : +Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsh">; + +def int_hexagon_V6_vabsh_128B : +Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsh_128B">; + +def int_hexagon_V6_vabsh_sat : +Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsh_sat">; + +def int_hexagon_V6_vabsh_sat_128B : +Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsh_sat_128B">; + +def int_hexagon_V6_vabsw : +Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsw">; + +def int_hexagon_V6_vabsw_128B : +Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsw_128B">; + +def int_hexagon_V6_vabsw_sat : +Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsw_sat">; + +def int_hexagon_V6_vabsw_sat_128B : +Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsw_sat_128B">; + +def int_hexagon_V6_vaddb : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddb">; + +def int_hexagon_V6_vaddb_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddb_128B">; + +def int_hexagon_V6_vaddb_dv : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddb_dv">; + +def int_hexagon_V6_vaddb_dv_128B : +Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddb_dv_128B">; + +def int_hexagon_V6_vaddbnq : +Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; + +def int_hexagon_V6_vaddbnq_128B : +Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; + +def int_hexagon_V6_vaddbq : +Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; + +def int_hexagon_V6_vaddbq_128B : +Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; + +def int_hexagon_V6_vaddh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddh">; + +def int_hexagon_V6_vaddh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddh_128B">; + +def int_hexagon_V6_vaddh_dv : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddh_dv">; + +def int_hexagon_V6_vaddh_dv_128B : +Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddh_dv_128B">; + +def int_hexagon_V6_vaddhnq : +Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; + +def int_hexagon_V6_vaddhnq_128B : +Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; + +def int_hexagon_V6_vaddhq : +Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; + +def int_hexagon_V6_vaddhq_128B : +Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; + +def int_hexagon_V6_vaddhsat : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhsat">; + +def int_hexagon_V6_vaddhsat_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhsat_128B">; + +def int_hexagon_V6_vaddhsat_dv : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhsat_dv">; + +def int_hexagon_V6_vaddhsat_dv_128B : +Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddhsat_dv_128B">; + +def int_hexagon_V6_vaddhw : +Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhw">; + +def int_hexagon_V6_vaddhw_128B : +Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhw_128B">; + +def int_hexagon_V6_vaddubh : +Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddubh">; + +def int_hexagon_V6_vaddubh_128B : +Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubh_128B">; + +def int_hexagon_V6_vaddubsat : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddubsat">; + +def int_hexagon_V6_vaddubsat_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubsat_128B">; + +def int_hexagon_V6_vaddubsat_dv : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubsat_dv">; + +def int_hexagon_V6_vaddubsat_dv_128B : +Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddubsat_dv_128B">; + +def int_hexagon_V6_vadduhsat : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduhsat">; + +def int_hexagon_V6_vadduhsat_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhsat_128B">; + +def int_hexagon_V6_vadduhsat_dv : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhsat_dv">; + +def int_hexagon_V6_vadduhsat_dv_128B : +Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vadduhsat_dv_128B">; + +def int_hexagon_V6_vadduhw : +Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduhw">; + +def int_hexagon_V6_vadduhw_128B : +Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhw_128B">; + +def int_hexagon_V6_vaddw : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddw">; + +def int_hexagon_V6_vaddw_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddw_128B">; + +def int_hexagon_V6_vaddw_dv : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddw_dv">; + +def int_hexagon_V6_vaddw_dv_128B : +Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddw_dv_128B">; + +def int_hexagon_V6_vaddwnq : +Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; + +def int_hexagon_V6_vaddwnq_128B : +Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; + +def int_hexagon_V6_vaddwq : +Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; + +def int_hexagon_V6_vaddwq_128B : +Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; + +def int_hexagon_V6_vaddwsat : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddwsat">; + +def int_hexagon_V6_vaddwsat_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwsat_128B">; + +def int_hexagon_V6_vaddwsat_dv : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwsat_dv">; + +def int_hexagon_V6_vaddwsat_dv_128B : +Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddwsat_dv_128B">; + def int_hexagon_V6_valignb : Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_valignb">; def int_hexagon_V6_valignb_128B : Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_valignb_128B">; -def int_hexagon_V6_vlalignb : -Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlalignb">; - -def int_hexagon_V6_vlalignb_128B : -Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlalignb_128B">; - def int_hexagon_V6_valignbi : Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_valignbi", [IntrNoMem, ImmArg>]>; def int_hexagon_V6_valignbi_128B : Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_valignbi_128B", [IntrNoMem, ImmArg>]>; -def int_hexagon_V6_vlalignbi : -Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlalignbi", [IntrNoMem, ImmArg>]>; +def int_hexagon_V6_vand : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vand">; -def int_hexagon_V6_vlalignbi_128B : -Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlalignbi_128B", [IntrNoMem, ImmArg>]>; +def int_hexagon_V6_vand_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vand_128B">; -def int_hexagon_V6_vror : -Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vror">; +def int_hexagon_V6_vandqrt : +Hexagon_custom_v16i32_v64i1i32_Intrinsic; -def int_hexagon_V6_vror_128B : -Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vror_128B">; +def int_hexagon_V6_vandqrt_128B : +Hexagon_custom_v32i32_v128i1i32_Intrinsic_128B; -def int_hexagon_V6_vunpackub : -Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackub">; +def int_hexagon_V6_vandqrt_acc : +Hexagon_custom_v16i32_v16i32v64i1i32_Intrinsic; -def int_hexagon_V6_vunpackub_128B : -Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackub_128B">; +def int_hexagon_V6_vandqrt_acc_128B : +Hexagon_custom_v32i32_v32i32v128i1i32_Intrinsic_128B; -def int_hexagon_V6_vunpackb : -Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackb">; +def int_hexagon_V6_vandvrt : +Hexagon_custom_v64i1_v16i32i32_Intrinsic; -def int_hexagon_V6_vunpackb_128B : -Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackb_128B">; +def int_hexagon_V6_vandvrt_128B : +Hexagon_custom_v128i1_v32i32i32_Intrinsic_128B; -def int_hexagon_V6_vunpackuh : -Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackuh">; +def int_hexagon_V6_vandvrt_acc : +Hexagon_custom_v64i1_v64i1v16i32i32_Intrinsic; -def int_hexagon_V6_vunpackuh_128B : -Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackuh_128B">; +def int_hexagon_V6_vandvrt_acc_128B : +Hexagon_custom_v128i1_v128i1v32i32i32_Intrinsic_128B; -def int_hexagon_V6_vunpackh : -Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackh">; +def int_hexagon_V6_vaslh : +Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vaslh">; -def int_hexagon_V6_vunpackh_128B : -Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackh_128B">; +def int_hexagon_V6_vaslh_128B : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vaslh_128B">; -def int_hexagon_V6_vunpackob : -Hexagon_v32i32_v32i32v16i32_Intrinsic<"HEXAGON_V6_vunpackob">; +def int_hexagon_V6_vaslhv : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaslhv">; -def int_hexagon_V6_vunpackob_128B : -Hexagon_v64i32_v64i32v32i32_Intrinsic<"HEXAGON_V6_vunpackob_128B">; +def int_hexagon_V6_vaslhv_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaslhv_128B">; -def int_hexagon_V6_vunpackoh : -Hexagon_v32i32_v32i32v16i32_Intrinsic<"HEXAGON_V6_vunpackoh">; +def int_hexagon_V6_vaslw : +Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vaslw">; -def int_hexagon_V6_vunpackoh_128B : -Hexagon_v64i32_v64i32v32i32_Intrinsic<"HEXAGON_V6_vunpackoh_128B">; +def int_hexagon_V6_vaslw_128B : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vaslw_128B">; -def int_hexagon_V6_vpackeb : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackeb">; +def int_hexagon_V6_vaslw_acc : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vaslw_acc">; -def int_hexagon_V6_vpackeb_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackeb_128B">; +def int_hexagon_V6_vaslw_acc_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vaslw_acc_128B">; -def int_hexagon_V6_vpackeh : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackeh">; +def int_hexagon_V6_vaslwv : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaslwv">; -def int_hexagon_V6_vpackeh_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackeh_128B">; +def int_hexagon_V6_vaslwv_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaslwv_128B">; -def int_hexagon_V6_vpackob : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackob">; +def int_hexagon_V6_vasrh : +Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vasrh">; -def int_hexagon_V6_vpackob_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackob_128B">; +def int_hexagon_V6_vasrh_128B : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vasrh_128B">; -def int_hexagon_V6_vpackoh : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackoh">; +def int_hexagon_V6_vasrhbrndsat : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhbrndsat">; -def int_hexagon_V6_vpackoh_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackoh_128B">; +def int_hexagon_V6_vasrhbrndsat_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhbrndsat_128B">; -def int_hexagon_V6_vpackhub_sat : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackhub_sat">; +def int_hexagon_V6_vasrhubrndsat : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhubrndsat">; -def int_hexagon_V6_vpackhub_sat_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackhub_sat_128B">; +def int_hexagon_V6_vasrhubrndsat_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhubrndsat_128B">; -def int_hexagon_V6_vpackhb_sat : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackhb_sat">; +def int_hexagon_V6_vasrhubsat : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhubsat">; -def int_hexagon_V6_vpackhb_sat_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackhb_sat_128B">; +def int_hexagon_V6_vasrhubsat_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhubsat_128B">; -def int_hexagon_V6_vpackwuh_sat : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackwuh_sat">; +def int_hexagon_V6_vasrhv : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vasrhv">; -def int_hexagon_V6_vpackwuh_sat_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackwuh_sat_128B">; +def int_hexagon_V6_vasrhv_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vasrhv_128B">; -def int_hexagon_V6_vpackwh_sat : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackwh_sat">; +def int_hexagon_V6_vasrw : +Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vasrw">; -def int_hexagon_V6_vpackwh_sat_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackwh_sat_128B">; +def int_hexagon_V6_vasrw_128B : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vasrw_128B">; -def int_hexagon_V6_vzb : -Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vzb">; +def int_hexagon_V6_vasrw_acc : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrw_acc">; -def int_hexagon_V6_vzb_128B : -Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vzb_128B">; +def int_hexagon_V6_vasrw_acc_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrw_acc_128B">; -def int_hexagon_V6_vsb : -Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vsb">; +def int_hexagon_V6_vasrwh : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwh">; -def int_hexagon_V6_vsb_128B : -Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vsb_128B">; +def int_hexagon_V6_vasrwh_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwh_128B">; -def int_hexagon_V6_vzh : -Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vzh">; +def int_hexagon_V6_vasrwhrndsat : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwhrndsat">; -def int_hexagon_V6_vzh_128B : -Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vzh_128B">; +def int_hexagon_V6_vasrwhrndsat_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwhrndsat_128B">; -def int_hexagon_V6_vsh : -Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vsh">; +def int_hexagon_V6_vasrwhsat : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwhsat">; -def int_hexagon_V6_vsh_128B : -Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vsh_128B">; +def int_hexagon_V6_vasrwhsat_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwhsat_128B">; + +def int_hexagon_V6_vasrwuhsat : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwuhsat">; + +def int_hexagon_V6_vasrwuhsat_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwuhsat_128B">; + +def int_hexagon_V6_vasrwv : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vasrwv">; + +def int_hexagon_V6_vasrwv_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vasrwv_128B">; + +def int_hexagon_V6_vassign : +Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vassign">; + +def int_hexagon_V6_vassign_128B : +Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vassign_128B">; + +def int_hexagon_V6_vassignp : +Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vassignp">; + +def int_hexagon_V6_vassignp_128B : +Hexagon_v64i32_v64i32_Intrinsic<"HEXAGON_V6_vassignp_128B">; + +def int_hexagon_V6_vavgh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgh">; + +def int_hexagon_V6_vavgh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgh_128B">; + +def int_hexagon_V6_vavghrnd : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavghrnd">; + +def int_hexagon_V6_vavghrnd_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavghrnd_128B">; + +def int_hexagon_V6_vavgub : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgub">; + +def int_hexagon_V6_vavgub_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgub_128B">; + +def int_hexagon_V6_vavgubrnd : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgubrnd">; + +def int_hexagon_V6_vavgubrnd_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgubrnd_128B">; + +def int_hexagon_V6_vavguh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguh">; + +def int_hexagon_V6_vavguh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguh_128B">; + +def int_hexagon_V6_vavguhrnd : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguhrnd">; + +def int_hexagon_V6_vavguhrnd_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguhrnd_128B">; + +def int_hexagon_V6_vavgw : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgw">; + +def int_hexagon_V6_vavgw_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgw_128B">; + +def int_hexagon_V6_vavgwrnd : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgwrnd">; + +def int_hexagon_V6_vavgwrnd_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgwrnd_128B">; + +def int_hexagon_V6_vcl0h : +Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vcl0h">; + +def int_hexagon_V6_vcl0h_128B : +Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vcl0h_128B">; + +def int_hexagon_V6_vcl0w : +Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vcl0w">; + +def int_hexagon_V6_vcl0w_128B : +Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vcl0w_128B">; + +def int_hexagon_V6_vcombine : +Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vcombine">; + +def int_hexagon_V6_vcombine_128B : +Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vcombine_128B">; + +def int_hexagon_V6_vd0 : +Hexagon_v16i32__Intrinsic<"HEXAGON_V6_vd0">; + +def int_hexagon_V6_vd0_128B : +Hexagon_v32i32__Intrinsic<"HEXAGON_V6_vd0_128B">; + +def int_hexagon_V6_vdealb : +Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vdealb">; + +def int_hexagon_V6_vdealb_128B : +Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vdealb_128B">; + +def int_hexagon_V6_vdealb4w : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vdealb4w">; + +def int_hexagon_V6_vdealb4w_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vdealb4w_128B">; + +def int_hexagon_V6_vdealh : +Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vdealh">; + +def int_hexagon_V6_vdealh_128B : +Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vdealh_128B">; + +def int_hexagon_V6_vdealvdd : +Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdealvdd">; + +def int_hexagon_V6_vdealvdd_128B : +Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdealvdd_128B">; + +def int_hexagon_V6_vdelta : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vdelta">; + +def int_hexagon_V6_vdelta_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vdelta_128B">; def int_hexagon_V6_vdmpybus : Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpybus">; @@ -3988,17 +4366,17 @@ Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_acc">; def int_hexagon_V6_vdmpyhb_dv_acc_128B : Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_acc_128B">; -def int_hexagon_V6_vdmpyhvsat : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat">; +def int_hexagon_V6_vdmpyhisat : +Hexagon_v16i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat">; -def int_hexagon_V6_vdmpyhvsat_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat_128B">; +def int_hexagon_V6_vdmpyhisat_128B : +Hexagon_v32i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat_128B">; -def int_hexagon_V6_vdmpyhvsat_acc : -Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat_acc">; +def int_hexagon_V6_vdmpyhisat_acc : +Hexagon_v16i32_v16i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat_acc">; -def int_hexagon_V6_vdmpyhvsat_acc_128B : -Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat_acc_128B">; +def int_hexagon_V6_vdmpyhisat_acc_128B : +Hexagon_v32i32_v32i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat_acc_128B">; def int_hexagon_V6_vdmpyhsat : Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat">; @@ -4012,17 +4390,17 @@ Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat_acc">; def int_hexagon_V6_vdmpyhsat_acc_128B : Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat_acc_128B">; -def int_hexagon_V6_vdmpyhisat : -Hexagon_v16i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat">; +def int_hexagon_V6_vdmpyhsuisat : +Hexagon_v16i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat">; -def int_hexagon_V6_vdmpyhisat_128B : -Hexagon_v32i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat_128B">; +def int_hexagon_V6_vdmpyhsuisat_128B : +Hexagon_v32i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_128B">; -def int_hexagon_V6_vdmpyhisat_acc : -Hexagon_v16i32_v16i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat_acc">; +def int_hexagon_V6_vdmpyhsuisat_acc : +Hexagon_v16i32_v16i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_acc">; -def int_hexagon_V6_vdmpyhisat_acc_128B : -Hexagon_v32i32_v32i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat_acc_128B">; +def int_hexagon_V6_vdmpyhsuisat_acc_128B : +Hexagon_v32i32_v32i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_acc_128B">; def int_hexagon_V6_vdmpyhsusat : Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat">; @@ -4036,101 +4414,749 @@ Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat_acc">; def int_hexagon_V6_vdmpyhsusat_acc_128B : Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat_acc_128B">; -def int_hexagon_V6_vdmpyhsuisat : -Hexagon_v16i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat">; +def int_hexagon_V6_vdmpyhvsat : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat">; -def int_hexagon_V6_vdmpyhsuisat_128B : -Hexagon_v32i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_128B">; +def int_hexagon_V6_vdmpyhvsat_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat_128B">; -def int_hexagon_V6_vdmpyhsuisat_acc : -Hexagon_v16i32_v16i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_acc">; +def int_hexagon_V6_vdmpyhvsat_acc : +Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat_acc">; -def int_hexagon_V6_vdmpyhsuisat_acc_128B : -Hexagon_v32i32_v32i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_acc_128B">; +def int_hexagon_V6_vdmpyhvsat_acc_128B : +Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat_acc_128B">; -def int_hexagon_V6_vtmpyb : -Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyb">; +def int_hexagon_V6_vdsaduh : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdsaduh">; -def int_hexagon_V6_vtmpyb_128B : -Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyb_128B">; +def int_hexagon_V6_vdsaduh_128B : +Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdsaduh_128B">; -def int_hexagon_V6_vtmpyb_acc : -Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyb_acc">; +def int_hexagon_V6_vdsaduh_acc : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdsaduh_acc">; -def int_hexagon_V6_vtmpyb_acc_128B : -Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyb_acc_128B">; +def int_hexagon_V6_vdsaduh_acc_128B : +Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vdsaduh_acc_128B">; -def int_hexagon_V6_vtmpybus : -Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vtmpybus">; +def int_hexagon_V6_veqb : +Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; -def int_hexagon_V6_vtmpybus_128B : -Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vtmpybus_128B">; +def int_hexagon_V6_veqb_128B : +Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; -def int_hexagon_V6_vtmpybus_acc : -Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vtmpybus_acc">; +def int_hexagon_V6_veqb_and : +Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; -def int_hexagon_V6_vtmpybus_acc_128B : -Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vtmpybus_acc_128B">; +def int_hexagon_V6_veqb_and_128B : +Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; -def int_hexagon_V6_vtmpyhb : -Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb">; +def int_hexagon_V6_veqb_or : +Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; -def int_hexagon_V6_vtmpyhb_128B : -Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb_128B">; +def int_hexagon_V6_veqb_or_128B : +Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; -def int_hexagon_V6_vtmpyhb_acc : -Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb_acc">; +def int_hexagon_V6_veqb_xor : +Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; -def int_hexagon_V6_vtmpyhb_acc_128B : -Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb_acc_128B">; +def int_hexagon_V6_veqb_xor_128B : +Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; -def int_hexagon_V6_vrmpyub : -Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vrmpyub">; +def int_hexagon_V6_veqh : +Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; -def int_hexagon_V6_vrmpyub_128B : -Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vrmpyub_128B">; +def int_hexagon_V6_veqh_128B : +Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; -def int_hexagon_V6_vrmpyub_acc : -Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vrmpyub_acc">; +def int_hexagon_V6_veqh_and : +Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; -def int_hexagon_V6_vrmpyub_acc_128B : -Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vrmpyub_acc_128B">; +def int_hexagon_V6_veqh_and_128B : +Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; -def int_hexagon_V6_vrmpyubv : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpyubv">; +def int_hexagon_V6_veqh_or : +Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; -def int_hexagon_V6_vrmpyubv_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpyubv_128B">; +def int_hexagon_V6_veqh_or_128B : +Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; -def int_hexagon_V6_vrmpyubv_acc : -Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpyubv_acc">; +def int_hexagon_V6_veqh_xor : +Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; -def int_hexagon_V6_vrmpyubv_acc_128B : -Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpyubv_acc_128B">; +def int_hexagon_V6_veqh_xor_128B : +Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; -def int_hexagon_V6_vrmpybv : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybv">; +def int_hexagon_V6_veqw : +Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; -def int_hexagon_V6_vrmpybv_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybv_128B">; +def int_hexagon_V6_veqw_128B : +Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; -def int_hexagon_V6_vrmpybv_acc : -Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybv_acc">; +def int_hexagon_V6_veqw_and : +Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; -def int_hexagon_V6_vrmpybv_acc_128B : -Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybv_acc_128B">; +def int_hexagon_V6_veqw_and_128B : +Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; -def int_hexagon_V6_vrmpyubi : -Hexagon_v32i32_v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi", [IntrNoMem, ImmArg>]>; +def int_hexagon_V6_veqw_or : +Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; -def int_hexagon_V6_vrmpyubi_128B : -Hexagon_v64i32_v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_128B", [IntrNoMem, ImmArg>]>; +def int_hexagon_V6_veqw_or_128B : +Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; -def int_hexagon_V6_vrmpyubi_acc : -Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_acc", [IntrNoMem, ImmArg>]>; +def int_hexagon_V6_veqw_xor : +Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; -def int_hexagon_V6_vrmpyubi_acc_128B : -Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_acc_128B", [IntrNoMem, ImmArg>]>; +def int_hexagon_V6_veqw_xor_128B : +Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; + +def int_hexagon_V6_vgtb : +Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; + +def int_hexagon_V6_vgtb_128B : +Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; + +def int_hexagon_V6_vgtb_and : +Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; + +def int_hexagon_V6_vgtb_and_128B : +Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; + +def int_hexagon_V6_vgtb_or : +Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; + +def int_hexagon_V6_vgtb_or_128B : +Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; + +def int_hexagon_V6_vgtb_xor : +Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; + +def int_hexagon_V6_vgtb_xor_128B : +Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; + +def int_hexagon_V6_vgth : +Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; + +def int_hexagon_V6_vgth_128B : +Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; + +def int_hexagon_V6_vgth_and : +Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; + +def int_hexagon_V6_vgth_and_128B : +Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; + +def int_hexagon_V6_vgth_or : +Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; + +def int_hexagon_V6_vgth_or_128B : +Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; + +def int_hexagon_V6_vgth_xor : +Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; + +def int_hexagon_V6_vgth_xor_128B : +Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; + +def int_hexagon_V6_vgtub : +Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; + +def int_hexagon_V6_vgtub_128B : +Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; + +def int_hexagon_V6_vgtub_and : +Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; + +def int_hexagon_V6_vgtub_and_128B : +Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; + +def int_hexagon_V6_vgtub_or : +Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; + +def int_hexagon_V6_vgtub_or_128B : +Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; + +def int_hexagon_V6_vgtub_xor : +Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; + +def int_hexagon_V6_vgtub_xor_128B : +Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; + +def int_hexagon_V6_vgtuh : +Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; + +def int_hexagon_V6_vgtuh_128B : +Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; + +def int_hexagon_V6_vgtuh_and : +Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; + +def int_hexagon_V6_vgtuh_and_128B : +Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; + +def int_hexagon_V6_vgtuh_or : +Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; + +def int_hexagon_V6_vgtuh_or_128B : +Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; + +def int_hexagon_V6_vgtuh_xor : +Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; + +def int_hexagon_V6_vgtuh_xor_128B : +Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; + +def int_hexagon_V6_vgtuw : +Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; + +def int_hexagon_V6_vgtuw_128B : +Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; + +def int_hexagon_V6_vgtuw_and : +Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; + +def int_hexagon_V6_vgtuw_and_128B : +Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; + +def int_hexagon_V6_vgtuw_or : +Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; + +def int_hexagon_V6_vgtuw_or_128B : +Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; + +def int_hexagon_V6_vgtuw_xor : +Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; + +def int_hexagon_V6_vgtuw_xor_128B : +Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; + +def int_hexagon_V6_vgtw : +Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; + +def int_hexagon_V6_vgtw_128B : +Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; + +def int_hexagon_V6_vgtw_and : +Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; + +def int_hexagon_V6_vgtw_and_128B : +Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; + +def int_hexagon_V6_vgtw_or : +Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; + +def int_hexagon_V6_vgtw_or_128B : +Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; + +def int_hexagon_V6_vgtw_xor : +Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; + +def int_hexagon_V6_vgtw_xor_128B : +Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; + +def int_hexagon_V6_vinsertwr : +Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vinsertwr">; + +def int_hexagon_V6_vinsertwr_128B : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vinsertwr_128B">; + +def int_hexagon_V6_vlalignb : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlalignb">; + +def int_hexagon_V6_vlalignb_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlalignb_128B">; + +def int_hexagon_V6_vlalignbi : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlalignbi", [IntrNoMem, ImmArg>]>; + +def int_hexagon_V6_vlalignbi_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlalignbi_128B", [IntrNoMem, ImmArg>]>; + +def int_hexagon_V6_vlsrh : +Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vlsrh">; + +def int_hexagon_V6_vlsrh_128B : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vlsrh_128B">; + +def int_hexagon_V6_vlsrhv : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vlsrhv">; + +def int_hexagon_V6_vlsrhv_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vlsrhv_128B">; + +def int_hexagon_V6_vlsrw : +Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vlsrw">; + +def int_hexagon_V6_vlsrw_128B : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vlsrw_128B">; + +def int_hexagon_V6_vlsrwv : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vlsrwv">; + +def int_hexagon_V6_vlsrwv_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vlsrwv_128B">; + +def int_hexagon_V6_vlutvvb : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb">; + +def int_hexagon_V6_vlutvvb_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_128B">; + +def int_hexagon_V6_vlutvvb_oracc : +Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracc">; + +def int_hexagon_V6_vlutvvb_oracc_128B : +Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracc_128B">; + +def int_hexagon_V6_vlutvwh : +Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh">; + +def int_hexagon_V6_vlutvwh_128B : +Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_128B">; + +def int_hexagon_V6_vlutvwh_oracc : +Hexagon_v32i32_v32i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracc">; + +def int_hexagon_V6_vlutvwh_oracc_128B : +Hexagon_v64i32_v64i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracc_128B">; + +def int_hexagon_V6_vmaxh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxh">; + +def int_hexagon_V6_vmaxh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxh_128B">; + +def int_hexagon_V6_vmaxub : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxub">; + +def int_hexagon_V6_vmaxub_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxub_128B">; + +def int_hexagon_V6_vmaxuh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxuh">; + +def int_hexagon_V6_vmaxuh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxuh_128B">; + +def int_hexagon_V6_vmaxw : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxw">; + +def int_hexagon_V6_vmaxw_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxw_128B">; + +def int_hexagon_V6_vminh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminh">; + +def int_hexagon_V6_vminh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminh_128B">; + +def int_hexagon_V6_vminub : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminub">; + +def int_hexagon_V6_vminub_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminub_128B">; + +def int_hexagon_V6_vminuh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminuh">; + +def int_hexagon_V6_vminuh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminuh_128B">; + +def int_hexagon_V6_vminw : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminw">; + +def int_hexagon_V6_vminw_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminw_128B">; + +def int_hexagon_V6_vmpabus : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpabus">; + +def int_hexagon_V6_vmpabus_128B : +Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpabus_128B">; + +def int_hexagon_V6_vmpabus_acc : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpabus_acc">; + +def int_hexagon_V6_vmpabus_acc_128B : +Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpabus_acc_128B">; + +def int_hexagon_V6_vmpabusv : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpabusv">; + +def int_hexagon_V6_vmpabusv_128B : +Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vmpabusv_128B">; + +def int_hexagon_V6_vmpabuuv : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpabuuv">; + +def int_hexagon_V6_vmpabuuv_128B : +Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vmpabuuv_128B">; + +def int_hexagon_V6_vmpahb : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpahb">; + +def int_hexagon_V6_vmpahb_128B : +Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpahb_128B">; + +def int_hexagon_V6_vmpahb_acc : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpahb_acc">; + +def int_hexagon_V6_vmpahb_acc_128B : +Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpahb_acc_128B">; + +def int_hexagon_V6_vmpybus : +Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpybus">; + +def int_hexagon_V6_vmpybus_128B : +Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpybus_128B">; + +def int_hexagon_V6_vmpybus_acc : +Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpybus_acc">; + +def int_hexagon_V6_vmpybus_acc_128B : +Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpybus_acc_128B">; + +def int_hexagon_V6_vmpybusv : +Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybusv">; + +def int_hexagon_V6_vmpybusv_128B : +Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybusv_128B">; + +def int_hexagon_V6_vmpybusv_acc : +Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybusv_acc">; + +def int_hexagon_V6_vmpybusv_acc_128B : +Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybusv_acc_128B">; + +def int_hexagon_V6_vmpybv : +Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybv">; + +def int_hexagon_V6_vmpybv_128B : +Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybv_128B">; + +def int_hexagon_V6_vmpybv_acc : +Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybv_acc">; + +def int_hexagon_V6_vmpybv_acc_128B : +Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybv_acc_128B">; + +def int_hexagon_V6_vmpyewuh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyewuh">; + +def int_hexagon_V6_vmpyewuh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyewuh_128B">; + +def int_hexagon_V6_vmpyh : +Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyh">; + +def int_hexagon_V6_vmpyh_128B : +Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyh_128B">; + +def int_hexagon_V6_vmpyhsat_acc : +Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyhsat_acc">; + +def int_hexagon_V6_vmpyhsat_acc_128B : +Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyhsat_acc_128B">; + +def int_hexagon_V6_vmpyhsrs : +Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyhsrs">; + +def int_hexagon_V6_vmpyhsrs_128B : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyhsrs_128B">; + +def int_hexagon_V6_vmpyhss : +Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyhss">; + +def int_hexagon_V6_vmpyhss_128B : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyhss_128B">; + +def int_hexagon_V6_vmpyhus : +Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhus">; + +def int_hexagon_V6_vmpyhus_128B : +Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhus_128B">; + +def int_hexagon_V6_vmpyhus_acc : +Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhus_acc">; + +def int_hexagon_V6_vmpyhus_acc_128B : +Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhus_acc_128B">; + +def int_hexagon_V6_vmpyhv : +Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhv">; + +def int_hexagon_V6_vmpyhv_128B : +Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhv_128B">; + +def int_hexagon_V6_vmpyhv_acc : +Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhv_acc">; + +def int_hexagon_V6_vmpyhv_acc_128B : +Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhv_acc_128B">; + +def int_hexagon_V6_vmpyhvsrs : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhvsrs">; + +def int_hexagon_V6_vmpyhvsrs_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhvsrs_128B">; + +def int_hexagon_V6_vmpyieoh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyieoh">; + +def int_hexagon_V6_vmpyieoh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyieoh_128B">; + +def int_hexagon_V6_vmpyiewh_acc : +Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiewh_acc">; + +def int_hexagon_V6_vmpyiewh_acc_128B : +Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiewh_acc_128B">; + +def int_hexagon_V6_vmpyiewuh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiewuh">; + +def int_hexagon_V6_vmpyiewuh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiewuh_128B">; + +def int_hexagon_V6_vmpyiewuh_acc : +Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiewuh_acc">; + +def int_hexagon_V6_vmpyiewuh_acc_128B : +Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiewuh_acc_128B">; + +def int_hexagon_V6_vmpyih : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyih">; + +def int_hexagon_V6_vmpyih_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyih_128B">; + +def int_hexagon_V6_vmpyih_acc : +Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyih_acc">; + +def int_hexagon_V6_vmpyih_acc_128B : +Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyih_acc_128B">; + +def int_hexagon_V6_vmpyihb : +Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyihb">; + +def int_hexagon_V6_vmpyihb_128B : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyihb_128B">; + +def int_hexagon_V6_vmpyihb_acc : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyihb_acc">; + +def int_hexagon_V6_vmpyihb_acc_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyihb_acc_128B">; + +def int_hexagon_V6_vmpyiowh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiowh">; + +def int_hexagon_V6_vmpyiowh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiowh_128B">; + +def int_hexagon_V6_vmpyiwb : +Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb">; + +def int_hexagon_V6_vmpyiwb_128B : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb_128B">; + +def int_hexagon_V6_vmpyiwb_acc : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb_acc">; + +def int_hexagon_V6_vmpyiwb_acc_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb_acc_128B">; + +def int_hexagon_V6_vmpyiwh : +Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh">; + +def int_hexagon_V6_vmpyiwh_128B : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh_128B">; + +def int_hexagon_V6_vmpyiwh_acc : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh_acc">; + +def int_hexagon_V6_vmpyiwh_acc_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh_acc_128B">; + +def int_hexagon_V6_vmpyowh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh">; + +def int_hexagon_V6_vmpyowh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_128B">; + +def int_hexagon_V6_vmpyowh_rnd : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd">; + +def int_hexagon_V6_vmpyowh_rnd_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_128B">; + +def int_hexagon_V6_vmpyowh_rnd_sacc : +Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_sacc">; + +def int_hexagon_V6_vmpyowh_rnd_sacc_128B : +Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_sacc_128B">; + +def int_hexagon_V6_vmpyowh_sacc : +Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_sacc">; + +def int_hexagon_V6_vmpyowh_sacc_128B : +Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_sacc_128B">; + +def int_hexagon_V6_vmpyub : +Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyub">; + +def int_hexagon_V6_vmpyub_128B : +Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyub_128B">; + +def int_hexagon_V6_vmpyub_acc : +Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyub_acc">; + +def int_hexagon_V6_vmpyub_acc_128B : +Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyub_acc_128B">; + +def int_hexagon_V6_vmpyubv : +Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyubv">; + +def int_hexagon_V6_vmpyubv_128B : +Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyubv_128B">; + +def int_hexagon_V6_vmpyubv_acc : +Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyubv_acc">; + +def int_hexagon_V6_vmpyubv_acc_128B : +Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyubv_acc_128B">; + +def int_hexagon_V6_vmpyuh : +Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuh">; + +def int_hexagon_V6_vmpyuh_128B : +Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuh_128B">; + +def int_hexagon_V6_vmpyuh_acc : +Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuh_acc">; + +def int_hexagon_V6_vmpyuh_acc_128B : +Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuh_acc_128B">; + +def int_hexagon_V6_vmpyuhv : +Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyuhv">; + +def int_hexagon_V6_vmpyuhv_128B : +Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyuhv_128B">; + +def int_hexagon_V6_vmpyuhv_acc : +Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyuhv_acc">; + +def int_hexagon_V6_vmpyuhv_acc_128B : +Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyuhv_acc_128B">; + +def int_hexagon_V6_vmux : +Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; + +def int_hexagon_V6_vmux_128B : +Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; + +def int_hexagon_V6_vnavgh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgh">; + +def int_hexagon_V6_vnavgh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgh_128B">; + +def int_hexagon_V6_vnavgub : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgub">; + +def int_hexagon_V6_vnavgub_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgub_128B">; + +def int_hexagon_V6_vnavgw : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgw">; + +def int_hexagon_V6_vnavgw_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgw_128B">; + +def int_hexagon_V6_vnormamth : +Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vnormamth">; + +def int_hexagon_V6_vnormamth_128B : +Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vnormamth_128B">; + +def int_hexagon_V6_vnormamtw : +Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vnormamtw">; + +def int_hexagon_V6_vnormamtw_128B : +Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vnormamtw_128B">; + +def int_hexagon_V6_vnot : +Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vnot">; + +def int_hexagon_V6_vnot_128B : +Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vnot_128B">; + +def int_hexagon_V6_vor : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vor">; + +def int_hexagon_V6_vor_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vor_128B">; + +def int_hexagon_V6_vpackeb : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackeb">; + +def int_hexagon_V6_vpackeb_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackeb_128B">; + +def int_hexagon_V6_vpackeh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackeh">; + +def int_hexagon_V6_vpackeh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackeh_128B">; + +def int_hexagon_V6_vpackhb_sat : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackhb_sat">; + +def int_hexagon_V6_vpackhb_sat_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackhb_sat_128B">; + +def int_hexagon_V6_vpackhub_sat : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackhub_sat">; + +def int_hexagon_V6_vpackhub_sat_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackhub_sat_128B">; + +def int_hexagon_V6_vpackob : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackob">; + +def int_hexagon_V6_vpackob_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackob_128B">; + +def int_hexagon_V6_vpackoh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackoh">; + +def int_hexagon_V6_vpackoh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackoh_128B">; + +def int_hexagon_V6_vpackwh_sat : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackwh_sat">; + +def int_hexagon_V6_vpackwh_sat_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackwh_sat_128B">; + +def int_hexagon_V6_vpackwuh_sat : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackwuh_sat">; + +def int_hexagon_V6_vpackwuh_sat_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackwuh_sat_128B">; + +def int_hexagon_V6_vpopcounth : +Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vpopcounth">; + +def int_hexagon_V6_vpopcounth_128B : +Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vpopcounth_128B">; + +def int_hexagon_V6_vrdelta : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrdelta">; + +def int_hexagon_V6_vrdelta_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrdelta_128B">; def int_hexagon_V6_vrmpybus : Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vrmpybus">; @@ -4168,155 +5194,59 @@ Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybusv_acc">; def int_hexagon_V6_vrmpybusv_acc_128B : Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybusv_acc_128B">; -def int_hexagon_V6_vdsaduh : -Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdsaduh">; +def int_hexagon_V6_vrmpybv : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybv">; -def int_hexagon_V6_vdsaduh_128B : -Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdsaduh_128B">; +def int_hexagon_V6_vrmpybv_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybv_128B">; -def int_hexagon_V6_vdsaduh_acc : -Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdsaduh_acc">; +def int_hexagon_V6_vrmpybv_acc : +Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybv_acc">; -def int_hexagon_V6_vdsaduh_acc_128B : -Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vdsaduh_acc_128B">; +def int_hexagon_V6_vrmpybv_acc_128B : +Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybv_acc_128B">; -def int_hexagon_V6_vrsadubi : -Hexagon_v32i32_v32i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi", [IntrNoMem, ImmArg>]>; +def int_hexagon_V6_vrmpyub : +Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vrmpyub">; -def int_hexagon_V6_vrsadubi_128B : -Hexagon_v64i32_v64i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_128B", [IntrNoMem, ImmArg>]>; +def int_hexagon_V6_vrmpyub_128B : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vrmpyub_128B">; -def int_hexagon_V6_vrsadubi_acc : -Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_acc", [IntrNoMem, ImmArg>]>; +def int_hexagon_V6_vrmpyub_acc : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vrmpyub_acc">; -def int_hexagon_V6_vrsadubi_acc_128B : -Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_acc_128B", [IntrNoMem, ImmArg>]>; +def int_hexagon_V6_vrmpyub_acc_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vrmpyub_acc_128B">; -def int_hexagon_V6_vasrw : -Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vasrw">; +def int_hexagon_V6_vrmpyubi : +Hexagon_v32i32_v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi", [IntrNoMem, ImmArg>]>; -def int_hexagon_V6_vasrw_128B : -Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vasrw_128B">; +def int_hexagon_V6_vrmpyubi_128B : +Hexagon_v64i32_v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_128B", [IntrNoMem, ImmArg>]>; -def int_hexagon_V6_vaslw : -Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vaslw">; +def int_hexagon_V6_vrmpyubi_acc : +Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_acc", [IntrNoMem, ImmArg>]>; -def int_hexagon_V6_vaslw_128B : -Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vaslw_128B">; +def int_hexagon_V6_vrmpyubi_acc_128B : +Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_acc_128B", [IntrNoMem, ImmArg>]>; -def int_hexagon_V6_vlsrw : -Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vlsrw">; +def int_hexagon_V6_vrmpyubv : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpyubv">; -def int_hexagon_V6_vlsrw_128B : -Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vlsrw_128B">; +def int_hexagon_V6_vrmpyubv_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpyubv_128B">; -def int_hexagon_V6_vasrwv : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vasrwv">; +def int_hexagon_V6_vrmpyubv_acc : +Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpyubv_acc">; -def int_hexagon_V6_vasrwv_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vasrwv_128B">; +def int_hexagon_V6_vrmpyubv_acc_128B : +Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpyubv_acc_128B">; -def int_hexagon_V6_vaslwv : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaslwv">; +def int_hexagon_V6_vror : +Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vror">; -def int_hexagon_V6_vaslwv_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaslwv_128B">; - -def int_hexagon_V6_vlsrwv : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vlsrwv">; - -def int_hexagon_V6_vlsrwv_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vlsrwv_128B">; - -def int_hexagon_V6_vasrh : -Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vasrh">; - -def int_hexagon_V6_vasrh_128B : -Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vasrh_128B">; - -def int_hexagon_V6_vaslh : -Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vaslh">; - -def int_hexagon_V6_vaslh_128B : -Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vaslh_128B">; - -def int_hexagon_V6_vlsrh : -Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vlsrh">; - -def int_hexagon_V6_vlsrh_128B : -Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vlsrh_128B">; - -def int_hexagon_V6_vasrhv : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vasrhv">; - -def int_hexagon_V6_vasrhv_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vasrhv_128B">; - -def int_hexagon_V6_vaslhv : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaslhv">; - -def int_hexagon_V6_vaslhv_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaslhv_128B">; - -def int_hexagon_V6_vlsrhv : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vlsrhv">; - -def int_hexagon_V6_vlsrhv_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vlsrhv_128B">; - -def int_hexagon_V6_vasrwh : -Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwh">; - -def int_hexagon_V6_vasrwh_128B : -Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwh_128B">; - -def int_hexagon_V6_vasrwhsat : -Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwhsat">; - -def int_hexagon_V6_vasrwhsat_128B : -Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwhsat_128B">; - -def int_hexagon_V6_vasrwhrndsat : -Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwhrndsat">; - -def int_hexagon_V6_vasrwhrndsat_128B : -Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwhrndsat_128B">; - -def int_hexagon_V6_vasrwuhsat : -Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwuhsat">; - -def int_hexagon_V6_vasrwuhsat_128B : -Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwuhsat_128B">; - -def int_hexagon_V6_vroundwh : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundwh">; - -def int_hexagon_V6_vroundwh_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundwh_128B">; - -def int_hexagon_V6_vroundwuh : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundwuh">; - -def int_hexagon_V6_vroundwuh_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundwuh_128B">; - -def int_hexagon_V6_vasrhubsat : -Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhubsat">; - -def int_hexagon_V6_vasrhubsat_128B : -Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhubsat_128B">; - -def int_hexagon_V6_vasrhubrndsat : -Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhubrndsat">; - -def int_hexagon_V6_vasrhubrndsat_128B : -Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhubrndsat_128B">; - -def int_hexagon_V6_vasrhbrndsat : -Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhbrndsat">; - -def int_hexagon_V6_vasrhbrndsat_128B : -Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhbrndsat_128B">; +def int_hexagon_V6_vror_128B : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vror_128B">; def int_hexagon_V6_vroundhb : Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundhb">; @@ -4330,1061 +5260,29 @@ Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundhub">; def int_hexagon_V6_vroundhub_128B : Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundhub_128B">; -def int_hexagon_V6_vaslw_acc : -Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vaslw_acc">; +def int_hexagon_V6_vroundwh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundwh">; -def int_hexagon_V6_vaslw_acc_128B : -Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vaslw_acc_128B">; +def int_hexagon_V6_vroundwh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundwh_128B">; -def int_hexagon_V6_vasrw_acc : -Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrw_acc">; +def int_hexagon_V6_vroundwuh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundwuh">; -def int_hexagon_V6_vasrw_acc_128B : -Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrw_acc_128B">; +def int_hexagon_V6_vroundwuh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundwuh_128B">; -def int_hexagon_V6_vaddb : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddb">; +def int_hexagon_V6_vrsadubi : +Hexagon_v32i32_v32i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi", [IntrNoMem, ImmArg>]>; -def int_hexagon_V6_vaddb_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddb_128B">; +def int_hexagon_V6_vrsadubi_128B : +Hexagon_v64i32_v64i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_128B", [IntrNoMem, ImmArg>]>; -def int_hexagon_V6_vsubb : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubb">; +def int_hexagon_V6_vrsadubi_acc : +Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_acc", [IntrNoMem, ImmArg>]>; -def int_hexagon_V6_vsubb_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubb_128B">; - -def int_hexagon_V6_vaddb_dv : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddb_dv">; - -def int_hexagon_V6_vaddb_dv_128B : -Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddb_dv_128B">; - -def int_hexagon_V6_vsubb_dv : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubb_dv">; - -def int_hexagon_V6_vsubb_dv_128B : -Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubb_dv_128B">; - -def int_hexagon_V6_vaddh : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddh">; - -def int_hexagon_V6_vaddh_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddh_128B">; - -def int_hexagon_V6_vsubh : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubh">; - -def int_hexagon_V6_vsubh_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubh_128B">; - -def int_hexagon_V6_vaddh_dv : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddh_dv">; - -def int_hexagon_V6_vaddh_dv_128B : -Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddh_dv_128B">; - -def int_hexagon_V6_vsubh_dv : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubh_dv">; - -def int_hexagon_V6_vsubh_dv_128B : -Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubh_dv_128B">; - -def int_hexagon_V6_vaddw : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddw">; - -def int_hexagon_V6_vaddw_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddw_128B">; - -def int_hexagon_V6_vsubw : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubw">; - -def int_hexagon_V6_vsubw_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubw_128B">; - -def int_hexagon_V6_vaddw_dv : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddw_dv">; - -def int_hexagon_V6_vaddw_dv_128B : -Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddw_dv_128B">; - -def int_hexagon_V6_vsubw_dv : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubw_dv">; - -def int_hexagon_V6_vsubw_dv_128B : -Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubw_dv_128B">; - -def int_hexagon_V6_vaddubsat : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddubsat">; - -def int_hexagon_V6_vaddubsat_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubsat_128B">; - -def int_hexagon_V6_vaddubsat_dv : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubsat_dv">; - -def int_hexagon_V6_vaddubsat_dv_128B : -Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddubsat_dv_128B">; - -def int_hexagon_V6_vsububsat : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsububsat">; - -def int_hexagon_V6_vsububsat_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsububsat_128B">; - -def int_hexagon_V6_vsububsat_dv : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsububsat_dv">; - -def int_hexagon_V6_vsububsat_dv_128B : -Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsububsat_dv_128B">; - -def int_hexagon_V6_vadduhsat : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduhsat">; - -def int_hexagon_V6_vadduhsat_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhsat_128B">; - -def int_hexagon_V6_vadduhsat_dv : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhsat_dv">; - -def int_hexagon_V6_vadduhsat_dv_128B : -Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vadduhsat_dv_128B">; - -def int_hexagon_V6_vsubuhsat : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubuhsat">; - -def int_hexagon_V6_vsubuhsat_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuhsat_128B">; - -def int_hexagon_V6_vsubuhsat_dv : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuhsat_dv">; - -def int_hexagon_V6_vsubuhsat_dv_128B : -Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubuhsat_dv_128B">; - -def int_hexagon_V6_vaddhsat : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhsat">; - -def int_hexagon_V6_vaddhsat_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhsat_128B">; - -def int_hexagon_V6_vaddhsat_dv : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhsat_dv">; - -def int_hexagon_V6_vaddhsat_dv_128B : -Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddhsat_dv_128B">; - -def int_hexagon_V6_vsubhsat : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhsat">; - -def int_hexagon_V6_vsubhsat_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhsat_128B">; - -def int_hexagon_V6_vsubhsat_dv : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhsat_dv">; - -def int_hexagon_V6_vsubhsat_dv_128B : -Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubhsat_dv_128B">; - -def int_hexagon_V6_vaddwsat : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddwsat">; - -def int_hexagon_V6_vaddwsat_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwsat_128B">; - -def int_hexagon_V6_vaddwsat_dv : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwsat_dv">; - -def int_hexagon_V6_vaddwsat_dv_128B : -Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddwsat_dv_128B">; - -def int_hexagon_V6_vsubwsat : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubwsat">; - -def int_hexagon_V6_vsubwsat_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwsat_128B">; - -def int_hexagon_V6_vsubwsat_dv : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwsat_dv">; - -def int_hexagon_V6_vsubwsat_dv_128B : -Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubwsat_dv_128B">; - -def int_hexagon_V6_vavgub : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgub">; - -def int_hexagon_V6_vavgub_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgub_128B">; - -def int_hexagon_V6_vavgubrnd : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgubrnd">; - -def int_hexagon_V6_vavgubrnd_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgubrnd_128B">; - -def int_hexagon_V6_vavguh : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguh">; - -def int_hexagon_V6_vavguh_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguh_128B">; - -def int_hexagon_V6_vavguhrnd : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguhrnd">; - -def int_hexagon_V6_vavguhrnd_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguhrnd_128B">; - -def int_hexagon_V6_vavgh : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgh">; - -def int_hexagon_V6_vavgh_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgh_128B">; - -def int_hexagon_V6_vavghrnd : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavghrnd">; - -def int_hexagon_V6_vavghrnd_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavghrnd_128B">; - -def int_hexagon_V6_vnavgh : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgh">; - -def int_hexagon_V6_vnavgh_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgh_128B">; - -def int_hexagon_V6_vavgw : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgw">; - -def int_hexagon_V6_vavgw_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgw_128B">; - -def int_hexagon_V6_vavgwrnd : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgwrnd">; - -def int_hexagon_V6_vavgwrnd_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgwrnd_128B">; - -def int_hexagon_V6_vnavgw : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgw">; - -def int_hexagon_V6_vnavgw_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgw_128B">; - -def int_hexagon_V6_vabsdiffub : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffub">; - -def int_hexagon_V6_vabsdiffub_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabsdiffub_128B">; - -def int_hexagon_V6_vabsdiffuh : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffuh">; - -def int_hexagon_V6_vabsdiffuh_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabsdiffuh_128B">; - -def int_hexagon_V6_vabsdiffh : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffh">; - -def int_hexagon_V6_vabsdiffh_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabsdiffh_128B">; - -def int_hexagon_V6_vabsdiffw : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffw">; - -def int_hexagon_V6_vabsdiffw_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabsdiffw_128B">; - -def int_hexagon_V6_vnavgub : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgub">; - -def int_hexagon_V6_vnavgub_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgub_128B">; - -def int_hexagon_V6_vaddubh : -Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddubh">; - -def int_hexagon_V6_vaddubh_128B : -Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubh_128B">; - -def int_hexagon_V6_vsububh : -Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsububh">; - -def int_hexagon_V6_vsububh_128B : -Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsububh_128B">; - -def int_hexagon_V6_vaddhw : -Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhw">; - -def int_hexagon_V6_vaddhw_128B : -Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhw_128B">; - -def int_hexagon_V6_vsubhw : -Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhw">; - -def int_hexagon_V6_vsubhw_128B : -Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhw_128B">; - -def int_hexagon_V6_vadduhw : -Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduhw">; - -def int_hexagon_V6_vadduhw_128B : -Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhw_128B">; - -def int_hexagon_V6_vsubuhw : -Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubuhw">; - -def int_hexagon_V6_vsubuhw_128B : -Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuhw_128B">; - -def int_hexagon_V6_vd0 : -Hexagon_v16i32__Intrinsic<"HEXAGON_V6_vd0">; - -def int_hexagon_V6_vd0_128B : -Hexagon_v32i32__Intrinsic<"HEXAGON_V6_vd0_128B">; - -def int_hexagon_V6_vaddbq : -Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; - -def int_hexagon_V6_vaddbq_128B : -Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_vsubbq : -Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; - -def int_hexagon_V6_vsubbq_128B : -Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_vaddbnq : -Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; - -def int_hexagon_V6_vaddbnq_128B : -Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_vsubbnq : -Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; - -def int_hexagon_V6_vsubbnq_128B : -Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_vaddhq : -Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; - -def int_hexagon_V6_vaddhq_128B : -Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_vsubhq : -Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; - -def int_hexagon_V6_vsubhq_128B : -Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_vaddhnq : -Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; - -def int_hexagon_V6_vaddhnq_128B : -Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_vsubhnq : -Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; - -def int_hexagon_V6_vsubhnq_128B : -Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_vaddwq : -Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; - -def int_hexagon_V6_vaddwq_128B : -Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_vsubwq : -Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; - -def int_hexagon_V6_vsubwq_128B : -Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_vaddwnq : -Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; - -def int_hexagon_V6_vaddwnq_128B : -Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_vsubwnq : -Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; - -def int_hexagon_V6_vsubwnq_128B : -Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_vabsh : -Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsh">; - -def int_hexagon_V6_vabsh_128B : -Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsh_128B">; - -def int_hexagon_V6_vabsh_sat : -Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsh_sat">; - -def int_hexagon_V6_vabsh_sat_128B : -Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsh_sat_128B">; - -def int_hexagon_V6_vabsw : -Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsw">; - -def int_hexagon_V6_vabsw_128B : -Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsw_128B">; - -def int_hexagon_V6_vabsw_sat : -Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsw_sat">; - -def int_hexagon_V6_vabsw_sat_128B : -Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsw_sat_128B">; - -def int_hexagon_V6_vmpybv : -Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybv">; - -def int_hexagon_V6_vmpybv_128B : -Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybv_128B">; - -def int_hexagon_V6_vmpybv_acc : -Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybv_acc">; - -def int_hexagon_V6_vmpybv_acc_128B : -Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybv_acc_128B">; - -def int_hexagon_V6_vmpyubv : -Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyubv">; - -def int_hexagon_V6_vmpyubv_128B : -Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyubv_128B">; - -def int_hexagon_V6_vmpyubv_acc : -Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyubv_acc">; - -def int_hexagon_V6_vmpyubv_acc_128B : -Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyubv_acc_128B">; - -def int_hexagon_V6_vmpybusv : -Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybusv">; - -def int_hexagon_V6_vmpybusv_128B : -Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybusv_128B">; - -def int_hexagon_V6_vmpybusv_acc : -Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybusv_acc">; - -def int_hexagon_V6_vmpybusv_acc_128B : -Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybusv_acc_128B">; - -def int_hexagon_V6_vmpabusv : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpabusv">; - -def int_hexagon_V6_vmpabusv_128B : -Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vmpabusv_128B">; - -def int_hexagon_V6_vmpabuuv : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpabuuv">; - -def int_hexagon_V6_vmpabuuv_128B : -Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vmpabuuv_128B">; - -def int_hexagon_V6_vmpyhv : -Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhv">; - -def int_hexagon_V6_vmpyhv_128B : -Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhv_128B">; - -def int_hexagon_V6_vmpyhv_acc : -Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhv_acc">; - -def int_hexagon_V6_vmpyhv_acc_128B : -Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhv_acc_128B">; - -def int_hexagon_V6_vmpyuhv : -Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyuhv">; - -def int_hexagon_V6_vmpyuhv_128B : -Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyuhv_128B">; - -def int_hexagon_V6_vmpyuhv_acc : -Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyuhv_acc">; - -def int_hexagon_V6_vmpyuhv_acc_128B : -Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyuhv_acc_128B">; - -def int_hexagon_V6_vmpyhvsrs : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhvsrs">; - -def int_hexagon_V6_vmpyhvsrs_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhvsrs_128B">; - -def int_hexagon_V6_vmpyhus : -Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhus">; - -def int_hexagon_V6_vmpyhus_128B : -Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhus_128B">; - -def int_hexagon_V6_vmpyhus_acc : -Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhus_acc">; - -def int_hexagon_V6_vmpyhus_acc_128B : -Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhus_acc_128B">; - -def int_hexagon_V6_vmpyih : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyih">; - -def int_hexagon_V6_vmpyih_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyih_128B">; - -def int_hexagon_V6_vmpyih_acc : -Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyih_acc">; - -def int_hexagon_V6_vmpyih_acc_128B : -Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyih_acc_128B">; - -def int_hexagon_V6_vmpyewuh : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyewuh">; - -def int_hexagon_V6_vmpyewuh_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyewuh_128B">; - -def int_hexagon_V6_vmpyowh : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh">; - -def int_hexagon_V6_vmpyowh_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_128B">; - -def int_hexagon_V6_vmpyowh_rnd : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd">; - -def int_hexagon_V6_vmpyowh_rnd_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_128B">; - -def int_hexagon_V6_vmpyowh_sacc : -Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_sacc">; - -def int_hexagon_V6_vmpyowh_sacc_128B : -Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_sacc_128B">; - -def int_hexagon_V6_vmpyowh_rnd_sacc : -Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_sacc">; - -def int_hexagon_V6_vmpyowh_rnd_sacc_128B : -Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_sacc_128B">; - -def int_hexagon_V6_vmpyieoh : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyieoh">; - -def int_hexagon_V6_vmpyieoh_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyieoh_128B">; - -def int_hexagon_V6_vmpyiewuh : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiewuh">; - -def int_hexagon_V6_vmpyiewuh_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiewuh_128B">; - -def int_hexagon_V6_vmpyiowh : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiowh">; - -def int_hexagon_V6_vmpyiowh_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiowh_128B">; - -def int_hexagon_V6_vmpyiewh_acc : -Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiewh_acc">; - -def int_hexagon_V6_vmpyiewh_acc_128B : -Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiewh_acc_128B">; - -def int_hexagon_V6_vmpyiewuh_acc : -Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiewuh_acc">; - -def int_hexagon_V6_vmpyiewuh_acc_128B : -Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiewuh_acc_128B">; - -def int_hexagon_V6_vmpyub : -Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyub">; - -def int_hexagon_V6_vmpyub_128B : -Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyub_128B">; - -def int_hexagon_V6_vmpyub_acc : -Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyub_acc">; - -def int_hexagon_V6_vmpyub_acc_128B : -Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyub_acc_128B">; - -def int_hexagon_V6_vmpybus : -Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpybus">; - -def int_hexagon_V6_vmpybus_128B : -Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpybus_128B">; - -def int_hexagon_V6_vmpybus_acc : -Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpybus_acc">; - -def int_hexagon_V6_vmpybus_acc_128B : -Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpybus_acc_128B">; - -def int_hexagon_V6_vmpabus : -Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpabus">; - -def int_hexagon_V6_vmpabus_128B : -Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpabus_128B">; - -def int_hexagon_V6_vmpabus_acc : -Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpabus_acc">; - -def int_hexagon_V6_vmpabus_acc_128B : -Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpabus_acc_128B">; - -def int_hexagon_V6_vmpahb : -Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpahb">; - -def int_hexagon_V6_vmpahb_128B : -Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpahb_128B">; - -def int_hexagon_V6_vmpahb_acc : -Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpahb_acc">; - -def int_hexagon_V6_vmpahb_acc_128B : -Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpahb_acc_128B">; - -def int_hexagon_V6_vmpyh : -Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyh">; - -def int_hexagon_V6_vmpyh_128B : -Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyh_128B">; - -def int_hexagon_V6_vmpyhsat_acc : -Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyhsat_acc">; - -def int_hexagon_V6_vmpyhsat_acc_128B : -Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyhsat_acc_128B">; - -def int_hexagon_V6_vmpyhss : -Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyhss">; - -def int_hexagon_V6_vmpyhss_128B : -Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyhss_128B">; - -def int_hexagon_V6_vmpyhsrs : -Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyhsrs">; - -def int_hexagon_V6_vmpyhsrs_128B : -Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyhsrs_128B">; - -def int_hexagon_V6_vmpyuh : -Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuh">; - -def int_hexagon_V6_vmpyuh_128B : -Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuh_128B">; - -def int_hexagon_V6_vmpyuh_acc : -Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuh_acc">; - -def int_hexagon_V6_vmpyuh_acc_128B : -Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuh_acc_128B">; - -def int_hexagon_V6_vmpyihb : -Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyihb">; - -def int_hexagon_V6_vmpyihb_128B : -Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyihb_128B">; - -def int_hexagon_V6_vmpyihb_acc : -Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyihb_acc">; - -def int_hexagon_V6_vmpyihb_acc_128B : -Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyihb_acc_128B">; - -def int_hexagon_V6_vmpyiwb : -Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb">; - -def int_hexagon_V6_vmpyiwb_128B : -Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb_128B">; - -def int_hexagon_V6_vmpyiwb_acc : -Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb_acc">; - -def int_hexagon_V6_vmpyiwb_acc_128B : -Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb_acc_128B">; - -def int_hexagon_V6_vmpyiwh : -Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh">; - -def int_hexagon_V6_vmpyiwh_128B : -Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh_128B">; - -def int_hexagon_V6_vmpyiwh_acc : -Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh_acc">; - -def int_hexagon_V6_vmpyiwh_acc_128B : -Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh_acc_128B">; - -def int_hexagon_V6_vand : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vand">; - -def int_hexagon_V6_vand_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vand_128B">; - -def int_hexagon_V6_vor : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vor">; - -def int_hexagon_V6_vor_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vor_128B">; - -def int_hexagon_V6_vxor : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vxor">; - -def int_hexagon_V6_vxor_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vxor_128B">; - -def int_hexagon_V6_vnot : -Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vnot">; - -def int_hexagon_V6_vnot_128B : -Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vnot_128B">; - -def int_hexagon_V6_vandqrt : -Hexagon_custom_v16i32_v64i1i32_Intrinsic; - -def int_hexagon_V6_vandqrt_128B : -Hexagon_custom_v32i32_v128i1i32_Intrinsic_128B; - -def int_hexagon_V6_vandqrt_acc : -Hexagon_custom_v16i32_v16i32v64i1i32_Intrinsic; - -def int_hexagon_V6_vandqrt_acc_128B : -Hexagon_custom_v32i32_v32i32v128i1i32_Intrinsic_128B; - -def int_hexagon_V6_vandvrt : -Hexagon_custom_v64i1_v16i32i32_Intrinsic; - -def int_hexagon_V6_vandvrt_128B : -Hexagon_custom_v128i1_v32i32i32_Intrinsic_128B; - -def int_hexagon_V6_vandvrt_acc : -Hexagon_custom_v64i1_v64i1v16i32i32_Intrinsic; - -def int_hexagon_V6_vandvrt_acc_128B : -Hexagon_custom_v128i1_v128i1v32i32i32_Intrinsic_128B; - -def int_hexagon_V6_vgtw : -Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; - -def int_hexagon_V6_vgtw_128B : -Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_vgtw_and : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; - -def int_hexagon_V6_vgtw_and_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_vgtw_or : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; - -def int_hexagon_V6_vgtw_or_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_vgtw_xor : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; - -def int_hexagon_V6_vgtw_xor_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_veqw : -Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; - -def int_hexagon_V6_veqw_128B : -Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_veqw_and : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; - -def int_hexagon_V6_veqw_and_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_veqw_or : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; - -def int_hexagon_V6_veqw_or_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_veqw_xor : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; - -def int_hexagon_V6_veqw_xor_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_vgth : -Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; - -def int_hexagon_V6_vgth_128B : -Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_vgth_and : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; - -def int_hexagon_V6_vgth_and_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_vgth_or : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; - -def int_hexagon_V6_vgth_or_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_vgth_xor : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; - -def int_hexagon_V6_vgth_xor_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_veqh : -Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; - -def int_hexagon_V6_veqh_128B : -Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_veqh_and : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; - -def int_hexagon_V6_veqh_and_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_veqh_or : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; - -def int_hexagon_V6_veqh_or_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_veqh_xor : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; - -def int_hexagon_V6_veqh_xor_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_vgtb : -Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; - -def int_hexagon_V6_vgtb_128B : -Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_vgtb_and : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; - -def int_hexagon_V6_vgtb_and_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_vgtb_or : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; - -def int_hexagon_V6_vgtb_or_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_vgtb_xor : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; - -def int_hexagon_V6_vgtb_xor_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_veqb : -Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; - -def int_hexagon_V6_veqb_128B : -Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_veqb_and : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; - -def int_hexagon_V6_veqb_and_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_veqb_or : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; - -def int_hexagon_V6_veqb_or_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_veqb_xor : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; - -def int_hexagon_V6_veqb_xor_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_vgtuw : -Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; - -def int_hexagon_V6_vgtuw_128B : -Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_vgtuw_and : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; - -def int_hexagon_V6_vgtuw_and_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_vgtuw_or : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; - -def int_hexagon_V6_vgtuw_or_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_vgtuw_xor : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; - -def int_hexagon_V6_vgtuw_xor_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_vgtuh : -Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; - -def int_hexagon_V6_vgtuh_128B : -Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_vgtuh_and : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; - -def int_hexagon_V6_vgtuh_and_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_vgtuh_or : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; - -def int_hexagon_V6_vgtuh_or_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_vgtuh_xor : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; - -def int_hexagon_V6_vgtuh_xor_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_vgtub : -Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; - -def int_hexagon_V6_vgtub_128B : -Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_vgtub_and : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; - -def int_hexagon_V6_vgtub_and_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_vgtub_or : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; - -def int_hexagon_V6_vgtub_or_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_vgtub_xor : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; - -def int_hexagon_V6_vgtub_xor_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_pred_or : -Hexagon_custom_v64i1_v64i1v64i1_Intrinsic; - -def int_hexagon_V6_pred_or_128B : -Hexagon_custom_v128i1_v128i1v128i1_Intrinsic_128B; - -def int_hexagon_V6_pred_and : -Hexagon_custom_v64i1_v64i1v64i1_Intrinsic; - -def int_hexagon_V6_pred_and_128B : -Hexagon_custom_v128i1_v128i1v128i1_Intrinsic_128B; - -def int_hexagon_V6_pred_not : -Hexagon_custom_v64i1_v64i1_Intrinsic; - -def int_hexagon_V6_pred_not_128B : -Hexagon_custom_v128i1_v128i1_Intrinsic_128B; - -def int_hexagon_V6_pred_xor : -Hexagon_custom_v64i1_v64i1v64i1_Intrinsic; - -def int_hexagon_V6_pred_xor_128B : -Hexagon_custom_v128i1_v128i1v128i1_Intrinsic_128B; - -def int_hexagon_V6_pred_and_n : -Hexagon_custom_v64i1_v64i1v64i1_Intrinsic; - -def int_hexagon_V6_pred_and_n_128B : -Hexagon_custom_v128i1_v128i1v128i1_Intrinsic_128B; - -def int_hexagon_V6_pred_or_n : -Hexagon_custom_v64i1_v64i1v64i1_Intrinsic; - -def int_hexagon_V6_pred_or_n_128B : -Hexagon_custom_v128i1_v128i1v128i1_Intrinsic_128B; - -def int_hexagon_V6_pred_scalar2 : -Hexagon_custom_v64i1_i32_Intrinsic; - -def int_hexagon_V6_pred_scalar2_128B : -Hexagon_custom_v128i1_i32_Intrinsic_128B; - -def int_hexagon_V6_vmux : -Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; - -def int_hexagon_V6_vmux_128B : -Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_vswap : -Hexagon_custom_v32i32_v64i1v16i32v16i32_Intrinsic; - -def int_hexagon_V6_vswap_128B : -Hexagon_custom_v64i32_v128i1v32i32v32i32_Intrinsic_128B; - -def int_hexagon_V6_vmaxub : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxub">; - -def int_hexagon_V6_vmaxub_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxub_128B">; - -def int_hexagon_V6_vminub : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminub">; - -def int_hexagon_V6_vminub_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminub_128B">; - -def int_hexagon_V6_vmaxuh : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxuh">; - -def int_hexagon_V6_vmaxuh_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxuh_128B">; - -def int_hexagon_V6_vminuh : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminuh">; - -def int_hexagon_V6_vminuh_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminuh_128B">; - -def int_hexagon_V6_vmaxh : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxh">; - -def int_hexagon_V6_vmaxh_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxh_128B">; - -def int_hexagon_V6_vminh : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminh">; - -def int_hexagon_V6_vminh_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminh_128B">; - -def int_hexagon_V6_vmaxw : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxw">; - -def int_hexagon_V6_vmaxw_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxw_128B">; - -def int_hexagon_V6_vminw : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminw">; - -def int_hexagon_V6_vminw_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminw_128B">; +def int_hexagon_V6_vrsadubi_acc_128B : +Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_acc_128B", [IntrNoMem, ImmArg>]>; def int_hexagon_V6_vsathub : Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsathub">; @@ -5398,17 +5296,17 @@ Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsatwh">; def int_hexagon_V6_vsatwh_128B : Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsatwh_128B">; -def int_hexagon_V6_vshuffeb : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshuffeb">; +def int_hexagon_V6_vsb : +Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vsb">; -def int_hexagon_V6_vshuffeb_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshuffeb_128B">; +def int_hexagon_V6_vsb_128B : +Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vsb_128B">; -def int_hexagon_V6_vshuffob : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshuffob">; +def int_hexagon_V6_vsh : +Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vsh">; -def int_hexagon_V6_vshuffob_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshuffob_128B">; +def int_hexagon_V6_vsh_128B : +Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vsh_128B">; def int_hexagon_V6_vshufeh : Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufeh">; @@ -5416,53 +5314,17 @@ Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufeh">; def int_hexagon_V6_vshufeh_128B : Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufeh_128B">; -def int_hexagon_V6_vshufoh : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufoh">; +def int_hexagon_V6_vshuffb : +Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vshuffb">; -def int_hexagon_V6_vshufoh_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufoh_128B">; +def int_hexagon_V6_vshuffb_128B : +Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vshuffb_128B">; -def int_hexagon_V6_vshuffvdd : -Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vshuffvdd">; +def int_hexagon_V6_vshuffeb : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshuffeb">; -def int_hexagon_V6_vshuffvdd_128B : -Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vshuffvdd_128B">; - -def int_hexagon_V6_vdealvdd : -Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdealvdd">; - -def int_hexagon_V6_vdealvdd_128B : -Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdealvdd_128B">; - -def int_hexagon_V6_vshufoeh : -Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufoeh">; - -def int_hexagon_V6_vshufoeh_128B : -Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufoeh_128B">; - -def int_hexagon_V6_vshufoeb : -Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufoeb">; - -def int_hexagon_V6_vshufoeb_128B : -Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufoeb_128B">; - -def int_hexagon_V6_vdealh : -Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vdealh">; - -def int_hexagon_V6_vdealh_128B : -Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vdealh_128B">; - -def int_hexagon_V6_vdealb : -Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vdealb">; - -def int_hexagon_V6_vdealb_128B : -Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vdealb_128B">; - -def int_hexagon_V6_vdealb4w : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vdealb4w">; - -def int_hexagon_V6_vdealb4w_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vdealb4w_128B">; +def int_hexagon_V6_vshuffeb_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshuffeb_128B">; def int_hexagon_V6_vshuffh : Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vshuffh">; @@ -5470,187 +5332,301 @@ Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vshuffh">; def int_hexagon_V6_vshuffh_128B : Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vshuffh_128B">; -def int_hexagon_V6_vshuffb : -Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vshuffb">; +def int_hexagon_V6_vshuffob : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshuffob">; -def int_hexagon_V6_vshuffb_128B : -Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vshuffb_128B">; +def int_hexagon_V6_vshuffob_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshuffob_128B">; -def int_hexagon_V6_extractw : -Hexagon_i32_v16i32i32_Intrinsic<"HEXAGON_V6_extractw">; +def int_hexagon_V6_vshuffvdd : +Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vshuffvdd">; -def int_hexagon_V6_extractw_128B : -Hexagon_i32_v32i32i32_Intrinsic<"HEXAGON_V6_extractw_128B">; +def int_hexagon_V6_vshuffvdd_128B : +Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vshuffvdd_128B">; -def int_hexagon_V6_vinsertwr : -Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vinsertwr">; +def int_hexagon_V6_vshufoeb : +Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufoeb">; -def int_hexagon_V6_vinsertwr_128B : -Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vinsertwr_128B">; +def int_hexagon_V6_vshufoeb_128B : +Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufoeb_128B">; -def int_hexagon_V6_lvsplatw : -Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_lvsplatw">; +def int_hexagon_V6_vshufoeh : +Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufoeh">; -def int_hexagon_V6_lvsplatw_128B : -Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_lvsplatw_128B">; +def int_hexagon_V6_vshufoeh_128B : +Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufoeh_128B">; -def int_hexagon_V6_vassignp : -Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vassignp">; +def int_hexagon_V6_vshufoh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufoh">; -def int_hexagon_V6_vassignp_128B : -Hexagon_v64i32_v64i32_Intrinsic<"HEXAGON_V6_vassignp_128B">; +def int_hexagon_V6_vshufoh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufoh_128B">; -def int_hexagon_V6_vassign : -Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vassign">; +def int_hexagon_V6_vsubb : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubb">; -def int_hexagon_V6_vassign_128B : -Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vassign_128B">; +def int_hexagon_V6_vsubb_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubb_128B">; -def int_hexagon_V6_vcombine : -Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vcombine">; +def int_hexagon_V6_vsubb_dv : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubb_dv">; -def int_hexagon_V6_vcombine_128B : -Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vcombine_128B">; +def int_hexagon_V6_vsubb_dv_128B : +Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubb_dv_128B">; -def int_hexagon_V6_vdelta : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vdelta">; +def int_hexagon_V6_vsubbnq : +Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; -def int_hexagon_V6_vdelta_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vdelta_128B">; +def int_hexagon_V6_vsubbnq_128B : +Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; -def int_hexagon_V6_vrdelta : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrdelta">; +def int_hexagon_V6_vsubbq : +Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; -def int_hexagon_V6_vrdelta_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrdelta_128B">; +def int_hexagon_V6_vsubbq_128B : +Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; -def int_hexagon_V6_vcl0w : -Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vcl0w">; +def int_hexagon_V6_vsubh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubh">; -def int_hexagon_V6_vcl0w_128B : -Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vcl0w_128B">; +def int_hexagon_V6_vsubh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubh_128B">; -def int_hexagon_V6_vcl0h : -Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vcl0h">; +def int_hexagon_V6_vsubh_dv : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubh_dv">; -def int_hexagon_V6_vcl0h_128B : -Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vcl0h_128B">; +def int_hexagon_V6_vsubh_dv_128B : +Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubh_dv_128B">; -def int_hexagon_V6_vnormamtw : -Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vnormamtw">; +def int_hexagon_V6_vsubhnq : +Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; -def int_hexagon_V6_vnormamtw_128B : -Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vnormamtw_128B">; +def int_hexagon_V6_vsubhnq_128B : +Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; -def int_hexagon_V6_vnormamth : -Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vnormamth">; +def int_hexagon_V6_vsubhq : +Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; -def int_hexagon_V6_vnormamth_128B : -Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vnormamth_128B">; +def int_hexagon_V6_vsubhq_128B : +Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; -def int_hexagon_V6_vpopcounth : -Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vpopcounth">; +def int_hexagon_V6_vsubhsat : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhsat">; -def int_hexagon_V6_vpopcounth_128B : -Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vpopcounth_128B">; +def int_hexagon_V6_vsubhsat_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhsat_128B">; -def int_hexagon_V6_vlutvvb : -Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb">; +def int_hexagon_V6_vsubhsat_dv : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhsat_dv">; -def int_hexagon_V6_vlutvvb_128B : -Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_128B">; +def int_hexagon_V6_vsubhsat_dv_128B : +Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubhsat_dv_128B">; -def int_hexagon_V6_vlutvvb_oracc : -Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracc">; +def int_hexagon_V6_vsubhw : +Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhw">; -def int_hexagon_V6_vlutvvb_oracc_128B : -Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracc_128B">; +def int_hexagon_V6_vsubhw_128B : +Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhw_128B">; -def int_hexagon_V6_vlutvwh : -Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh">; +def int_hexagon_V6_vsububh : +Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsububh">; -def int_hexagon_V6_vlutvwh_128B : -Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_128B">; +def int_hexagon_V6_vsububh_128B : +Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsububh_128B">; -def int_hexagon_V6_vlutvwh_oracc : -Hexagon_v32i32_v32i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracc">; +def int_hexagon_V6_vsububsat : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsububsat">; -def int_hexagon_V6_vlutvwh_oracc_128B : -Hexagon_v64i32_v64i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracc_128B">; +def int_hexagon_V6_vsububsat_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsububsat_128B">; -def int_hexagon_V6_hi : -Hexagon_v16i32_v32i32_Intrinsic<"HEXAGON_V6_hi">; +def int_hexagon_V6_vsububsat_dv : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsububsat_dv">; -def int_hexagon_V6_hi_128B : -Hexagon_v32i32_v64i32_Intrinsic<"HEXAGON_V6_hi_128B">; +def int_hexagon_V6_vsububsat_dv_128B : +Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsububsat_dv_128B">; -def int_hexagon_V6_lo : -Hexagon_v16i32_v32i32_Intrinsic<"HEXAGON_V6_lo">; +def int_hexagon_V6_vsubuhsat : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubuhsat">; -def int_hexagon_V6_lo_128B : -Hexagon_v32i32_v64i32_Intrinsic<"HEXAGON_V6_lo_128B">; +def int_hexagon_V6_vsubuhsat_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuhsat_128B">; + +def int_hexagon_V6_vsubuhsat_dv : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuhsat_dv">; + +def int_hexagon_V6_vsubuhsat_dv_128B : +Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubuhsat_dv_128B">; + +def int_hexagon_V6_vsubuhw : +Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubuhw">; + +def int_hexagon_V6_vsubuhw_128B : +Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuhw_128B">; + +def int_hexagon_V6_vsubw : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubw">; + +def int_hexagon_V6_vsubw_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubw_128B">; + +def int_hexagon_V6_vsubw_dv : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubw_dv">; + +def int_hexagon_V6_vsubw_dv_128B : +Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubw_dv_128B">; + +def int_hexagon_V6_vsubwnq : +Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; + +def int_hexagon_V6_vsubwnq_128B : +Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; + +def int_hexagon_V6_vsubwq : +Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; + +def int_hexagon_V6_vsubwq_128B : +Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; + +def int_hexagon_V6_vsubwsat : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubwsat">; + +def int_hexagon_V6_vsubwsat_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwsat_128B">; + +def int_hexagon_V6_vsubwsat_dv : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwsat_dv">; + +def int_hexagon_V6_vsubwsat_dv_128B : +Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubwsat_dv_128B">; + +def int_hexagon_V6_vswap : +Hexagon_custom_v32i32_v64i1v16i32v16i32_Intrinsic; + +def int_hexagon_V6_vswap_128B : +Hexagon_custom_v64i32_v128i1v32i32v32i32_Intrinsic_128B; + +def int_hexagon_V6_vtmpyb : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyb">; + +def int_hexagon_V6_vtmpyb_128B : +Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyb_128B">; + +def int_hexagon_V6_vtmpyb_acc : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyb_acc">; + +def int_hexagon_V6_vtmpyb_acc_128B : +Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyb_acc_128B">; + +def int_hexagon_V6_vtmpybus : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vtmpybus">; + +def int_hexagon_V6_vtmpybus_128B : +Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vtmpybus_128B">; + +def int_hexagon_V6_vtmpybus_acc : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vtmpybus_acc">; + +def int_hexagon_V6_vtmpybus_acc_128B : +Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vtmpybus_acc_128B">; + +def int_hexagon_V6_vtmpyhb : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb">; + +def int_hexagon_V6_vtmpyhb_128B : +Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb_128B">; + +def int_hexagon_V6_vtmpyhb_acc : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb_acc">; + +def int_hexagon_V6_vtmpyhb_acc_128B : +Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb_acc_128B">; + +def int_hexagon_V6_vunpackb : +Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackb">; + +def int_hexagon_V6_vunpackb_128B : +Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackb_128B">; + +def int_hexagon_V6_vunpackh : +Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackh">; + +def int_hexagon_V6_vunpackh_128B : +Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackh_128B">; + +def int_hexagon_V6_vunpackob : +Hexagon_v32i32_v32i32v16i32_Intrinsic<"HEXAGON_V6_vunpackob">; + +def int_hexagon_V6_vunpackob_128B : +Hexagon_v64i32_v64i32v32i32_Intrinsic<"HEXAGON_V6_vunpackob_128B">; + +def int_hexagon_V6_vunpackoh : +Hexagon_v32i32_v32i32v16i32_Intrinsic<"HEXAGON_V6_vunpackoh">; + +def int_hexagon_V6_vunpackoh_128B : +Hexagon_v64i32_v64i32v32i32_Intrinsic<"HEXAGON_V6_vunpackoh_128B">; + +def int_hexagon_V6_vunpackub : +Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackub">; + +def int_hexagon_V6_vunpackub_128B : +Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackub_128B">; + +def int_hexagon_V6_vunpackuh : +Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackuh">; + +def int_hexagon_V6_vunpackuh_128B : +Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackuh_128B">; + +def int_hexagon_V6_vxor : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vxor">; + +def int_hexagon_V6_vxor_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vxor_128B">; + +def int_hexagon_V6_vzb : +Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vzb">; + +def int_hexagon_V6_vzb_128B : +Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vzb_128B">; + +def int_hexagon_V6_vzh : +Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vzh">; + +def int_hexagon_V6_vzh_128B : +Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vzh_128B">; // V62 HVX Instructions. -def int_hexagon_V6_vlsrb : -Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vlsrb">; +def int_hexagon_V6_lvsplatb : +Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_lvsplatb">; -def int_hexagon_V6_vlsrb_128B : -Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vlsrb_128B">; +def int_hexagon_V6_lvsplatb_128B : +Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_lvsplatb_128B">; -def int_hexagon_V6_vasrwuhrndsat : -Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwuhrndsat">; +def int_hexagon_V6_lvsplath : +Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_lvsplath">; -def int_hexagon_V6_vasrwuhrndsat_128B : -Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwuhrndsat_128B">; +def int_hexagon_V6_lvsplath_128B : +Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_lvsplath_128B">; -def int_hexagon_V6_vasruwuhrndsat : -Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruwuhrndsat">; +def int_hexagon_V6_pred_scalar2v2 : +Hexagon_custom_v64i1_i32_Intrinsic; -def int_hexagon_V6_vasruwuhrndsat_128B : -Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruwuhrndsat_128B">; +def int_hexagon_V6_pred_scalar2v2_128B : +Hexagon_custom_v128i1_i32_Intrinsic_128B; -def int_hexagon_V6_vasrhbsat : -Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhbsat">; +def int_hexagon_V6_shuffeqh : +Hexagon_custom_v64i1_v64i1v64i1_Intrinsic; -def int_hexagon_V6_vasrhbsat_128B : -Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhbsat_128B">; +def int_hexagon_V6_shuffeqh_128B : +Hexagon_custom_v128i1_v128i1v128i1_Intrinsic_128B; -def int_hexagon_V6_vrounduwuh : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrounduwuh">; +def int_hexagon_V6_shuffeqw : +Hexagon_custom_v64i1_v64i1v64i1_Intrinsic; -def int_hexagon_V6_vrounduwuh_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrounduwuh_128B">; - -def int_hexagon_V6_vrounduhub : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrounduhub">; - -def int_hexagon_V6_vrounduhub_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrounduhub_128B">; - -def int_hexagon_V6_vadduwsat : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduwsat">; - -def int_hexagon_V6_vadduwsat_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduwsat_128B">; - -def int_hexagon_V6_vadduwsat_dv : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduwsat_dv">; - -def int_hexagon_V6_vadduwsat_dv_128B : -Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vadduwsat_dv_128B">; - -def int_hexagon_V6_vsubuwsat : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubuwsat">; - -def int_hexagon_V6_vsubuwsat_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuwsat_128B">; - -def int_hexagon_V6_vsubuwsat_dv : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuwsat_dv">; - -def int_hexagon_V6_vsubuwsat_dv_128B : -Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubuwsat_dv_128B">; +def int_hexagon_V6_shuffeqw_128B : +Hexagon_custom_v128i1_v128i1v128i1_Intrinsic_128B; def int_hexagon_V6_vaddbsat : Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddbsat">; @@ -5664,41 +5640,23 @@ Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddbsat_dv">; def int_hexagon_V6_vaddbsat_dv_128B : Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddbsat_dv_128B">; -def int_hexagon_V6_vsubbsat : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubbsat">; - -def int_hexagon_V6_vsubbsat_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbsat_128B">; - -def int_hexagon_V6_vsubbsat_dv : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbsat_dv">; - -def int_hexagon_V6_vsubbsat_dv_128B : -Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubbsat_dv_128B">; - def int_hexagon_V6_vaddcarry : Hexagon_custom_v16i32v64i1_v16i32v16i32v64i1_Intrinsic; def int_hexagon_V6_vaddcarry_128B : Hexagon_custom_v32i32v128i1_v32i32v32i32v128i1_Intrinsic_128B; -def int_hexagon_V6_vsubcarry : -Hexagon_custom_v16i32v64i1_v16i32v16i32v64i1_Intrinsic; +def int_hexagon_V6_vaddclbh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddclbh">; -def int_hexagon_V6_vsubcarry_128B : -Hexagon_custom_v32i32v128i1_v32i32v32i32v128i1_Intrinsic_128B; +def int_hexagon_V6_vaddclbh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddclbh_128B">; -def int_hexagon_V6_vaddububb_sat : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddububb_sat">; +def int_hexagon_V6_vaddclbw : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddclbw">; -def int_hexagon_V6_vaddububb_sat_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddububb_sat_128B">; - -def int_hexagon_V6_vsubububb_sat : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubububb_sat">; - -def int_hexagon_V6_vsubububb_sat_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubububb_sat_128B">; +def int_hexagon_V6_vaddclbw_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddclbw_128B">; def int_hexagon_V6_vaddhw_acc : Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhw_acc">; @@ -5706,53 +5664,35 @@ Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhw_acc">; def int_hexagon_V6_vaddhw_acc_128B : Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhw_acc_128B">; -def int_hexagon_V6_vadduhw_acc : -Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduhw_acc">; - -def int_hexagon_V6_vadduhw_acc_128B : -Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhw_acc_128B">; - def int_hexagon_V6_vaddubh_acc : Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddubh_acc">; def int_hexagon_V6_vaddubh_acc_128B : Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubh_acc_128B">; -def int_hexagon_V6_vmpyewuh_64 : -Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyewuh_64">; +def int_hexagon_V6_vaddububb_sat : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddububb_sat">; -def int_hexagon_V6_vmpyewuh_64_128B : -Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyewuh_64_128B">; +def int_hexagon_V6_vaddububb_sat_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddububb_sat_128B">; -def int_hexagon_V6_vmpyowh_64_acc : -Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_64_acc">; +def int_hexagon_V6_vadduhw_acc : +Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduhw_acc">; -def int_hexagon_V6_vmpyowh_64_acc_128B : -Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_64_acc_128B">; +def int_hexagon_V6_vadduhw_acc_128B : +Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhw_acc_128B">; -def int_hexagon_V6_vmpauhb : -Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpauhb">; +def int_hexagon_V6_vadduwsat : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduwsat">; -def int_hexagon_V6_vmpauhb_128B : -Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpauhb_128B">; +def int_hexagon_V6_vadduwsat_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduwsat_128B">; -def int_hexagon_V6_vmpauhb_acc : -Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpauhb_acc">; +def int_hexagon_V6_vadduwsat_dv : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduwsat_dv">; -def int_hexagon_V6_vmpauhb_acc_128B : -Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpauhb_acc_128B">; - -def int_hexagon_V6_vmpyiwub : -Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub">; - -def int_hexagon_V6_vmpyiwub_128B : -Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub_128B">; - -def int_hexagon_V6_vmpyiwub_acc : -Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub_acc">; - -def int_hexagon_V6_vmpyiwub_acc_128B : -Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub_acc_128B">; +def int_hexagon_V6_vadduwsat_dv_128B : +Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vadduwsat_dv_128B">; def int_hexagon_V6_vandnqrt : Hexagon_custom_v16i32_v64i1i32_Intrinsic; @@ -5766,35 +5706,77 @@ Hexagon_custom_v16i32_v16i32v64i1i32_Intrinsic; def int_hexagon_V6_vandnqrt_acc_128B : Hexagon_custom_v32i32_v32i32v128i1i32_Intrinsic_128B; -def int_hexagon_V6_vandvqv : -Hexagon_custom_v16i32_v64i1v16i32_Intrinsic; - -def int_hexagon_V6_vandvqv_128B : -Hexagon_custom_v32i32_v128i1v32i32_Intrinsic_128B; - def int_hexagon_V6_vandvnqv : Hexagon_custom_v16i32_v64i1v16i32_Intrinsic; def int_hexagon_V6_vandvnqv_128B : Hexagon_custom_v32i32_v128i1v32i32_Intrinsic_128B; -def int_hexagon_V6_pred_scalar2v2 : -Hexagon_custom_v64i1_i32_Intrinsic; +def int_hexagon_V6_vandvqv : +Hexagon_custom_v16i32_v64i1v16i32_Intrinsic; -def int_hexagon_V6_pred_scalar2v2_128B : -Hexagon_custom_v128i1_i32_Intrinsic_128B; +def int_hexagon_V6_vandvqv_128B : +Hexagon_custom_v32i32_v128i1v32i32_Intrinsic_128B; -def int_hexagon_V6_shuffeqw : -Hexagon_custom_v64i1_v64i1v64i1_Intrinsic; +def int_hexagon_V6_vasrhbsat : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhbsat">; -def int_hexagon_V6_shuffeqw_128B : -Hexagon_custom_v128i1_v128i1v128i1_Intrinsic_128B; +def int_hexagon_V6_vasrhbsat_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhbsat_128B">; -def int_hexagon_V6_shuffeqh : -Hexagon_custom_v64i1_v64i1v64i1_Intrinsic; +def int_hexagon_V6_vasruwuhrndsat : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruwuhrndsat">; -def int_hexagon_V6_shuffeqh_128B : -Hexagon_custom_v128i1_v128i1v128i1_Intrinsic_128B; +def int_hexagon_V6_vasruwuhrndsat_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruwuhrndsat_128B">; + +def int_hexagon_V6_vasrwuhrndsat : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwuhrndsat">; + +def int_hexagon_V6_vasrwuhrndsat_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwuhrndsat_128B">; + +def int_hexagon_V6_vlsrb : +Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vlsrb">; + +def int_hexagon_V6_vlsrb_128B : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vlsrb_128B">; + +def int_hexagon_V6_vlutvvb_nm : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_nm">; + +def int_hexagon_V6_vlutvvb_nm_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_nm_128B">; + +def int_hexagon_V6_vlutvvb_oracci : +Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracci", [IntrNoMem, ImmArg>]>; + +def int_hexagon_V6_vlutvvb_oracci_128B : +Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracci_128B", [IntrNoMem, ImmArg>]>; + +def int_hexagon_V6_vlutvvbi : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvbi", [IntrNoMem, ImmArg>]>; + +def int_hexagon_V6_vlutvvbi_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvbi_128B", [IntrNoMem, ImmArg>]>; + +def int_hexagon_V6_vlutvwh_nm : +Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_nm">; + +def int_hexagon_V6_vlutvwh_nm_128B : +Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_nm_128B">; + +def int_hexagon_V6_vlutvwh_oracci : +Hexagon_v32i32_v32i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracci", [IntrNoMem, ImmArg>]>; + +def int_hexagon_V6_vlutvwh_oracci_128B : +Hexagon_v64i32_v64i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracci_128B", [IntrNoMem, ImmArg>]>; + +def int_hexagon_V6_vlutvwhi : +Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwhi", [IntrNoMem, ImmArg>]>; + +def int_hexagon_V6_vlutvwhi_128B : +Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwhi_128B", [IntrNoMem, ImmArg>]>; def int_hexagon_V6_vmaxb : Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxb">; @@ -5808,140 +5790,98 @@ Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminb">; def int_hexagon_V6_vminb_128B : Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminb_128B">; +def int_hexagon_V6_vmpauhb : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpauhb">; + +def int_hexagon_V6_vmpauhb_128B : +Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpauhb_128B">; + +def int_hexagon_V6_vmpauhb_acc : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpauhb_acc">; + +def int_hexagon_V6_vmpauhb_acc_128B : +Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpauhb_acc_128B">; + +def int_hexagon_V6_vmpyewuh_64 : +Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyewuh_64">; + +def int_hexagon_V6_vmpyewuh_64_128B : +Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyewuh_64_128B">; + +def int_hexagon_V6_vmpyiwub : +Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub">; + +def int_hexagon_V6_vmpyiwub_128B : +Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub_128B">; + +def int_hexagon_V6_vmpyiwub_acc : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub_acc">; + +def int_hexagon_V6_vmpyiwub_acc_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub_acc_128B">; + +def int_hexagon_V6_vmpyowh_64_acc : +Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_64_acc">; + +def int_hexagon_V6_vmpyowh_64_acc_128B : +Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_64_acc_128B">; + +def int_hexagon_V6_vrounduhub : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrounduhub">; + +def int_hexagon_V6_vrounduhub_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrounduhub_128B">; + +def int_hexagon_V6_vrounduwuh : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrounduwuh">; + +def int_hexagon_V6_vrounduwuh_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrounduwuh_128B">; + def int_hexagon_V6_vsatuwuh : Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsatuwuh">; def int_hexagon_V6_vsatuwuh_128B : Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsatuwuh_128B">; -def int_hexagon_V6_lvsplath : -Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_lvsplath">; +def int_hexagon_V6_vsubbsat : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubbsat">; -def int_hexagon_V6_lvsplath_128B : -Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_lvsplath_128B">; +def int_hexagon_V6_vsubbsat_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbsat_128B">; -def int_hexagon_V6_lvsplatb : -Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_lvsplatb">; +def int_hexagon_V6_vsubbsat_dv : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbsat_dv">; -def int_hexagon_V6_lvsplatb_128B : -Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_lvsplatb_128B">; +def int_hexagon_V6_vsubbsat_dv_128B : +Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubbsat_dv_128B">; -def int_hexagon_V6_vaddclbw : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddclbw">; +def int_hexagon_V6_vsubcarry : +Hexagon_custom_v16i32v64i1_v16i32v16i32v64i1_Intrinsic; -def int_hexagon_V6_vaddclbw_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddclbw_128B">; +def int_hexagon_V6_vsubcarry_128B : +Hexagon_custom_v32i32v128i1_v32i32v32i32v128i1_Intrinsic_128B; -def int_hexagon_V6_vaddclbh : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddclbh">; +def int_hexagon_V6_vsubububb_sat : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubububb_sat">; -def int_hexagon_V6_vaddclbh_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddclbh_128B">; +def int_hexagon_V6_vsubububb_sat_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubububb_sat_128B">; -def int_hexagon_V6_vlutvvbi : -Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvbi", [IntrNoMem, ImmArg>]>; +def int_hexagon_V6_vsubuwsat : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubuwsat">; -def int_hexagon_V6_vlutvvbi_128B : -Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvbi_128B", [IntrNoMem, ImmArg>]>; +def int_hexagon_V6_vsubuwsat_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuwsat_128B">; -def int_hexagon_V6_vlutvvb_oracci : -Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracci", [IntrNoMem, ImmArg>]>; +def int_hexagon_V6_vsubuwsat_dv : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuwsat_dv">; -def int_hexagon_V6_vlutvvb_oracci_128B : -Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracci_128B", [IntrNoMem, ImmArg>]>; - -def int_hexagon_V6_vlutvwhi : -Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwhi", [IntrNoMem, ImmArg>]>; - -def int_hexagon_V6_vlutvwhi_128B : -Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwhi_128B", [IntrNoMem, ImmArg>]>; - -def int_hexagon_V6_vlutvwh_oracci : -Hexagon_v32i32_v32i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracci", [IntrNoMem, ImmArg>]>; - -def int_hexagon_V6_vlutvwh_oracci_128B : -Hexagon_v64i32_v64i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracci_128B", [IntrNoMem, ImmArg>]>; - -def int_hexagon_V6_vlutvvb_nm : -Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_nm">; - -def int_hexagon_V6_vlutvvb_nm_128B : -Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_nm_128B">; - -def int_hexagon_V6_vlutvwh_nm : -Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_nm">; - -def int_hexagon_V6_vlutvwh_nm_128B : -Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_nm_128B">; +def int_hexagon_V6_vsubuwsat_dv_128B : +Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubuwsat_dv_128B">; // V65 HVX Instructions. -def int_hexagon_V6_vasruwuhsat : -Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruwuhsat">; - -def int_hexagon_V6_vasruwuhsat_128B : -Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruwuhsat_128B">; - -def int_hexagon_V6_vasruhubsat : -Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruhubsat">; - -def int_hexagon_V6_vasruhubsat_128B : -Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruhubsat_128B">; - -def int_hexagon_V6_vasruhubrndsat : -Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruhubrndsat">; - -def int_hexagon_V6_vasruhubrndsat_128B : -Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruhubrndsat_128B">; - -def int_hexagon_V6_vaslh_acc : -Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vaslh_acc">; - -def int_hexagon_V6_vaslh_acc_128B : -Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vaslh_acc_128B">; - -def int_hexagon_V6_vasrh_acc : -Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrh_acc">; - -def int_hexagon_V6_vasrh_acc_128B : -Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrh_acc_128B">; - -def int_hexagon_V6_vavguw : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguw">; - -def int_hexagon_V6_vavguw_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguw_128B">; - -def int_hexagon_V6_vavguwrnd : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguwrnd">; - -def int_hexagon_V6_vavguwrnd_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguwrnd_128B">; - -def int_hexagon_V6_vavgb : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgb">; - -def int_hexagon_V6_vavgb_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgb_128B">; - -def int_hexagon_V6_vavgbrnd : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgbrnd">; - -def int_hexagon_V6_vavgbrnd_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgbrnd_128B">; - -def int_hexagon_V6_vnavgb : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgb">; - -def int_hexagon_V6_vnavgb_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgb_128B">; - -def int_hexagon_V6_vdd0 : -Hexagon_v32i32__Intrinsic<"HEXAGON_V6_vdd0">; - -def int_hexagon_V6_vdd0_128B : -Hexagon_v64i32__Intrinsic<"HEXAGON_V6_vdd0_128B">; - def int_hexagon_V6_vabsb : Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsb">; @@ -5954,6 +5894,108 @@ Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsb_sat">; def int_hexagon_V6_vabsb_sat_128B : Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsb_sat_128B">; +def int_hexagon_V6_vaslh_acc : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vaslh_acc">; + +def int_hexagon_V6_vaslh_acc_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vaslh_acc_128B">; + +def int_hexagon_V6_vasrh_acc : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrh_acc">; + +def int_hexagon_V6_vasrh_acc_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrh_acc_128B">; + +def int_hexagon_V6_vasruhubrndsat : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruhubrndsat">; + +def int_hexagon_V6_vasruhubrndsat_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruhubrndsat_128B">; + +def int_hexagon_V6_vasruhubsat : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruhubsat">; + +def int_hexagon_V6_vasruhubsat_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruhubsat_128B">; + +def int_hexagon_V6_vasruwuhsat : +Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruwuhsat">; + +def int_hexagon_V6_vasruwuhsat_128B : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruwuhsat_128B">; + +def int_hexagon_V6_vavgb : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgb">; + +def int_hexagon_V6_vavgb_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgb_128B">; + +def int_hexagon_V6_vavgbrnd : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgbrnd">; + +def int_hexagon_V6_vavgbrnd_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgbrnd_128B">; + +def int_hexagon_V6_vavguw : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguw">; + +def int_hexagon_V6_vavguw_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguw_128B">; + +def int_hexagon_V6_vavguwrnd : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguwrnd">; + +def int_hexagon_V6_vavguwrnd_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguwrnd_128B">; + +def int_hexagon_V6_vdd0 : +Hexagon_v32i32__Intrinsic<"HEXAGON_V6_vdd0">; + +def int_hexagon_V6_vdd0_128B : +Hexagon_v64i32__Intrinsic<"HEXAGON_V6_vdd0_128B">; + +def int_hexagon_V6_vgathermh : +Hexagon__ptri32i32v16i32_Intrinsic<"HEXAGON_V6_vgathermh", [IntrArgMemOnly]>; + +def int_hexagon_V6_vgathermh_128B : +Hexagon__ptri32i32v32i32_Intrinsic<"HEXAGON_V6_vgathermh_128B", [IntrArgMemOnly]>; + +def int_hexagon_V6_vgathermhq : +Hexagon_custom__ptrv64i1i32i32v16i32_Intrinsic<[IntrArgMemOnly]>; + +def int_hexagon_V6_vgathermhq_128B : +Hexagon_custom__ptrv128i1i32i32v32i32_Intrinsic_128B<[IntrArgMemOnly]>; + +def int_hexagon_V6_vgathermhw : +Hexagon__ptri32i32v32i32_Intrinsic<"HEXAGON_V6_vgathermhw", [IntrArgMemOnly]>; + +def int_hexagon_V6_vgathermhw_128B : +Hexagon__ptri32i32v64i32_Intrinsic<"HEXAGON_V6_vgathermhw_128B", [IntrArgMemOnly]>; + +def int_hexagon_V6_vgathermhwq : +Hexagon_custom__ptrv64i1i32i32v32i32_Intrinsic<[IntrArgMemOnly]>; + +def int_hexagon_V6_vgathermhwq_128B : +Hexagon_custom__ptrv128i1i32i32v64i32_Intrinsic_128B<[IntrArgMemOnly]>; + +def int_hexagon_V6_vgathermw : +Hexagon__ptri32i32v16i32_Intrinsic<"HEXAGON_V6_vgathermw", [IntrArgMemOnly]>; + +def int_hexagon_V6_vgathermw_128B : +Hexagon__ptri32i32v32i32_Intrinsic<"HEXAGON_V6_vgathermw_128B", [IntrArgMemOnly]>; + +def int_hexagon_V6_vgathermwq : +Hexagon_custom__ptrv64i1i32i32v16i32_Intrinsic<[IntrArgMemOnly]>; + +def int_hexagon_V6_vgathermwq_128B : +Hexagon_custom__ptrv128i1i32i32v32i32_Intrinsic_128B<[IntrArgMemOnly]>; + +def int_hexagon_V6_vlut4 : +Hexagon_v16i32_v16i32i64_Intrinsic<"HEXAGON_V6_vlut4">; + +def int_hexagon_V6_vlut4_128B : +Hexagon_v32i32_v32i32i64_Intrinsic<"HEXAGON_V6_vlut4_128B">; + def int_hexagon_V6_vmpabuu : Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpabuu">; @@ -5966,12 +6008,6 @@ Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpabuu_acc">; def int_hexagon_V6_vmpabuu_acc_128B : Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpabuu_acc_128B">; -def int_hexagon_V6_vmpyh_acc : -Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyh_acc">; - -def int_hexagon_V6_vmpyh_acc_128B : -Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyh_acc_128B">; - def int_hexagon_V6_vmpahhsat : Hexagon_v16i32_v16i32v16i32i64_Intrinsic<"HEXAGON_V6_vmpahhsat">; @@ -5990,11 +6026,11 @@ Hexagon_v16i32_v16i32v16i32i64_Intrinsic<"HEXAGON_V6_vmpsuhuhsat">; def int_hexagon_V6_vmpsuhuhsat_128B : Hexagon_v32i32_v32i32v32i32i64_Intrinsic<"HEXAGON_V6_vmpsuhuhsat_128B">; -def int_hexagon_V6_vlut4 : -Hexagon_v16i32_v16i32i64_Intrinsic<"HEXAGON_V6_vlut4">; +def int_hexagon_V6_vmpyh_acc : +Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyh_acc">; -def int_hexagon_V6_vlut4_128B : -Hexagon_v32i32_v32i32i64_Intrinsic<"HEXAGON_V6_vlut4_128B">; +def int_hexagon_V6_vmpyh_acc_128B : +Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyh_acc_128B">; def int_hexagon_V6_vmpyuhe : Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe">; @@ -6008,95 +6044,11 @@ Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe_acc">; def int_hexagon_V6_vmpyuhe_acc_128B : Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe_acc_128B">; -def int_hexagon_V6_vgathermw : -Hexagon__ptri32i32v16i32_Intrinsic<"HEXAGON_V6_vgathermw", [IntrArgMemOnly]>; +def int_hexagon_V6_vnavgb : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgb">; -def int_hexagon_V6_vgathermw_128B : -Hexagon__ptri32i32v32i32_Intrinsic<"HEXAGON_V6_vgathermw_128B", [IntrArgMemOnly]>; - -def int_hexagon_V6_vgathermh : -Hexagon__ptri32i32v16i32_Intrinsic<"HEXAGON_V6_vgathermh", [IntrArgMemOnly]>; - -def int_hexagon_V6_vgathermh_128B : -Hexagon__ptri32i32v32i32_Intrinsic<"HEXAGON_V6_vgathermh_128B", [IntrArgMemOnly]>; - -def int_hexagon_V6_vgathermhw : -Hexagon__ptri32i32v32i32_Intrinsic<"HEXAGON_V6_vgathermhw", [IntrArgMemOnly]>; - -def int_hexagon_V6_vgathermhw_128B : -Hexagon__ptri32i32v64i32_Intrinsic<"HEXAGON_V6_vgathermhw_128B", [IntrArgMemOnly]>; - -def int_hexagon_V6_vgathermwq : -Hexagon_custom__ptrv64i1i32i32v16i32_Intrinsic<[IntrArgMemOnly]>; - -def int_hexagon_V6_vgathermwq_128B : -Hexagon_custom__ptrv128i1i32i32v32i32_Intrinsic_128B<[IntrArgMemOnly]>; - -def int_hexagon_V6_vgathermhq : -Hexagon_custom__ptrv64i1i32i32v16i32_Intrinsic<[IntrArgMemOnly]>; - -def int_hexagon_V6_vgathermhq_128B : -Hexagon_custom__ptrv128i1i32i32v32i32_Intrinsic_128B<[IntrArgMemOnly]>; - -def int_hexagon_V6_vgathermhwq : -Hexagon_custom__ptrv64i1i32i32v32i32_Intrinsic<[IntrArgMemOnly]>; - -def int_hexagon_V6_vgathermhwq_128B : -Hexagon_custom__ptrv128i1i32i32v64i32_Intrinsic_128B<[IntrArgMemOnly]>; - -def int_hexagon_V6_vscattermw : -Hexagon__i32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vscattermw", [IntrWriteMem]>; - -def int_hexagon_V6_vscattermw_128B : -Hexagon__i32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vscattermw_128B", [IntrWriteMem]>; - -def int_hexagon_V6_vscattermh : -Hexagon__i32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vscattermh", [IntrWriteMem]>; - -def int_hexagon_V6_vscattermh_128B : -Hexagon__i32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vscattermh_128B", [IntrWriteMem]>; - -def int_hexagon_V6_vscattermw_add : -Hexagon__i32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vscattermw_add", [IntrWriteMem]>; - -def int_hexagon_V6_vscattermw_add_128B : -Hexagon__i32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vscattermw_add_128B", [IntrWriteMem]>; - -def int_hexagon_V6_vscattermh_add : -Hexagon__i32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vscattermh_add", [IntrWriteMem]>; - -def int_hexagon_V6_vscattermh_add_128B : -Hexagon__i32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vscattermh_add_128B", [IntrWriteMem]>; - -def int_hexagon_V6_vscattermwq : -Hexagon_custom__v64i1i32i32v16i32v16i32_Intrinsic<[IntrWriteMem]>; - -def int_hexagon_V6_vscattermwq_128B : -Hexagon_custom__v128i1i32i32v32i32v32i32_Intrinsic_128B<[IntrWriteMem]>; - -def int_hexagon_V6_vscattermhq : -Hexagon_custom__v64i1i32i32v16i32v16i32_Intrinsic<[IntrWriteMem]>; - -def int_hexagon_V6_vscattermhq_128B : -Hexagon_custom__v128i1i32i32v32i32v32i32_Intrinsic_128B<[IntrWriteMem]>; - -def int_hexagon_V6_vscattermhw : -Hexagon__i32i32v32i32v16i32_Intrinsic<"HEXAGON_V6_vscattermhw", [IntrWriteMem]>; - -def int_hexagon_V6_vscattermhw_128B : -Hexagon__i32i32v64i32v32i32_Intrinsic<"HEXAGON_V6_vscattermhw_128B", [IntrWriteMem]>; - -def int_hexagon_V6_vscattermhwq : -Hexagon_custom__v64i1i32i32v32i32v16i32_Intrinsic<[IntrWriteMem]>; - -def int_hexagon_V6_vscattermhwq_128B : -Hexagon_custom__v128i1i32i32v64i32v32i32_Intrinsic_128B<[IntrWriteMem]>; - -def int_hexagon_V6_vscattermhw_add : -Hexagon__i32i32v32i32v16i32_Intrinsic<"HEXAGON_V6_vscattermhw_add", [IntrWriteMem]>; - -def int_hexagon_V6_vscattermhw_add_128B : -Hexagon__i32i32v64i32v32i32_Intrinsic<"HEXAGON_V6_vscattermhw_add_128B", [IntrWriteMem]>; +def int_hexagon_V6_vnavgb_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgb_128B">; def int_hexagon_V6_vprefixqb : Hexagon_custom_v16i32_v64i1_Intrinsic; @@ -6116,29 +6068,109 @@ Hexagon_custom_v16i32_v64i1_Intrinsic; def int_hexagon_V6_vprefixqw_128B : Hexagon_custom_v32i32_v128i1_Intrinsic_128B; +def int_hexagon_V6_vscattermh : +Hexagon__i32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vscattermh", [IntrWriteMem]>; + +def int_hexagon_V6_vscattermh_128B : +Hexagon__i32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vscattermh_128B", [IntrWriteMem]>; + +def int_hexagon_V6_vscattermh_add : +Hexagon__i32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vscattermh_add", [IntrWriteMem]>; + +def int_hexagon_V6_vscattermh_add_128B : +Hexagon__i32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vscattermh_add_128B", [IntrWriteMem]>; + +def int_hexagon_V6_vscattermhq : +Hexagon_custom__v64i1i32i32v16i32v16i32_Intrinsic<[IntrWriteMem]>; + +def int_hexagon_V6_vscattermhq_128B : +Hexagon_custom__v128i1i32i32v32i32v32i32_Intrinsic_128B<[IntrWriteMem]>; + +def int_hexagon_V6_vscattermhw : +Hexagon__i32i32v32i32v16i32_Intrinsic<"HEXAGON_V6_vscattermhw", [IntrWriteMem]>; + +def int_hexagon_V6_vscattermhw_128B : +Hexagon__i32i32v64i32v32i32_Intrinsic<"HEXAGON_V6_vscattermhw_128B", [IntrWriteMem]>; + +def int_hexagon_V6_vscattermhw_add : +Hexagon__i32i32v32i32v16i32_Intrinsic<"HEXAGON_V6_vscattermhw_add", [IntrWriteMem]>; + +def int_hexagon_V6_vscattermhw_add_128B : +Hexagon__i32i32v64i32v32i32_Intrinsic<"HEXAGON_V6_vscattermhw_add_128B", [IntrWriteMem]>; + +def int_hexagon_V6_vscattermhwq : +Hexagon_custom__v64i1i32i32v32i32v16i32_Intrinsic<[IntrWriteMem]>; + +def int_hexagon_V6_vscattermhwq_128B : +Hexagon_custom__v128i1i32i32v64i32v32i32_Intrinsic_128B<[IntrWriteMem]>; + +def int_hexagon_V6_vscattermw : +Hexagon__i32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vscattermw", [IntrWriteMem]>; + +def int_hexagon_V6_vscattermw_128B : +Hexagon__i32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vscattermw_128B", [IntrWriteMem]>; + +def int_hexagon_V6_vscattermw_add : +Hexagon__i32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vscattermw_add", [IntrWriteMem]>; + +def int_hexagon_V6_vscattermw_add_128B : +Hexagon__i32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vscattermw_add_128B", [IntrWriteMem]>; + +def int_hexagon_V6_vscattermwq : +Hexagon_custom__v64i1i32i32v16i32v16i32_Intrinsic<[IntrWriteMem]>; + +def int_hexagon_V6_vscattermwq_128B : +Hexagon_custom__v128i1i32i32v32i32v32i32_Intrinsic_128B<[IntrWriteMem]>; + // V66 HVX Instructions. -def int_hexagon_V6_vrotr : -Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrotr">; - -def int_hexagon_V6_vrotr_128B : -Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrotr_128B">; - -def int_hexagon_V6_vasr_into : -Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vasr_into">; - -def int_hexagon_V6_vasr_into_128B : -Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vasr_into_128B">; - def int_hexagon_V6_vaddcarrysat : Hexagon_custom_v16i32_v16i32v16i32v64i1_Intrinsic; def int_hexagon_V6_vaddcarrysat_128B : Hexagon_custom_v32i32_v32i32v32i32v128i1_Intrinsic_128B; +def int_hexagon_V6_vasr_into : +Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vasr_into">; + +def int_hexagon_V6_vasr_into_128B : +Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vasr_into_128B">; + +def int_hexagon_V6_vrotr : +Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrotr">; + +def int_hexagon_V6_vrotr_128B : +Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrotr_128B">; + def int_hexagon_V6_vsatdw : Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsatdw">; def int_hexagon_V6_vsatdw_128B : Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsatdw_128B">; +// V68 HVX Instructions. + +def int_hexagon_V6_v6mpyhubs10 : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_v6mpyhubs10", [IntrNoMem, ImmArg>]>; + +def int_hexagon_V6_v6mpyhubs10_128B : +Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_v6mpyhubs10_128B", [IntrNoMem, ImmArg>]>; + +def int_hexagon_V6_v6mpyhubs10_vxx : +Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_v6mpyhubs10_vxx", [IntrNoMem, ImmArg>]>; + +def int_hexagon_V6_v6mpyhubs10_vxx_128B : +Hexagon_v64i32_v64i32v64i32v64i32i32_Intrinsic<"HEXAGON_V6_v6mpyhubs10_vxx_128B", [IntrNoMem, ImmArg>]>; + +def int_hexagon_V6_v6mpyvubs10 : +Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_v6mpyvubs10", [IntrNoMem, ImmArg>]>; + +def int_hexagon_V6_v6mpyvubs10_128B : +Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_v6mpyvubs10_128B", [IntrNoMem, ImmArg>]>; + +def int_hexagon_V6_v6mpyvubs10_vxx : +Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_v6mpyvubs10_vxx", [IntrNoMem, ImmArg>]>; + +def int_hexagon_V6_v6mpyvubs10_vxx_128B : +Hexagon_v64i32_v64i32v64i32v64i32i32_Intrinsic<"HEXAGON_V6_v6mpyvubs10_vxx_128B", [IntrNoMem, ImmArg>]>; + diff --git a/lib/Target/Hexagon/Hexagon.td b/lib/Target/Hexagon/Hexagon.td index 2fadb0b5ddc..7518fd774a4 100644 --- a/lib/Target/Hexagon/Hexagon.td +++ b/lib/Target/Hexagon/Hexagon.td @@ -48,7 +48,10 @@ def ExtensionHVXV66: SubtargetFeature<"hvxv66", "HexagonHVXVersion", def ExtensionHVXV67: SubtargetFeature<"hvxv67", "HexagonHVXVersion", "Hexagon::ArchEnum::V67", "Hexagon HVX instructions", [ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, ExtensionHVXV66]>; - +def ExtensionHVXV68: SubtargetFeature<"hvxv68", "HexagonHVXVersion", + "Hexagon::ArchEnum::V68", "Hexagon HVX instructions", + [ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, ExtensionHVXV66, + ExtensionHVXV67]>; def ExtensionHVX64B: SubtargetFeature<"hvx-length64b", "UseHVX64BOps", "true", "Hexagon HVX 64B instructions", [ExtensionHVX]>; @@ -107,6 +110,8 @@ def UseHVXV66 : Predicate<"HST->useHVXV66Ops()">, AssemblerPredicate<(all_of ExtensionHVXV66)>; def UseHVXV67 : Predicate<"HST->useHVXV67Ops()">, AssemblerPredicate<(all_of ExtensionHVXV67)>; +def UseHVXV68 : Predicate<"HST->useHVXV68Ops()">, + AssemblerPredicate<(all_of ExtensionHVXV68)>; def UseAudio : Predicate<"HST->useAudioOps()">, AssemblerPredicate<(all_of ExtensionAudio)>; def UseZReg : Predicate<"HST->useZRegOps()">, @@ -394,6 +399,11 @@ def : Proc<"hexagonv67", HexagonModelV67, [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, ArchV67, FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops, FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>; +def : Proc<"hexagonv68", HexagonModelV68, + [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66, ArchV67, + ArchV68, + FeatureCompound, FeatureDuplex, FeatureMemNoShuf, FeatureMemops, + FeatureNVJ, FeatureNVS, FeaturePackets, FeatureSmallData]>; // Need to update the correct features for tiny core. // Disable NewValueJumps since the packetizer is unable to handle a packet with // a new value jump and another SLOT0 instruction. diff --git a/lib/Target/Hexagon/HexagonDepArch.h b/lib/Target/Hexagon/HexagonDepArch.h index 45b4cf04244..7a43a4440b2 100644 --- a/lib/Target/Hexagon/HexagonDepArch.h +++ b/lib/Target/Hexagon/HexagonDepArch.h @@ -14,35 +14,76 @@ #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/StringRef.h" +#include "llvm/BinaryFormat/ELF.h" + #include +#include namespace llvm { namespace Hexagon { -enum class ArchEnum { NoArch, Generic, V5, V55, V60, V62, V65, V66, V67 }; +enum class ArchEnum { NoArch, Generic, V5, V55, V60, V62, V65, V66, V67, V68 }; -static constexpr unsigned ArchValsNumArray[] = {5, 55, 60, 62, 65, 66, 67}; +static constexpr unsigned ArchValsNumArray[] = {5, 55, 60, 62, 65, 66, 67, 68}; static constexpr ArrayRef ArchValsNum(ArchValsNumArray); -static constexpr StringLiteral ArchValsTextArray[] = { "v5", "v55", "v60", "v62", "v65", "v66", "v67" }; +static constexpr StringLiteral ArchValsTextArray[] = { "v5", "v55", "v60", "v62", "v65", "v66", "v67", "v68" }; static constexpr ArrayRef ArchValsText(ArchValsTextArray); -static constexpr StringLiteral CpuValsTextArray[] = { "hexagonv5", "hexagonv55", "hexagonv60", "hexagonv62", "hexagonv65", "hexagonv66", "hexagonv67", "hexagonv67t" }; +static constexpr StringLiteral CpuValsTextArray[] = { "hexagonv5", "hexagonv55", "hexagonv60", "hexagonv62", "hexagonv65", "hexagonv66", "hexagonv67", "hexagonv67t", "hexagonv68" }; static constexpr ArrayRef CpuValsText(CpuValsTextArray); -static constexpr StringLiteral CpuNickTextArray[] = { "v5", "v55", "v60", "v62", "v65", "v66", "v67", "v67t" }; +static constexpr StringLiteral CpuNickTextArray[] = { "v5", "v55", "v60", "v62", "v65", "v66", "v67", "v67t", "v68" }; static constexpr ArrayRef CpuNickText(CpuNickTextArray); static const std::map CpuTable{ - {"generic", Hexagon::ArchEnum::V60}, - {"hexagonv5", Hexagon::ArchEnum::V5}, - {"hexagonv55", Hexagon::ArchEnum::V55}, - {"hexagonv60", Hexagon::ArchEnum::V60}, - {"hexagonv62", Hexagon::ArchEnum::V62}, - {"hexagonv65", Hexagon::ArchEnum::V65}, - {"hexagonv66", Hexagon::ArchEnum::V66}, - {"hexagonv67", Hexagon::ArchEnum::V67}, - {"hexagonv67t", Hexagon::ArchEnum::V67}, + {"generic", Hexagon::ArchEnum::V5}, + {"hexagonv5", Hexagon::ArchEnum::V5}, + {"hexagonv55", Hexagon::ArchEnum::V55}, + {"hexagonv60", Hexagon::ArchEnum::V60}, + {"hexagonv62", Hexagon::ArchEnum::V62}, + {"hexagonv65", Hexagon::ArchEnum::V65}, + {"hexagonv66", Hexagon::ArchEnum::V66}, + {"hexagonv67", Hexagon::ArchEnum::V67}, + {"hexagonv67t", Hexagon::ArchEnum::V67}, + {"hexagonv68", Hexagon::ArchEnum::V68}, }; + +static const std::map ElfFlagsByCpuStr = { + {"generic", llvm::ELF::EF_HEXAGON_MACH_V5}, + {"hexagonv5", llvm::ELF::EF_HEXAGON_MACH_V5}, + {"hexagonv55", llvm::ELF::EF_HEXAGON_MACH_V55}, + {"hexagonv60", llvm::ELF::EF_HEXAGON_MACH_V60}, + {"hexagonv62", llvm::ELF::EF_HEXAGON_MACH_V62}, + {"hexagonv65", llvm::ELF::EF_HEXAGON_MACH_V65}, + {"hexagonv66", llvm::ELF::EF_HEXAGON_MACH_V66}, + {"hexagonv67", llvm::ELF::EF_HEXAGON_MACH_V67}, + {"hexagonv67t", llvm::ELF::EF_HEXAGON_MACH_V67T}, + {"hexagonv68", llvm::ELF::EF_HEXAGON_MACH_V68}, +}; +static const std::map ElfArchByMachFlags = { + {llvm::ELF::EF_HEXAGON_MACH_V5, "V5"}, + {llvm::ELF::EF_HEXAGON_MACH_V55, "V55"}, + {llvm::ELF::EF_HEXAGON_MACH_V60, "V60"}, + {llvm::ELF::EF_HEXAGON_MACH_V62, "V62"}, + {llvm::ELF::EF_HEXAGON_MACH_V65, "V65"}, + {llvm::ELF::EF_HEXAGON_MACH_V66, "V66"}, + {llvm::ELF::EF_HEXAGON_MACH_V67, "V67"}, + {llvm::ELF::EF_HEXAGON_MACH_V67T, "V67T"}, + {llvm::ELF::EF_HEXAGON_MACH_V68, "V68"}, +}; +static const std::map ElfCpuByMachFlags = { + {llvm::ELF::EF_HEXAGON_MACH_V5, "hexagonv5"}, + {llvm::ELF::EF_HEXAGON_MACH_V55, "hexagonv55"}, + {llvm::ELF::EF_HEXAGON_MACH_V60, "hexagonv60"}, + {llvm::ELF::EF_HEXAGON_MACH_V62, "hexagonv62"}, + {llvm::ELF::EF_HEXAGON_MACH_V65, "hexagonv65"}, + {llvm::ELF::EF_HEXAGON_MACH_V66, "hexagonv66"}, + {llvm::ELF::EF_HEXAGON_MACH_V67, "hexagonv67"}, + {llvm::ELF::EF_HEXAGON_MACH_V67T, "hexagonv67t"}, + {llvm::ELF::EF_HEXAGON_MACH_V68, "hexagonv68"}, +}; + } // namespace Hexagon } // namespace llvm; -#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPARCH_H + +#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPARCH_H diff --git a/lib/Target/Hexagon/HexagonDepArch.td b/lib/Target/Hexagon/HexagonDepArch.td index 9374055eae7..e743a291f1e 100644 --- a/lib/Target/Hexagon/HexagonDepArch.td +++ b/lib/Target/Hexagon/HexagonDepArch.td @@ -22,3 +22,5 @@ def ArchV66: SubtargetFeature<"v66", "HexagonArchVersion", "Hexagon::ArchEnum::V def HasV66 : Predicate<"HST->hasV66Ops()">, AssemblerPredicate<(all_of ArchV66)>; def ArchV67: SubtargetFeature<"v67", "HexagonArchVersion", "Hexagon::ArchEnum::V67", "Enable Hexagon V67 architecture">; def HasV67 : Predicate<"HST->hasV67Ops()">, AssemblerPredicate<(all_of ArchV67)>; +def ArchV68: SubtargetFeature<"v68", "HexagonArchVersion", "Hexagon::ArchEnum::V68", "Enable Hexagon V68 architecture">; +def HasV68 : Predicate<"HST->hasV68Ops()">, AssemblerPredicate<(all_of ArchV68)>; diff --git a/lib/Target/Hexagon/HexagonDepDecoders.inc b/lib/Target/Hexagon/HexagonDepDecoders.inc index ce7aa02e3e0..40f6e14aed1 100644 --- a/lib/Target/Hexagon/HexagonDepDecoders.inc +++ b/lib/Target/Hexagon/HexagonDepDecoders.inc @@ -8,21 +8,14 @@ // Automatically generated file, do not edit! //===----------------------------------------------------------------------===// -// clang-format off - #if defined(__clang__) #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wunused-function" #endif -static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp, +static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const void *Decoder) { - signedDecoder<8>(MI, tmp, Decoder); - return MCDisassembler::Success; -} -static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t, const void *Decoder) { - signedDecoder<4>(MI, tmp, Decoder); + signedDecoder<6>(MI, tmp, Decoder); return MCDisassembler::Success; } static DecodeStatus s31_1ImmDecoder(MCInst &MI, unsigned tmp, @@ -30,44 +23,49 @@ static DecodeStatus s31_1ImmDecoder(MCInst &MI, unsigned tmp, signedDecoder<12>(MI, tmp, Decoder); return MCDisassembler::Success; } -static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t, const void *Decoder) { - signedDecoder<5>(MI, tmp, Decoder); - return MCDisassembler::Success; -} static DecodeStatus s30_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const void *Decoder) { signedDecoder<13>(MI, tmp, Decoder); return MCDisassembler::Success; } -static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t, const void *Decoder) { - signedDecoder<6>(MI, tmp, Decoder); - return MCDisassembler::Success; -} static DecodeStatus s29_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const void *Decoder) { signedDecoder<14>(MI, tmp, Decoder); return MCDisassembler::Success; } +static DecodeStatus s3_0ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t, const void *Decoder) { + signedDecoder<3>(MI, tmp, Decoder); + return MCDisassembler::Success; +} +static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t, const void *Decoder) { + signedDecoder<4>(MI, tmp, Decoder); + return MCDisassembler::Success; +} +static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t, const void *Decoder) { + signedDecoder<5>(MI, tmp, Decoder); + return MCDisassembler::Success; +} +static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t, const void *Decoder) { + signedDecoder<6>(MI, tmp, Decoder); + return MCDisassembler::Success; +} static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const void *Decoder) { signedDecoder<7>(MI, tmp, Decoder); return MCDisassembler::Success; } -static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t, const void *Decoder) { - signedDecoder<6>(MI, tmp, Decoder); - return MCDisassembler::Success; -} static DecodeStatus s6_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const void *Decoder) { signedDecoder<9>(MI, tmp, Decoder); return MCDisassembler::Success; } -static DecodeStatus s3_0ImmDecoder(MCInst &MI, unsigned tmp, +static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const void *Decoder) { - signedDecoder<3>(MI, tmp, Decoder); + signedDecoder<8>(MI, tmp, Decoder); return MCDisassembler::Success; } @@ -75,4 +73,3 @@ static DecodeStatus s3_0ImmDecoder(MCInst &MI, unsigned tmp, #pragma clang diagnostic pop #endif -// clang-format on diff --git a/lib/Target/Hexagon/HexagonDepIICHVX.td b/lib/Target/Hexagon/HexagonDepIICHVX.td index 1547e8f769b..a1db3ae7239 100644 --- a/lib/Target/Hexagon/HexagonDepIICHVX.td +++ b/lib/Target/Hexagon/HexagonDepIICHVX.td @@ -9,8 +9,6 @@ //===----------------------------------------------------------------------===// def tc_04da405a : InstrItinClass; -def tc_05058f6f : InstrItinClass; -def tc_05ac6f98 : InstrItinClass; def tc_05ca8cfd : InstrItinClass; def tc_08a4f1b6 : InstrItinClass; def tc_0b04c6c7 : InstrItinClass; @@ -25,6 +23,7 @@ def tc_1ba8a0cd : InstrItinClass; def tc_20a4bbec : InstrItinClass; def tc_257f6f7c : InstrItinClass; def tc_26a377fe : InstrItinClass; +def tc_2b4c548e : InstrItinClass; def tc_2c745bb8 : InstrItinClass; def tc_2d4051cd : InstrItinClass; def tc_2e8f5f6e : InstrItinClass; @@ -53,12 +52,14 @@ def tc_660769f1 : InstrItinClass; def tc_663c80a7 : InstrItinClass; def tc_6942b6e0 : InstrItinClass; def tc_6e7fa133 : InstrItinClass; +def tc_7095ecba : InstrItinClass; def tc_71646d06 : InstrItinClass; def tc_7177e272 : InstrItinClass; def tc_718b5c53 : InstrItinClass; def tc_7273323b : InstrItinClass; def tc_7417e785 : InstrItinClass; def tc_767c4e9d : InstrItinClass; +def tc_7d68d5c2 : InstrItinClass; def tc_7e6a3e89 : InstrItinClass; def tc_8772086c : InstrItinClass; def tc_87adc037 : InstrItinClass; @@ -70,6 +71,8 @@ def tc_9d1dc972 : InstrItinClass; def tc_9f363d21 : InstrItinClass; def tc_a02a10a8 : InstrItinClass; def tc_a0dbea28 : InstrItinClass; +def tc_a28f32b5 : InstrItinClass; +def tc_a69eeee1 : InstrItinClass; def tc_a7e6707d : InstrItinClass; def tc_ab23f776 : InstrItinClass; def tc_abe8c3b2 : InstrItinClass; @@ -79,6 +82,7 @@ def tc_b091f1c6 : InstrItinClass; def tc_b28e51aa : InstrItinClass; def tc_b4416217 : InstrItinClass; def tc_b9db8205 : InstrItinClass; +def tc_bb599486 : InstrItinClass; def tc_c0749f3c : InstrItinClass; def tc_c127de3a : InstrItinClass; def tc_c4edf264 : InstrItinClass; @@ -94,11 +98,9 @@ def tc_e35c1e93 : InstrItinClass; def tc_e3f68a46 : InstrItinClass; def tc_e675c45a : InstrItinClass; def tc_e699ae41 : InstrItinClass; -def tc_e8797b98 : InstrItinClass; def tc_e99d4c2e : InstrItinClass; def tc_f1de44ef : InstrItinClass; def tc_f21e8abb : InstrItinClass; -def tc_fd7610da : InstrItinClass; class DepHVXItinV55 { list DepHVXItinV55_list = [ @@ -107,18 +109,6 @@ class DepHVXItinV55 { InstrStage<1, [CVI_XLSHF]>], [9, 5], [HVX_FWD, HVX_FWD]>, - InstrItinData , - InstrStage<1, [CVI_LD], 0>, - InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7], - [Hex_FWD, Hex_FWD, HVX_FWD]>, - - InstrItinData , - InstrStage<1, [CVI_LD], 0>, - InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7], - [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, - InstrItinData , InstrStage<1, [CVI_SHIFT]>], [9, 5, 5], @@ -194,6 +184,11 @@ class DepHVXItinV55 { InstrStage<1, [CVI_ALL_NOMEM]>], [9, 3, 5, 2], [HVX_FWD, Hex_FWD, HVX_FWD, Hex_FWD]>, + InstrItinData , + InstrStage<1, [CVI_MPY01]>], [9, 5, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + InstrItinData , InstrStage<1, [CVI_XLSHF]>], [9, 7, 5], @@ -341,6 +336,12 @@ class DepHVXItinV55 { InstrStage<1, [CVI_XLANE]>], [9, 5, 2], [HVX_FWD, HVX_FWD, Hex_FWD]>, + InstrItinData , + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7], + [Hex_FWD, Hex_FWD, HVX_FWD]>, + InstrItinData , InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7, 7, 7], @@ -372,6 +373,12 @@ class DepHVXItinV55 { InstrStage<1, [CVI_ALL]>], [3, 2], [HVX_FWD, Hex_FWD]>, + InstrItinData , + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7], + [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + InstrItinData , InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 9, 7, 7, 7], @@ -430,6 +437,18 @@ class DepHVXItinV55 { InstrStage<1, [CVI_ZW]>], [3, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData , + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7], + [Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7], + [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + InstrItinData , InstrStage<1, [SLOT1], 0>, @@ -478,6 +497,11 @@ class DepHVXItinV55 { InstrStage<1, [CVI_LD]>], [9, 3, 2, 1, 2], [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData , + InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + InstrItinData , InstrStage<1, [CVI_LD], 0>, @@ -560,12 +584,6 @@ class DepHVXItinV55 { InstrStage<1, [CVI_ZW]>], [1, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData , - InstrStage<1, [CVI_LD], 0>, - InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7], - [Hex_FWD, Hex_FWD, HVX_FWD]>, - InstrItinData , InstrStage<1, [CVI_ST]>], [3, 2, 1, 2, 5], @@ -581,13 +599,7 @@ class DepHVXItinV55 { InstrStage<1, [SLOT1], 0>, InstrStage<1, [CVI_ST], 0>, InstrStage<1, [CVI_XLANE]>], [1, 2, 5], - [Hex_FWD, Hex_FWD, HVX_FWD]>, - - InstrItinData , - InstrStage<1, [CVI_LD], 0>, - InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7], - [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]> + [Hex_FWD, Hex_FWD, HVX_FWD]> ]; } @@ -598,18 +610,6 @@ class DepHVXItinV60 { InstrStage<1, [CVI_XLSHF]>], [9, 5], [HVX_FWD, HVX_FWD]>, - InstrItinData , - InstrStage<1, [CVI_LD], 0>, - InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7], - [Hex_FWD, Hex_FWD, HVX_FWD]>, - - InstrItinData , - InstrStage<1, [CVI_LD], 0>, - InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7], - [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, - InstrItinData , InstrStage<1, [CVI_SHIFT]>], [9, 5, 5], @@ -685,6 +685,11 @@ class DepHVXItinV60 { InstrStage<1, [CVI_ALL_NOMEM]>], [9, 3, 5, 2], [HVX_FWD, Hex_FWD, HVX_FWD, Hex_FWD]>, + InstrItinData , + InstrStage<1, [CVI_MPY01]>], [9, 5, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + InstrItinData , InstrStage<1, [CVI_XLSHF]>], [9, 7, 5], @@ -832,6 +837,12 @@ class DepHVXItinV60 { InstrStage<1, [CVI_XLANE]>], [9, 5, 2], [HVX_FWD, HVX_FWD, Hex_FWD]>, + InstrItinData , + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7], + [Hex_FWD, Hex_FWD, HVX_FWD]>, + InstrItinData , InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7, 7, 7], @@ -863,6 +874,12 @@ class DepHVXItinV60 { InstrStage<1, [CVI_ALL]>], [3, 2], [HVX_FWD, Hex_FWD]>, + InstrItinData , + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7], + [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + InstrItinData , InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 9, 7, 7, 7], @@ -921,6 +938,18 @@ class DepHVXItinV60 { InstrStage<1, [CVI_ZW]>], [3, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData , + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7], + [Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7], + [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + InstrItinData , InstrStage<1, [SLOT1], 0>, @@ -969,6 +998,11 @@ class DepHVXItinV60 { InstrStage<1, [CVI_LD]>], [9, 3, 2, 1, 2], [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData , + InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + InstrItinData , InstrStage<1, [CVI_LD], 0>, @@ -1051,12 +1085,6 @@ class DepHVXItinV60 { InstrStage<1, [CVI_ZW]>], [1, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData , - InstrStage<1, [CVI_LD], 0>, - InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7], - [Hex_FWD, Hex_FWD, HVX_FWD]>, - InstrItinData , InstrStage<1, [CVI_ST]>], [3, 2, 1, 2, 5], @@ -1072,13 +1100,7 @@ class DepHVXItinV60 { InstrStage<1, [SLOT1], 0>, InstrStage<1, [CVI_ST], 0>, InstrStage<1, [CVI_XLANE]>], [1, 2, 5], - [Hex_FWD, Hex_FWD, HVX_FWD]>, - - InstrItinData , - InstrStage<1, [CVI_LD], 0>, - InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7], - [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]> + [Hex_FWD, Hex_FWD, HVX_FWD]> ]; } @@ -1089,18 +1111,6 @@ class DepHVXItinV62 { InstrStage<1, [CVI_XLSHF]>], [9, 5], [HVX_FWD, HVX_FWD]>, - InstrItinData , - InstrStage<1, [CVI_LD], 0>, - InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7], - [Hex_FWD, Hex_FWD, HVX_FWD]>, - - InstrItinData , - InstrStage<1, [CVI_LD], 0>, - InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7], - [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, - InstrItinData , InstrStage<1, [CVI_SHIFT]>], [9, 5, 5], @@ -1176,6 +1186,11 @@ class DepHVXItinV62 { InstrStage<1, [CVI_ALL_NOMEM]>], [9, 3, 5, 2], [HVX_FWD, Hex_FWD, HVX_FWD, Hex_FWD]>, + InstrItinData , + InstrStage<1, [CVI_MPY01]>], [9, 5, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + InstrItinData , InstrStage<1, [CVI_XLSHF]>], [9, 7, 5], @@ -1323,6 +1338,12 @@ class DepHVXItinV62 { InstrStage<1, [CVI_XLANE]>], [9, 5, 2], [HVX_FWD, HVX_FWD, Hex_FWD]>, + InstrItinData , + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7], + [Hex_FWD, Hex_FWD, HVX_FWD]>, + InstrItinData , InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7, 7, 7], @@ -1354,6 +1375,12 @@ class DepHVXItinV62 { InstrStage<1, [CVI_ALL]>], [3, 2], [HVX_FWD, Hex_FWD]>, + InstrItinData , + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7], + [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + InstrItinData , InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 9, 7, 7, 7], @@ -1412,6 +1439,18 @@ class DepHVXItinV62 { InstrStage<1, [CVI_ZW]>], [3, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData , + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7], + [Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7], + [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + InstrItinData , InstrStage<1, [SLOT1], 0>, @@ -1460,6 +1499,11 @@ class DepHVXItinV62 { InstrStage<1, [CVI_LD]>], [9, 3, 2, 1, 2], [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData , + InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + InstrItinData , InstrStage<1, [CVI_LD], 0>, @@ -1542,12 +1586,6 @@ class DepHVXItinV62 { InstrStage<1, [CVI_ZW]>], [1, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData , - InstrStage<1, [CVI_LD], 0>, - InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7], - [Hex_FWD, Hex_FWD, HVX_FWD]>, - InstrItinData , InstrStage<1, [CVI_ST]>], [3, 2, 1, 2, 5], @@ -1563,13 +1601,7 @@ class DepHVXItinV62 { InstrStage<1, [SLOT1], 0>, InstrStage<1, [CVI_ST], 0>, InstrStage<1, [CVI_XLANE]>], [1, 2, 5], - [Hex_FWD, Hex_FWD, HVX_FWD]>, - - InstrItinData , - InstrStage<1, [CVI_LD], 0>, - InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7], - [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]> + [Hex_FWD, Hex_FWD, HVX_FWD]> ]; } @@ -1580,18 +1612,6 @@ class DepHVXItinV65 { InstrStage<1, [CVI_XLSHF]>], [9, 5], [HVX_FWD, HVX_FWD]>, - InstrItinData , - InstrStage<1, [CVI_LD], 0>, - InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7], - [Hex_FWD, Hex_FWD, HVX_FWD]>, - - InstrItinData , - InstrStage<1, [CVI_LD], 0>, - InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7], - [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, - InstrItinData , InstrStage<1, [CVI_SHIFT]>], [9, 5, 5], @@ -1667,6 +1687,11 @@ class DepHVXItinV65 { InstrStage<1, [CVI_ALL_NOMEM]>], [9, 3, 5, 2], [HVX_FWD, Hex_FWD, HVX_FWD, Hex_FWD]>, + InstrItinData , + InstrStage<1, [CVI_MPY01]>], [9, 5, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + InstrItinData , InstrStage<1, [CVI_XLSHF]>], [9, 7, 5], @@ -1814,6 +1839,12 @@ class DepHVXItinV65 { InstrStage<1, [CVI_XLANE]>], [9, 5, 2], [HVX_FWD, HVX_FWD, Hex_FWD]>, + InstrItinData , + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7], + [Hex_FWD, Hex_FWD, HVX_FWD]>, + InstrItinData , InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7, 7, 7], @@ -1845,6 +1876,12 @@ class DepHVXItinV65 { InstrStage<1, [CVI_ALL]>], [3, 2], [HVX_FWD, Hex_FWD]>, + InstrItinData , + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7], + [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + InstrItinData , InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 9, 7, 7, 7], @@ -1903,6 +1940,18 @@ class DepHVXItinV65 { InstrStage<1, [CVI_ZW]>], [3, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData , + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7], + [Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7], + [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + InstrItinData , InstrStage<1, [SLOT1], 0>, @@ -1951,6 +2000,11 @@ class DepHVXItinV65 { InstrStage<1, [CVI_LD]>], [9, 3, 2, 1, 2], [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData , + InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + InstrItinData , InstrStage<1, [CVI_LD], 0>, @@ -2033,12 +2087,6 @@ class DepHVXItinV65 { InstrStage<1, [CVI_ZW]>], [1, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData , - InstrStage<1, [CVI_LD], 0>, - InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7], - [Hex_FWD, Hex_FWD, HVX_FWD]>, - InstrItinData , InstrStage<1, [CVI_ST]>], [3, 2, 1, 2, 5], @@ -2054,13 +2102,7 @@ class DepHVXItinV65 { InstrStage<1, [SLOT1], 0>, InstrStage<1, [CVI_ST], 0>, InstrStage<1, [CVI_XLANE]>], [1, 2, 5], - [Hex_FWD, Hex_FWD, HVX_FWD]>, - - InstrItinData , - InstrStage<1, [CVI_LD], 0>, - InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7], - [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]> + [Hex_FWD, Hex_FWD, HVX_FWD]> ]; } @@ -2071,18 +2113,6 @@ class DepHVXItinV66 { InstrStage<1, [CVI_XLSHF]>], [9, 5], [HVX_FWD, HVX_FWD]>, - InstrItinData , - InstrStage<1, [CVI_LD], 0>, - InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7], - [Hex_FWD, Hex_FWD, HVX_FWD]>, - - InstrItinData , - InstrStage<1, [CVI_LD], 0>, - InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7], - [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, - InstrItinData , InstrStage<1, [CVI_SHIFT]>], [9, 5, 5], @@ -2158,6 +2188,11 @@ class DepHVXItinV66 { InstrStage<1, [CVI_ALL_NOMEM]>], [9, 3, 5, 2], [HVX_FWD, Hex_FWD, HVX_FWD, Hex_FWD]>, + InstrItinData , + InstrStage<1, [CVI_MPY01]>], [9, 5, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + InstrItinData , InstrStage<1, [CVI_XLSHF]>], [9, 7, 5], @@ -2305,6 +2340,12 @@ class DepHVXItinV66 { InstrStage<1, [CVI_XLANE]>], [9, 5, 2], [HVX_FWD, HVX_FWD, Hex_FWD]>, + InstrItinData , + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7], + [Hex_FWD, Hex_FWD, HVX_FWD]>, + InstrItinData , InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7, 7, 7], @@ -2336,6 +2377,12 @@ class DepHVXItinV66 { InstrStage<1, [CVI_ALL]>], [3, 2], [HVX_FWD, Hex_FWD]>, + InstrItinData , + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7], + [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + InstrItinData , InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 9, 7, 7, 7], @@ -2394,6 +2441,18 @@ class DepHVXItinV66 { InstrStage<1, [CVI_ZW]>], [3, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData , + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7], + [Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7], + [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + InstrItinData , InstrStage<1, [SLOT1], 0>, @@ -2442,6 +2501,11 @@ class DepHVXItinV66 { InstrStage<1, [CVI_LD]>], [9, 3, 2, 1, 2], [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData , + InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + InstrItinData , InstrStage<1, [CVI_LD], 0>, @@ -2524,12 +2588,6 @@ class DepHVXItinV66 { InstrStage<1, [CVI_ZW]>], [1, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData , - InstrStage<1, [CVI_LD], 0>, - InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7], - [Hex_FWD, Hex_FWD, HVX_FWD]>, - InstrItinData , InstrStage<1, [CVI_ST]>], [3, 2, 1, 2, 5], @@ -2545,13 +2603,7 @@ class DepHVXItinV66 { InstrStage<1, [SLOT1], 0>, InstrStage<1, [CVI_ST], 0>, InstrStage<1, [CVI_XLANE]>], [1, 2, 5], - [Hex_FWD, Hex_FWD, HVX_FWD]>, - - InstrItinData , - InstrStage<1, [CVI_LD], 0>, - InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7], - [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]> + [Hex_FWD, Hex_FWD, HVX_FWD]> ]; } @@ -2562,18 +2614,6 @@ class DepHVXItinV67 { InstrStage<1, [CVI_XLSHF]>], [9, 5], [HVX_FWD, HVX_FWD]>, - InstrItinData , - InstrStage<1, [CVI_LD], 0>, - InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7], - [Hex_FWD, Hex_FWD, HVX_FWD]>, - - InstrItinData , - InstrStage<1, [CVI_LD], 0>, - InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7], - [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, - InstrItinData , InstrStage<1, [CVI_SHIFT]>], [9, 5, 5], @@ -2649,6 +2689,11 @@ class DepHVXItinV67 { InstrStage<1, [CVI_ALL_NOMEM]>], [9, 3, 5, 2], [HVX_FWD, Hex_FWD, HVX_FWD, Hex_FWD]>, + InstrItinData , + InstrStage<1, [CVI_MPY01]>], [9, 5, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + InstrItinData , InstrStage<1, [CVI_XLSHF]>], [9, 7, 5], @@ -2796,6 +2841,12 @@ class DepHVXItinV67 { InstrStage<1, [CVI_XLANE]>], [9, 5, 2], [HVX_FWD, HVX_FWD, Hex_FWD]>, + InstrItinData , + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7], + [Hex_FWD, Hex_FWD, HVX_FWD]>, + InstrItinData , InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7, 7, 7], @@ -2827,6 +2878,12 @@ class DepHVXItinV67 { InstrStage<1, [CVI_ALL]>], [3, 2], [HVX_FWD, Hex_FWD]>, + InstrItinData , + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7], + [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + InstrItinData , InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 9, 7, 7, 7], @@ -2885,6 +2942,18 @@ class DepHVXItinV67 { InstrStage<1, [CVI_ZW]>], [3, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData , + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7], + [Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7], + [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + InstrItinData , InstrStage<1, [SLOT1], 0>, @@ -2933,6 +3002,11 @@ class DepHVXItinV67 { InstrStage<1, [CVI_LD]>], [9, 3, 2, 1, 2], [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData , + InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + InstrItinData , InstrStage<1, [CVI_LD], 0>, @@ -3015,12 +3089,507 @@ class DepHVXItinV67 { InstrStage<1, [CVI_ZW]>], [1, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData , + InstrItinData , + InstrStage<1, [CVI_ST]>], [3, 2, 1, 2, 5], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_MPY01]>], [9, 5, 2], + [HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData , + InstrStage<1, [SLOT1], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_XLANE]>], [1, 2, 5], + [Hex_FWD, Hex_FWD, HVX_FWD]> + ]; +} + +class DepHVXItinV68 { + list DepHVXItinV68_list = [ + InstrItinData , + InstrStage<1, [CVI_XLSHF]>], [9, 5], + [HVX_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_SHIFT]>], [9, 5, 5], + [HVX_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 5], + [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_MPY01]>], [9, 5, 2], + [HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 7], + [HVX_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [SLOT1], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_XLANE]>], [2, 1, 2, 5], + [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_ALL]>], [], + []>, + + InstrItinData , + InstrStage<1, [CVI_MPY0, CVI_MPY1], 0>, + InstrStage<1, [CVI_SHIFT, CVI_XLANE]>], [9, 7, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_SHIFT]>], [9, 5, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [3, 7, 1, 2, 7], + [Hex_FWD, HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_MPY01]>], [9, 5, 2, 2], + [HVX_FWD, HVX_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 3, 1, 2], + [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_ST]>], [3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 7, 7, 7], + [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_ALL_NOMEM]>], [9, 3, 5, 2], + [HVX_FWD, Hex_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_MPY01]>], [9, 5, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_XLSHF]>], [9, 7, 5], + [HVX_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_ALL_NOMEM]>], [9, 3, 7, 5, 2], + [HVX_FWD, Hex_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 7, 7, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_SHIFT]>], [9, 7, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_LD]>], [9, 2, 1, 2], + [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 2, 7], + [HVX_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_ZW]>], [3, 2, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData , + InstrStage<1, [SLOT1], 0>, + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_XLANE]>], [9, 3, 1, 2], + [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_ST]>], [1, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [3, 1, 2, 7], + [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7], + [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 3, 2, 1, 2], + [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_XLANE]>], [9, 5, 5], + [HVX_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_SHIFT]>], [9, 5], + [HVX_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_LD]>], [9, 1, 2], + [HVX_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [4, 7, 1], + [Hex_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [3, 2, 1, 2, 7], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_XLSHF]>], [9, 9, 5, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 7, 7], + [HVX_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_XLANE]>], [9, 5, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7, 7], + [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_XLANE]>], [9, 2], + [HVX_FWD, Hex_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_ALL_NOMEM]>], [9, 5, 2], + [HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 5, 2], + [HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_LD]>], [9, 3, 1, 2], + [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_ST]>], [3, 1, 2, 5], + [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_XLANE]>], [9, 5, 2], + [HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7], + [Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7, 7, 7], + [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_ST]>], [2, 1, 2, 5], + [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9], + [HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [1, 2, 7, 7], + [Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_SHIFT]>], [9, 5, 2], + [HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_ALL]>], [3, 2], + [HVX_FWD, Hex_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7], + [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 9, 7, 7, 7], + [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 7, 7], + [HVX_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_XLSHF]>], [9, 5, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [7, 1, 2, 7, 7], + [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_MPY01]>], [9, 5, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_ALL_NOMEM]>], [9, 7, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_XLANE]>], [9, 5], + [HVX_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_XLSHF]>], [9, 7, 5, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7, 7], + [Hex_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [2, 1, 2, 7], + [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_ZW]>], [3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData , InstrStage<1, [CVI_LD], 0>, InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7], [Hex_FWD, Hex_FWD, HVX_FWD]>, + InstrItinData , + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7], + [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [SLOT1], 0>, + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_XLANE]>], [9, 1, 2], + [HVX_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_ST]>], [1, 2, 5], + [Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 2, 1, 2], + [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 7, 2], + [HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 2, 7, 7], + [HVX_FWD, Hex_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 7, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_ALL]>], [2], + [Hex_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7], + [HVX_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_LD]>], [9, 3, 2, 1, 2], + [HVX_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 5, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 1, 2], + [HVX_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 5, 5], + [HVX_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_MPY0, CVI_MPY1]>], [9, 2], + [HVX_FWD, Hex_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [1, 2, 7], + [Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [SLOT1], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_XLANE]>], [3, 2, 1, 2, 5], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_MPY0, CVI_MPY1], 0>, + InstrStage<1, [CVI_SHIFT, CVI_XLANE]>], [9, 5, 2], + [HVX_FWD, HVX_FWD, Hex_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_MPY01]>], [9, 5, 5], + [HVX_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 7, 7], + [HVX_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_ZW]>], [2, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_XLSHF]>], [9, 7, 5, 5], + [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [SLOT1], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_XLANE]>], [3, 1, 2, 5], + [Hex_FWD, Hex_FWD, Hex_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [9, 9, 7, 7], + [HVX_FWD, HVX_FWD, HVX_FWD, HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_ALL]>], [3], + [HVX_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_MPY01]>], [9, 7, 5, 2, 2], + [HVX_FWD, HVX_FWD, HVX_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData , + InstrStage<1, [CVI_ZW]>], [1, 2], + [Hex_FWD, Hex_FWD]>, + InstrItinData , InstrStage<1, [CVI_ST]>], [3, 2, 1, 2, 5], @@ -3036,12 +3605,6 @@ class DepHVXItinV67 { InstrStage<1, [SLOT1], 0>, InstrStage<1, [CVI_ST], 0>, InstrStage<1, [CVI_XLANE]>], [1, 2, 5], - [Hex_FWD, Hex_FWD, HVX_FWD]>, - - InstrItinData , - InstrStage<1, [CVI_LD], 0>, - InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [7, 1, 2, 7], - [HVX_FWD, Hex_FWD, Hex_FWD, HVX_FWD]> + [Hex_FWD, Hex_FWD, HVX_FWD]> ]; } diff --git a/lib/Target/Hexagon/HexagonDepIICScalar.td b/lib/Target/Hexagon/HexagonDepIICScalar.td index fecccb25019..a3766652794 100644 --- a/lib/Target/Hexagon/HexagonDepIICScalar.td +++ b/lib/Target/Hexagon/HexagonDepIICScalar.td @@ -19,8 +19,6 @@ def tc_0a6c20ae : InstrItinClass; def tc_0ba0d5da : InstrItinClass; def tc_0dfac0a7 : InstrItinClass; def tc_0fac1eb8 : InstrItinClass; -def tc_1044324a : InstrItinClass; -def tc_10b884b7 : InstrItinClass; def tc_112d30d6 : InstrItinClass; def tc_1242dc2a : InstrItinClass; def tc_1248597c : InstrItinClass; @@ -29,26 +27,22 @@ def tc_151bf368 : InstrItinClass; def tc_158aa3f7 : InstrItinClass; def tc_197dce51 : InstrItinClass; def tc_1981450d : InstrItinClass; -def tc_1b8138fc : InstrItinClass; def tc_1c2c7a4a : InstrItinClass; def tc_1c7522a8 : InstrItinClass; def tc_1d41f8b7 : InstrItinClass; -def tc_1e7875f0 : InstrItinClass; def tc_1fcb8495 : InstrItinClass; def tc_1fe4ab69 : InstrItinClass; def tc_20131976 : InstrItinClass; def tc_2237d952 : InstrItinClass; -def tc_234f8560 : InstrItinClass; def tc_23708a21 : InstrItinClass; +def tc_2471c1c8 : InstrItinClass; def tc_24e109c7 : InstrItinClass; def tc_24f426ab : InstrItinClass; -def tc_27106296 : InstrItinClass; def tc_280f7fe1 : InstrItinClass; def tc_28e55c6f : InstrItinClass; def tc_2c13e7f5 : InstrItinClass; def tc_2c3e17fc : InstrItinClass; def tc_2f573607 : InstrItinClass; -def tc_2f669c77 : InstrItinClass; def tc_362b0be2 : InstrItinClass; def tc_38382228 : InstrItinClass; def tc_388f9897 : InstrItinClass; @@ -70,7 +64,7 @@ def tc_49fdfd4b : InstrItinClass; def tc_4a55d03c : InstrItinClass; def tc_4abdbdc6 : InstrItinClass; def tc_4ac61d92 : InstrItinClass; -def tc_4c1520ae : InstrItinClass; +def tc_4bf903b0 : InstrItinClass; def tc_503ce0f3 : InstrItinClass; def tc_53c851ab : InstrItinClass; def tc_5502c366 : InstrItinClass; @@ -85,7 +79,6 @@ def tc_59a7822c : InstrItinClass; def tc_5a4b5e58 : InstrItinClass; def tc_5b347363 : InstrItinClass; def tc_5ceb2f9e : InstrItinClass; -def tc_5d636bc7 : InstrItinClass; def tc_5da50c4b : InstrItinClass; def tc_5deb5e47 : InstrItinClass; def tc_5e4cf0e8 : InstrItinClass; @@ -101,7 +94,6 @@ def tc_6ae3426b : InstrItinClass; def tc_6d861a95 : InstrItinClass; def tc_6e20402a : InstrItinClass; def tc_6f42bc60 : InstrItinClass; -def tc_6fb32599 : InstrItinClass; def tc_6fc5dbea : InstrItinClass; def tc_711c805f : InstrItinClass; def tc_713b66bf : InstrItinClass; @@ -111,11 +103,10 @@ def tc_74a42bda : InstrItinClass; def tc_76bb5435 : InstrItinClass; def tc_77f94a5e : InstrItinClass; def tc_788b1d09 : InstrItinClass; +def tc_7af3a37e : InstrItinClass; def tc_7b9187d3 : InstrItinClass; def tc_7c31e19a : InstrItinClass; def tc_7c6d32e4 : InstrItinClass; -def tc_7dc63b5c : InstrItinClass; -def tc_7dcd9d89 : InstrItinClass; def tc_7f7f45f5 : InstrItinClass; def tc_7f8ae742 : InstrItinClass; def tc_8035e91f : InstrItinClass; @@ -130,7 +121,6 @@ def tc_8a825db2 : InstrItinClass; def tc_8b5bd4f5 : InstrItinClass; def tc_8e82e8ca : InstrItinClass; def tc_9124c04f : InstrItinClass; -def tc_9165014d : InstrItinClass; def tc_92240447 : InstrItinClass; def tc_934753bb : InstrItinClass; def tc_937dd41c : InstrItinClass; @@ -139,7 +129,6 @@ def tc_95a33176 : InstrItinClass; def tc_96ef76ef : InstrItinClass; def tc_975a4e54 : InstrItinClass; def tc_9783714b : InstrItinClass; -def tc_988416e3 : InstrItinClass; def tc_9b34f5e0 : InstrItinClass; def tc_9b3c0462 : InstrItinClass; def tc_9bcfb2ee : InstrItinClass; @@ -167,9 +156,7 @@ def tc_addc37a8 : InstrItinClass; def tc_ae5babd7 : InstrItinClass; def tc_aee6250c : InstrItinClass; def tc_b1ae5f67 : InstrItinClass; -def tc_b34eb232 : InstrItinClass; def tc_b4dc7630 : InstrItinClass; -def tc_b570493d : InstrItinClass; def tc_b7c4062a : InstrItinClass; def tc_b837298f : InstrItinClass; def tc_ba9255a6 : InstrItinClass; @@ -186,7 +173,6 @@ def tc_d03278fd : InstrItinClass; def tc_d33e5eee : InstrItinClass; def tc_d3632d88 : InstrItinClass; def tc_d45ba9cd : InstrItinClass; -def tc_d47648a2 : InstrItinClass; def tc_d57d649c : InstrItinClass; def tc_d61dfdc3 : InstrItinClass; def tc_d68dca5c : InstrItinClass; @@ -195,7 +181,6 @@ def tc_db596beb : InstrItinClass; def tc_db96aa6b : InstrItinClass; def tc_dc51281d : InstrItinClass; def tc_decdde8a : InstrItinClass; -def tc_df4536ae : InstrItinClass; def tc_df5d53f9 : InstrItinClass; def tc_e3d699e3 : InstrItinClass; def tc_e9170fb7 : InstrItinClass; @@ -228,8 +213,6 @@ class DepScalarItinV5 { InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, - InstrItinData ]>, - InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, @@ -238,26 +221,22 @@ class DepScalarItinV5 { InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, - InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, - InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, - InstrItinData ]>, InstrItinData ]>, + InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, - InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, - InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, @@ -279,7 +258,7 @@ class DepScalarItinV5 { InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, - InstrItinData ]>, + InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, @@ -294,7 +273,6 @@ class DepScalarItinV5 { InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, - InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, @@ -310,7 +288,6 @@ class DepScalarItinV5 { InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, - InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, @@ -320,11 +297,10 @@ class DepScalarItinV5 { InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, + InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, - InstrItinData ]>, - InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, @@ -339,7 +315,6 @@ class DepScalarItinV5 { InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, - InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, @@ -348,7 +323,6 @@ class DepScalarItinV5 { InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, - InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, @@ -376,9 +350,7 @@ class DepScalarItinV5 { InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, - InstrItinData ]>, InstrItinData ]>, - InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, @@ -395,7 +367,6 @@ class DepScalarItinV5 { InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, - InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, @@ -404,7 +375,6 @@ class DepScalarItinV5 { InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, - InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, InstrItinData ]>, @@ -471,14 +441,6 @@ class DepScalarItinV55 { [InstrStage<1, [SLOT0]>], [3, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [1, 1], - [Hex_FWD, Hex_FWD]>, - - InstrItinData ], [], - []>, - InstrItinData ], [2], [Hex_FWD]>, @@ -511,10 +473,6 @@ class DepScalarItinV55 { [InstrStage<1, [SLOT0]>], [3], [Hex_FWD]>, - InstrItinData ], [4, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [3, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -527,10 +485,6 @@ class DepScalarItinV55 { [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [1, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -547,14 +501,14 @@ class DepScalarItinV55 { [InstrStage<1, [SLOT0]>], [1, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1, 1], - [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [], []>, + InstrItinData ], [4, 1], + [Hex_FWD, Hex_FWD]>, + InstrItinData ], [3, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -563,10 +517,6 @@ class DepScalarItinV55 { [InstrStage<1, [SLOT2, SLOT3]>], [1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 2, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [1, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -587,10 +537,6 @@ class DepScalarItinV55 { [InstrStage<1, [SLOT2]>], [2, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData ], [1, 2], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [1], [Hex_FWD]>, @@ -675,9 +621,9 @@ class DepScalarItinV55 { [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 3, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [2, 1], - [Hex_FWD, Hex_FWD]>, + InstrItinData ], [3], + [Hex_FWD]>, InstrItinData ], [4, 2, 2, 1], @@ -735,10 +681,6 @@ class DepScalarItinV55 { [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -799,10 +741,6 @@ class DepScalarItinV55 { [InstrStage<1, [SLOT0]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [1], - [Hex_FWD]>, - InstrItinData ], [3, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -839,6 +777,10 @@ class DepScalarItinV55 { [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData ], [1, 3], + [Hex_FWD, Hex_FWD]>, + InstrItinData ], [3, 2], [Hex_FWD, Hex_FWD]>, @@ -851,14 +793,6 @@ class DepScalarItinV55 { [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 2], - [Hex_FWD, Hex_FWD]>, - - InstrItinData ], [1, 2], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 4, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -915,10 +849,6 @@ class DepScalarItinV55 { [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [3, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -951,10 +881,6 @@ class DepScalarItinV55 { [InstrStage<1, [SLOT2, SLOT3]>], [4, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData ], [2], - [Hex_FWD]>, - InstrItinData ], [], []>, @@ -1063,18 +989,10 @@ class DepScalarItinV55 { [InstrStage<1, [SLOT0]>], [1], [Hex_FWD]>, - InstrItinData ], [], - []>, - InstrItinData ], [3, 1, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 3, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -1139,10 +1057,6 @@ class DepScalarItinV55 { [InstrStage<1, [SLOT0]>], [1], [Hex_FWD]>, - InstrItinData ], [1, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [2], [Hex_FWD]>, @@ -1175,10 +1089,6 @@ class DepScalarItinV55 { [InstrStage<1, [SLOT2, SLOT3]>], [2], [Hex_FWD]>, - InstrItinData ], [4, 1, 1], - [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 2, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -1299,14 +1209,6 @@ class DepScalarItinV60 { [InstrStage<1, [SLOT0]>], [3, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [1, 1], - [Hex_FWD, Hex_FWD]>, - - InstrItinData ], [], - []>, - InstrItinData ], [2], [Hex_FWD]>, @@ -1339,10 +1241,6 @@ class DepScalarItinV60 { [InstrStage<1, [SLOT0]>], [3], [Hex_FWD]>, - InstrItinData ], [4, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [3, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -1355,10 +1253,6 @@ class DepScalarItinV60 { [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [1, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -1375,14 +1269,14 @@ class DepScalarItinV60 { [InstrStage<1, [SLOT0]>], [1, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1, 1], - [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [], []>, + InstrItinData ], [4, 1], + [Hex_FWD, Hex_FWD]>, + InstrItinData ], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -1391,10 +1285,6 @@ class DepScalarItinV60 { [InstrStage<1, [SLOT2, SLOT3]>], [1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [1, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -1415,10 +1305,6 @@ class DepScalarItinV60 { [InstrStage<1, [SLOT2]>], [2, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData ], [1, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [1], [Hex_FWD]>, @@ -1503,9 +1389,9 @@ class DepScalarItinV60 { [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 3, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [2, 1], - [Hex_FWD, Hex_FWD]>, + InstrItinData ], [3], + [Hex_FWD]>, InstrItinData ], [4, 2, 2, 1], @@ -1563,10 +1449,6 @@ class DepScalarItinV60 { [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -1627,10 +1509,6 @@ class DepScalarItinV60 { [InstrStage<1, [SLOT0]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [1], - [Hex_FWD]>, - InstrItinData ], [3, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -1667,6 +1545,10 @@ class DepScalarItinV60 { [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData ], [1, 3], + [Hex_FWD, Hex_FWD]>, + InstrItinData ], [3, 2], [Hex_FWD, Hex_FWD]>, @@ -1679,14 +1561,6 @@ class DepScalarItinV60 { [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1], - [Hex_FWD, Hex_FWD]>, - - InstrItinData ], [1, 2], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [5, 5, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -1743,10 +1617,6 @@ class DepScalarItinV60 { [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [3, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -1779,10 +1649,6 @@ class DepScalarItinV60 { [InstrStage<1, [SLOT2, SLOT3]>], [5, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData ], [2], - [Hex_FWD]>, - InstrItinData ], [], []>, @@ -1891,18 +1757,10 @@ class DepScalarItinV60 { [InstrStage<1, [SLOT0]>], [1], [Hex_FWD]>, - InstrItinData ], [], - []>, - InstrItinData ], [3, 1, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 3, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -1967,10 +1825,6 @@ class DepScalarItinV60 { [InstrStage<1, [SLOT0]>], [1], [Hex_FWD]>, - InstrItinData ], [1, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [2], [Hex_FWD]>, @@ -2003,10 +1857,6 @@ class DepScalarItinV60 { [InstrStage<1, [SLOT2, SLOT3]>], [2], [Hex_FWD]>, - InstrItinData ], [4, 1, 1], - [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -2127,15 +1977,6 @@ class DepScalarItinV60se { [InstrStage<1, [SLOT0]>], [3, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [1, 1], - [Hex_FWD, Hex_FWD]>, - - InstrItinData , - InstrStage<1, [CVI_ST]>], [], - []>, - InstrItinData ], [2], [Hex_FWD]>, @@ -2170,10 +2011,6 @@ class DepScalarItinV60se { InstrStage<1, [CVI_ST]>], [3], [Hex_FWD]>, - InstrItinData ], [4, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [3, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -2186,10 +2023,6 @@ class DepScalarItinV60se { [InstrStage<1, [SLOT2, SLOT3]>], [4, 4, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [1, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -2206,15 +2039,15 @@ class DepScalarItinV60se { [InstrStage<1, [SLOT0]>], [1, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1, 1], - [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData , InstrStage<1, [CVI_ST]>], [], []>, + InstrItinData ], [4, 1], + [Hex_FWD, Hex_FWD]>, + InstrItinData , InstrStage<1, [CVI_ST]>], [3, 2, 2], @@ -2225,10 +2058,6 @@ class DepScalarItinV60se { InstrStage<1, [CVI_ST]>], [1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [1, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -2250,10 +2079,6 @@ class DepScalarItinV60se { InstrStage<1, [CVI_ST]>], [2, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData ], [1, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData , InstrStage<1, [CVI_ST]>], [1], @@ -2343,9 +2168,9 @@ class DepScalarItinV60se { [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 3, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [2, 1], - [Hex_FWD, Hex_FWD]>, + InstrItinData ], [3], + [Hex_FWD]>, InstrItinData ], [4, 2, 2, 1], @@ -2407,10 +2232,6 @@ class DepScalarItinV60se { [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -2473,10 +2294,6 @@ class DepScalarItinV60se { [InstrStage<1, [SLOT0]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [1], - [Hex_FWD]>, - InstrItinData ], [3, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -2514,6 +2331,10 @@ class DepScalarItinV60se { [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData ], [1, 3], + [Hex_FWD, Hex_FWD]>, + InstrItinData , InstrStage<1, [CVI_ST]>], [3, 2], @@ -2527,14 +2348,6 @@ class DepScalarItinV60se { [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1], - [Hex_FWD, Hex_FWD]>, - - InstrItinData ], [1, 2], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [5, 5, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -2591,10 +2404,6 @@ class DepScalarItinV60se { [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [3, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -2628,10 +2437,6 @@ class DepScalarItinV60se { [InstrStage<1, [SLOT2, SLOT3]>], [5, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData ], [2], - [Hex_FWD]>, - InstrItinData ], [], []>, @@ -2742,18 +2547,10 @@ class DepScalarItinV60se { [InstrStage<1, [SLOT0]>], [1], [Hex_FWD]>, - InstrItinData ], [], - []>, - InstrItinData ], [3, 1, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 3, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -2819,10 +2616,6 @@ class DepScalarItinV60se { [InstrStage<1, [SLOT0]>], [1], [Hex_FWD]>, - InstrItinData ], [1, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData , InstrStage<1, [CVI_ST]>], [2], @@ -2858,10 +2651,6 @@ class DepScalarItinV60se { InstrStage<1, [CVI_ST]>], [2], [Hex_FWD]>, - InstrItinData ], [4, 1, 1], - [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData , InstrStage<1, [CVI_ST]>], [3, 2, 2], @@ -2988,14 +2777,6 @@ class DepScalarItinV62 { [InstrStage<1, [SLOT0]>], [3, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [1, 1], - [Hex_FWD, Hex_FWD]>, - - InstrItinData ], [], - []>, - InstrItinData ], [2], [Hex_FWD]>, @@ -3028,10 +2809,6 @@ class DepScalarItinV62 { [InstrStage<1, [SLOT0]>], [3], [Hex_FWD]>, - InstrItinData ], [4, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [3, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -3044,10 +2821,6 @@ class DepScalarItinV62 { [InstrStage<1, [SLOT2, SLOT3]>], [3, 4, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [1, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -3064,14 +2837,14 @@ class DepScalarItinV62 { [InstrStage<1, [SLOT0]>], [1, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1, 1], - [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [], []>, + InstrItinData ], [4, 1], + [Hex_FWD, Hex_FWD]>, + InstrItinData ], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -3080,10 +2853,6 @@ class DepScalarItinV62 { [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [1, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -3104,10 +2873,6 @@ class DepScalarItinV62 { [InstrStage<1, [SLOT2]>], [2, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData ], [1, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [1], [Hex_FWD]>, @@ -3192,9 +2957,9 @@ class DepScalarItinV62 { [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 3, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [2, 1], - [Hex_FWD, Hex_FWD]>, + InstrItinData ], [3], + [Hex_FWD]>, InstrItinData ], [4, 2, 2, 1], @@ -3252,10 +3017,6 @@ class DepScalarItinV62 { [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -3316,10 +3077,6 @@ class DepScalarItinV62 { [InstrStage<1, [SLOT0]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [1], - [Hex_FWD]>, - InstrItinData ], [3, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -3356,6 +3113,10 @@ class DepScalarItinV62 { [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData ], [1, 3], + [Hex_FWD, Hex_FWD]>, + InstrItinData ], [3, 2], [Hex_FWD, Hex_FWD]>, @@ -3368,14 +3129,6 @@ class DepScalarItinV62 { [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1], - [Hex_FWD, Hex_FWD]>, - - InstrItinData ], [1, 2], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [5, 5, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -3432,10 +3185,6 @@ class DepScalarItinV62 { [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [3, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -3468,10 +3217,6 @@ class DepScalarItinV62 { [InstrStage<1, [SLOT2, SLOT3]>], [5, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData ], [2], - [Hex_FWD]>, - InstrItinData ], [], []>, @@ -3580,18 +3325,10 @@ class DepScalarItinV62 { [InstrStage<1, [SLOT0]>], [1], [Hex_FWD]>, - InstrItinData ], [], - []>, - InstrItinData ], [3, 1, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 3, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -3656,10 +3393,6 @@ class DepScalarItinV62 { [InstrStage<1, [SLOT0]>], [1], [Hex_FWD]>, - InstrItinData ], [1, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [2], [Hex_FWD]>, @@ -3692,10 +3425,6 @@ class DepScalarItinV62 { [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2], [Hex_FWD]>, - InstrItinData ], [4, 1, 1], - [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -3816,14 +3545,6 @@ class DepScalarItinV65 { [InstrStage<1, [SLOT0]>], [3, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [1, 1], - [Hex_FWD, Hex_FWD]>, - - InstrItinData ], [], - []>, - InstrItinData ], [2], [Hex_FWD]>, @@ -3856,10 +3577,6 @@ class DepScalarItinV65 { [InstrStage<1, [SLOT0]>], [3], [Hex_FWD]>, - InstrItinData ], [4, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [3, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -3872,10 +3589,6 @@ class DepScalarItinV65 { [InstrStage<1, [SLOT2, SLOT3]>], [3, 4, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [1, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -3892,14 +3605,14 @@ class DepScalarItinV65 { [InstrStage<1, [SLOT0]>], [1, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1, 1], - [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [], []>, + InstrItinData ], [4, 1], + [Hex_FWD, Hex_FWD]>, + InstrItinData ], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -3908,10 +3621,6 @@ class DepScalarItinV65 { [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [1, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -3932,10 +3641,6 @@ class DepScalarItinV65 { [InstrStage<1, [SLOT2]>], [2, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData ], [1, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [1], [Hex_FWD]>, @@ -4020,9 +3725,9 @@ class DepScalarItinV65 { [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 3, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [2, 1], - [Hex_FWD, Hex_FWD]>, + InstrItinData ], [3], + [Hex_FWD]>, InstrItinData ], [4, 2, 2, 1], @@ -4080,10 +3785,6 @@ class DepScalarItinV65 { [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -4144,10 +3845,6 @@ class DepScalarItinV65 { [InstrStage<1, [SLOT0]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [1], - [Hex_FWD]>, - InstrItinData ], [3, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -4184,6 +3881,10 @@ class DepScalarItinV65 { [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData ], [1, 3], + [Hex_FWD, Hex_FWD]>, + InstrItinData ], [3, 2], [Hex_FWD, Hex_FWD]>, @@ -4196,14 +3897,6 @@ class DepScalarItinV65 { [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1], - [Hex_FWD, Hex_FWD]>, - - InstrItinData ], [1, 2], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [5, 5, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -4260,10 +3953,6 @@ class DepScalarItinV65 { [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [3, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -4296,10 +3985,6 @@ class DepScalarItinV65 { [InstrStage<1, [SLOT2, SLOT3]>], [5, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData ], [2], - [Hex_FWD]>, - InstrItinData ], [], []>, @@ -4408,18 +4093,10 @@ class DepScalarItinV65 { [InstrStage<1, [SLOT0]>], [1], [Hex_FWD]>, - InstrItinData ], [], - []>, - InstrItinData ], [3, 1, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 3, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -4484,10 +4161,6 @@ class DepScalarItinV65 { [InstrStage<1, [SLOT0]>], [1], [Hex_FWD]>, - InstrItinData ], [1, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [2], [Hex_FWD]>, @@ -4520,10 +4193,6 @@ class DepScalarItinV65 { [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2], [Hex_FWD]>, - InstrItinData ], [4, 1, 1], - [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [3, 2, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -4644,14 +4313,6 @@ class DepScalarItinV66 { [InstrStage<1, [SLOT0]>], [3, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [1, 1], - [Hex_FWD, Hex_FWD]>, - - InstrItinData ], [], - []>, - InstrItinData ], [2], [Hex_FWD]>, @@ -4684,10 +4345,6 @@ class DepScalarItinV66 { [InstrStage<1, [SLOT0]>], [3], [Hex_FWD]>, - InstrItinData ], [4, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [3, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -4700,10 +4357,6 @@ class DepScalarItinV66 { [InstrStage<1, [SLOT2, SLOT3]>], [3, 4, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [1, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -4720,14 +4373,14 @@ class DepScalarItinV66 { [InstrStage<1, [SLOT0]>], [1, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1, 1], - [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [], []>, + InstrItinData ], [4, 1], + [Hex_FWD, Hex_FWD]>, + InstrItinData ], [3, 3, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -4736,10 +4389,6 @@ class DepScalarItinV66 { [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [1, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -4760,10 +4409,6 @@ class DepScalarItinV66 { [InstrStage<1, [SLOT2]>], [2, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData ], [1, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [1], [Hex_FWD]>, @@ -4848,9 +4493,9 @@ class DepScalarItinV66 { [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 3, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [2, 1], - [Hex_FWD, Hex_FWD]>, + InstrItinData ], [3], + [Hex_FWD]>, InstrItinData ], [4, 2, 2, 1], @@ -4908,10 +4553,6 @@ class DepScalarItinV66 { [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -4972,10 +4613,6 @@ class DepScalarItinV66 { [InstrStage<1, [SLOT0]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [1], - [Hex_FWD]>, - InstrItinData ], [3, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -5012,6 +4649,10 @@ class DepScalarItinV66 { [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData ], [1, 3], + [Hex_FWD, Hex_FWD]>, + InstrItinData ], [3, 2], [Hex_FWD, Hex_FWD]>, @@ -5024,14 +4665,6 @@ class DepScalarItinV66 { [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1], - [Hex_FWD, Hex_FWD]>, - - InstrItinData ], [1, 3], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [5, 5, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -5088,10 +4721,6 @@ class DepScalarItinV66 { [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [3, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -5124,10 +4753,6 @@ class DepScalarItinV66 { [InstrStage<1, [SLOT2, SLOT3]>], [5, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData ], [3], - [Hex_FWD]>, - InstrItinData ], [], []>, @@ -5236,18 +4861,10 @@ class DepScalarItinV66 { [InstrStage<1, [SLOT0]>], [1], [Hex_FWD]>, - InstrItinData ], [], - []>, - InstrItinData ], [3, 1, 2, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 3, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -5312,10 +4929,6 @@ class DepScalarItinV66 { [InstrStage<1, [SLOT0]>], [1], [Hex_FWD]>, - InstrItinData ], [1, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [2], [Hex_FWD]>, @@ -5348,10 +4961,6 @@ class DepScalarItinV66 { [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2], [Hex_FWD]>, - InstrItinData ], [4, 1, 1], - [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [3, 2, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -5472,14 +5081,6 @@ class DepScalarItinV67 { [InstrStage<1, [SLOT0]>], [3, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [1, 1], - [Hex_FWD, Hex_FWD]>, - - InstrItinData ], [], - []>, - InstrItinData ], [2], [Hex_FWD]>, @@ -5512,10 +5113,6 @@ class DepScalarItinV67 { [InstrStage<1, [SLOT0]>], [3], [Hex_FWD]>, - InstrItinData ], [4, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [3, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -5528,10 +5125,6 @@ class DepScalarItinV67 { [InstrStage<1, [SLOT2, SLOT3]>], [3, 4, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [1, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -5548,14 +5141,14 @@ class DepScalarItinV67 { [InstrStage<1, [SLOT0]>], [1, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1, 1], - [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [], []>, + InstrItinData ], [4, 1], + [Hex_FWD, Hex_FWD]>, + InstrItinData ], [3, 3, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -5564,10 +5157,6 @@ class DepScalarItinV67 { [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [1, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -5588,10 +5177,6 @@ class DepScalarItinV67 { [InstrStage<1, [SLOT2]>], [2, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData ], [1, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [1], [Hex_FWD]>, @@ -5676,9 +5261,9 @@ class DepScalarItinV67 { [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 3, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [2, 1], - [Hex_FWD, Hex_FWD]>, + InstrItinData ], [3], + [Hex_FWD]>, InstrItinData ], [4, 2, 2, 1], @@ -5736,10 +5321,6 @@ class DepScalarItinV67 { [InstrStage<1, [SLOT0, SLOT1]>], [4, 3, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -5800,10 +5381,6 @@ class DepScalarItinV67 { [InstrStage<1, [SLOT0]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [1], - [Hex_FWD]>, - InstrItinData ], [3, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -5840,6 +5417,10 @@ class DepScalarItinV67 { [InstrStage<1, [SLOT2, SLOT3]>], [4, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData ], [1, 3], + [Hex_FWD, Hex_FWD]>, + InstrItinData ], [3, 2], [Hex_FWD, Hex_FWD]>, @@ -5852,14 +5433,6 @@ class DepScalarItinV67 { [InstrStage<1, [SLOT0, SLOT1]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1], - [Hex_FWD, Hex_FWD]>, - - InstrItinData ], [1, 3], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [5, 5, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -5916,10 +5489,6 @@ class DepScalarItinV67 { [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [3, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -5952,10 +5521,6 @@ class DepScalarItinV67 { [InstrStage<1, [SLOT2, SLOT3]>], [5, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData ], [3], - [Hex_FWD]>, - InstrItinData ], [], []>, @@ -6064,18 +5629,10 @@ class DepScalarItinV67 { [InstrStage<1, [SLOT0]>], [1], [Hex_FWD]>, - InstrItinData ], [], - []>, - InstrItinData ], [3, 1, 2, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 3, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -6140,10 +5697,6 @@ class DepScalarItinV67 { [InstrStage<1, [SLOT0]>], [1], [Hex_FWD]>, - InstrItinData ], [1, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [2], [Hex_FWD]>, @@ -6176,10 +5729,6 @@ class DepScalarItinV67 { [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2], [Hex_FWD]>, - InstrItinData ], [4, 1, 1], - [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [3, 2, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -6300,14 +5849,6 @@ class DepScalarItinV67T { [InstrStage<1, [SLOT0]>], [3, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [1, 1], - [Hex_FWD, Hex_FWD]>, - - InstrItinData ], [], - []>, - InstrItinData ], [2], [Hex_FWD]>, @@ -6340,10 +5881,6 @@ class DepScalarItinV67T { [InstrStage<1, [SLOT0]>], [3], [Hex_FWD]>, - InstrItinData ], [4, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [3, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -6356,10 +5893,6 @@ class DepScalarItinV67T { [InstrStage<1, [SLOT2, SLOT3]>], [3, 4, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [1, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -6376,14 +5909,14 @@ class DepScalarItinV67T { [InstrStage<1, [SLOT0]>], [1, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1, 1], - [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [], []>, + InstrItinData ], [4, 1], + [Hex_FWD, Hex_FWD]>, + InstrItinData ], [3, 3, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -6392,10 +5925,6 @@ class DepScalarItinV67T { [InstrStage<1, [SLOT0, SLOT2, SLOT3]>], [2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1, 2], - [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [1, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -6416,10 +5945,6 @@ class DepScalarItinV67T { [InstrStage<1, [SLOT2]>], [2, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData ], [1, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [1], [Hex_FWD]>, @@ -6504,9 +6029,9 @@ class DepScalarItinV67T { [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [4, 3, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [2, 1], - [Hex_FWD, Hex_FWD]>, + InstrItinData ], [3], + [Hex_FWD]>, InstrItinData ], [4, 2, 2, 1], @@ -6564,10 +6089,6 @@ class DepScalarItinV67T { [InstrStage<1, [SLOT0]>], [4, 3, 1, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [3, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -6628,10 +6149,6 @@ class DepScalarItinV67T { [InstrStage<1, [SLOT0]>], [4, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [1], - [Hex_FWD]>, - InstrItinData ], [3, 2, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -6668,6 +6185,10 @@ class DepScalarItinV67T { [InstrStage<1, [SLOT3]>], [4, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + InstrItinData ], [1, 3], + [Hex_FWD, Hex_FWD]>, + InstrItinData ], [3, 2], [Hex_FWD, Hex_FWD]>, @@ -6680,14 +6201,6 @@ class DepScalarItinV67T { [InstrStage<1, [SLOT0]>], [4, 2, 2], [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1], - [Hex_FWD, Hex_FWD]>, - - InstrItinData ], [1, 3], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [5, 5, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -6744,10 +6257,6 @@ class DepScalarItinV67T { [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [3, 2], [Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [3, 1, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -6780,10 +6289,6 @@ class DepScalarItinV67T { [InstrStage<1, [SLOT3]>], [5, 1], [Hex_FWD, Hex_FWD]>, - InstrItinData ], [3], - [Hex_FWD]>, - InstrItinData ], [], []>, @@ -6892,18 +6397,10 @@ class DepScalarItinV67T { [InstrStage<1, [SLOT0]>], [1], [Hex_FWD]>, - InstrItinData ], [], - []>, - InstrItinData ], [3, 1, 2, 2, 3], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [4, 3, 1, 1, 2], [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -6968,10 +6465,6 @@ class DepScalarItinV67T { [InstrStage<1, [SLOT0]>], [1], [Hex_FWD]>, - InstrItinData ], [1, 1], - [Hex_FWD, Hex_FWD]>, - InstrItinData ], [2], [Hex_FWD]>, @@ -7004,10 +6497,6 @@ class DepScalarItinV67T { [InstrStage<1, [SLOT0, SLOT2, SLOT3]>], [2], [Hex_FWD]>, - InstrItinData ], [4, 1, 1], - [Hex_FWD, Hex_FWD, Hex_FWD]>, - InstrItinData ], [3, 2, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>, @@ -7081,3 +6570,771 @@ class DepScalarItinV67T { [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]> ]; } + +class DepScalarItinV68 { + list DepScalarItinV68_list = [ + InstrItinData ], [2, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 2, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [5, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [2, 3], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [5, 2, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [2, 1, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [1], + [Hex_FWD]>, + + InstrItinData ], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [3, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [2], + [Hex_FWD]>, + + InstrItinData ], [2], + [Hex_FWD]>, + + InstrItinData ], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [3, 3, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 2, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [3], + [Hex_FWD]>, + + InstrItinData ], [3, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 3, 2, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [3, 4, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [2, 1, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [1, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [], + []>, + + InstrItinData ], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [3, 3, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [1, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [1, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [1], + [Hex_FWD]>, + + InstrItinData ], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [1], + [Hex_FWD]>, + + InstrItinData ], [4, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 4, 2, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [3], + [Hex_FWD]>, + + InstrItinData ], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [3, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 3, 1, 2, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [1, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [2], + [Hex_FWD]>, + + InstrItinData ], [4, 2, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [2], + [Hex_FWD]>, + + InstrItinData ], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 3, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [3], + [Hex_FWD]>, + + InstrItinData ], [4, 2, 2, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [], + []>, + + InstrItinData ], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [1, 2, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 3, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 4, 3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [2], + [Hex_FWD]>, + + InstrItinData ], [4], + [Hex_FWD]>, + + InstrItinData ], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [3, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [2, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [2, 3], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [3, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 3, 2, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [], + []>, + + InstrItinData ], [4, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [1, 3], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [5, 5, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 2, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [2, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 3, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [3, 1, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 3, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [1, 2, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [3, 1, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [3, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [3, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [], + []>, + + InstrItinData ], [2, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [1, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [3, 3, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [5, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [], + []>, + + InstrItinData ], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [5, 2, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [5, 2, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [3, 2, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 2, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [3, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [1, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 2, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 2, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [], + []>, + + InstrItinData ], [3, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [3, 1, 2, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [1], + [Hex_FWD]>, + + InstrItinData ], [3, 1, 2, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 3, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [], + []>, + + InstrItinData ], [2, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [3, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 2, 2, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [], + []>, + + InstrItinData ], [3, 2, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [2, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [2, 1, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [1], + [Hex_FWD]>, + + InstrItinData ], [2], + [Hex_FWD]>, + + InstrItinData ], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [1], + [Hex_FWD]>, + + InstrItinData ], [4, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [1], + [Hex_FWD]>, + + InstrItinData ], [2, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [2], + [Hex_FWD]>, + + InstrItinData ], [3, 2, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 1], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [3, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 1, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [5, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [2], + [Hex_FWD]>, + + InstrItinData ], [4, 3, 1, 2, 3], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [3, 2, 2], + [Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [5, 5, 1, 1], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]>, + + InstrItinData ], [2, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 2], + [Hex_FWD, Hex_FWD]>, + + InstrItinData ], [4, 2, 1, 2], + [Hex_FWD, Hex_FWD, Hex_FWD, Hex_FWD]> + ]; +} diff --git a/lib/Target/Hexagon/HexagonDepITypes.h b/lib/Target/Hexagon/HexagonDepITypes.h index b261b465312..54e046d5536 100644 --- a/lib/Target/Hexagon/HexagonDepITypes.h +++ b/lib/Target/Hexagon/HexagonDepITypes.h @@ -8,6 +8,10 @@ // Automatically generated file, do not edit! //===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPITYPES_H +#define LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPITYPES_H + namespace llvm { namespace HexagonII { enum Type { @@ -16,48 +20,50 @@ enum Type { TypeALU32_ADDI = 2, TypeALU64 = 3, TypeCJ = 4, - TypeCR = 7, - TypeCVI_4SLOT_MPY = 8, - TypeCVI_GATHER = 9, - TypeCVI_GATHER_DV = 10, - TypeCVI_GATHER_RST = 11, - TypeCVI_HIST = 12, - TypeCVI_SCATTER = 13, - TypeCVI_SCATTER_DV = 14, - TypeCVI_SCATTER_NEW_RST = 15, - TypeCVI_SCATTER_NEW_ST = 16, - TypeCVI_SCATTER_RST = 17, - TypeCVI_VA = 18, - TypeCVI_VA_DV = 19, - TypeCVI_VM_LD = 20, - TypeCVI_VM_NEW_ST = 21, - TypeCVI_VM_ST = 22, - TypeCVI_VM_STU = 23, - TypeCVI_VM_TMP_LD = 24, - TypeCVI_VM_VP_LDU = 25, - TypeCVI_VP = 26, - TypeCVI_VP_VS = 27, - TypeCVI_VS = 28, - TypeCVI_VS_VX = 29, - TypeCVI_VX = 30, - TypeCVI_VX_DV = 31, - TypeCVI_VX_LATE = 32, - TypeCVI_ZW = 33, - TypeDUPLEX = 34, - TypeENDLOOP = 35, - TypeEXTENDER = 36, - TypeJ = 37, - TypeLD = 38, - TypeM = 39, - TypeMAPPING = 40, - TypeNCJ = 41, - TypePSEUDO = 42, - TypeST = 43, - TypeSUBINSN = 44, - TypeS_2op = 45, - TypeS_3op = 46, - TypeV2LDST = 49, - TypeV4LDST = 50, + TypeCR = 5, + TypeCVI_4SLOT_MPY = 6, + TypeCVI_GATHER = 7, + TypeCVI_GATHER_DV = 8, + TypeCVI_GATHER_RST = 9, + TypeCVI_HIST = 10, + TypeCVI_SCATTER = 11, + TypeCVI_SCATTER_DV = 12, + TypeCVI_SCATTER_NEW_RST = 13, + TypeCVI_SCATTER_NEW_ST = 14, + TypeCVI_SCATTER_RST = 15, + TypeCVI_VA = 16, + TypeCVI_VA_DV = 17, + TypeCVI_VM_LD = 18, + TypeCVI_VM_NEW_ST = 19, + TypeCVI_VM_ST = 20, + TypeCVI_VM_STU = 21, + TypeCVI_VM_TMP_LD = 22, + TypeCVI_VM_VP_LDU = 23, + TypeCVI_VP = 24, + TypeCVI_VP_VS = 25, + TypeCVI_VS = 26, + TypeCVI_VS_VX = 27, + TypeCVI_VX = 28, + TypeCVI_VX_DV = 29, + TypeCVI_VX_LATE = 30, + TypeCVI_ZW = 31, + TypeDUPLEX = 32, + TypeENDLOOP = 33, + TypeEXTENDER = 34, + TypeJ = 35, + TypeLD = 36, + TypeM = 37, + TypeMAPPING = 38, + TypeNCJ = 39, + TypePSEUDO = 40, + TypeST = 41, + TypeSUBINSN = 42, + TypeS_2op = 43, + TypeS_3op = 44, + TypeV2LDST = 47, + TypeV4LDST = 48, }; } } + +#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPITYPES_H diff --git a/lib/Target/Hexagon/HexagonDepITypes.td b/lib/Target/Hexagon/HexagonDepITypes.td index f251a291c23..8d2b46d7f99 100644 --- a/lib/Target/Hexagon/HexagonDepITypes.td +++ b/lib/Target/Hexagon/HexagonDepITypes.td @@ -14,45 +14,45 @@ def TypeALU32_3op : IType<1>; def TypeALU32_ADDI : IType<2>; def TypeALU64 : IType<3>; def TypeCJ : IType<4>; -def TypeCR : IType<7>; -def TypeCVI_4SLOT_MPY : IType<8>; -def TypeCVI_GATHER : IType<9>; -def TypeCVI_GATHER_DV : IType<10>; -def TypeCVI_GATHER_RST : IType<11>; -def TypeCVI_HIST : IType<12>; -def TypeCVI_SCATTER : IType<13>; -def TypeCVI_SCATTER_DV : IType<14>; -def TypeCVI_SCATTER_NEW_RST : IType<15>; -def TypeCVI_SCATTER_NEW_ST : IType<16>; -def TypeCVI_SCATTER_RST : IType<17>; -def TypeCVI_VA : IType<18>; -def TypeCVI_VA_DV : IType<19>; -def TypeCVI_VM_LD : IType<20>; -def TypeCVI_VM_NEW_ST : IType<21>; -def TypeCVI_VM_ST : IType<22>; -def TypeCVI_VM_STU : IType<23>; -def TypeCVI_VM_TMP_LD : IType<24>; -def TypeCVI_VM_VP_LDU : IType<25>; -def TypeCVI_VP : IType<26>; -def TypeCVI_VP_VS : IType<27>; -def TypeCVI_VS : IType<28>; -def TypeCVI_VS_VX : IType<29>; -def TypeCVI_VX : IType<30>; -def TypeCVI_VX_DV : IType<31>; -def TypeCVI_VX_LATE : IType<32>; -def TypeCVI_ZW : IType<33>; -def TypeDUPLEX : IType<34>; -def TypeENDLOOP : IType<35>; -def TypeEXTENDER : IType<36>; -def TypeJ : IType<37>; -def TypeLD : IType<38>; -def TypeM : IType<39>; -def TypeMAPPING : IType<40>; -def TypeNCJ : IType<41>; -def TypePSEUDO : IType<42>; -def TypeST : IType<43>; -def TypeSUBINSN : IType<44>; -def TypeS_2op : IType<45>; -def TypeS_3op : IType<46>; -def TypeV2LDST : IType<49>; -def TypeV4LDST : IType<50>; +def TypeCR : IType<5>; +def TypeCVI_4SLOT_MPY : IType<6>; +def TypeCVI_GATHER : IType<7>; +def TypeCVI_GATHER_DV : IType<8>; +def TypeCVI_GATHER_RST : IType<9>; +def TypeCVI_HIST : IType<10>; +def TypeCVI_SCATTER : IType<11>; +def TypeCVI_SCATTER_DV : IType<12>; +def TypeCVI_SCATTER_NEW_RST : IType<13>; +def TypeCVI_SCATTER_NEW_ST : IType<14>; +def TypeCVI_SCATTER_RST : IType<15>; +def TypeCVI_VA : IType<16>; +def TypeCVI_VA_DV : IType<17>; +def TypeCVI_VM_LD : IType<18>; +def TypeCVI_VM_NEW_ST : IType<19>; +def TypeCVI_VM_ST : IType<20>; +def TypeCVI_VM_STU : IType<21>; +def TypeCVI_VM_TMP_LD : IType<22>; +def TypeCVI_VM_VP_LDU : IType<23>; +def TypeCVI_VP : IType<24>; +def TypeCVI_VP_VS : IType<25>; +def TypeCVI_VS : IType<26>; +def TypeCVI_VS_VX : IType<27>; +def TypeCVI_VX : IType<28>; +def TypeCVI_VX_DV : IType<29>; +def TypeCVI_VX_LATE : IType<30>; +def TypeCVI_ZW : IType<31>; +def TypeDUPLEX : IType<32>; +def TypeENDLOOP : IType<33>; +def TypeEXTENDER : IType<34>; +def TypeJ : IType<35>; +def TypeLD : IType<36>; +def TypeM : IType<37>; +def TypeMAPPING : IType<38>; +def TypeNCJ : IType<39>; +def TypePSEUDO : IType<40>; +def TypeST : IType<41>; +def TypeSUBINSN : IType<42>; +def TypeS_2op : IType<43>; +def TypeS_3op : IType<44>; +def TypeV2LDST : IType<47>; +def TypeV4LDST : IType<48>; diff --git a/lib/Target/Hexagon/HexagonDepInstrFormats.td b/lib/Target/Hexagon/HexagonDepInstrFormats.td index 305115da576..4dd0110c4fe 100644 --- a/lib/Target/Hexagon/HexagonDepInstrFormats.td +++ b/lib/Target/Hexagon/HexagonDepInstrFormats.td @@ -8,50 +8,197 @@ // Automatically generated file, do not edit! //===----------------------------------------------------------------------===// -class Enc_5e2823 : OpcodeHexagon { +class Enc_01d3d0 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; +} +class Enc_02553a : OpcodeHexagon { + bits <7> Ii; + let Inst{11-5} = Ii{6-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_03833b : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_041d7b : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <5> n1; + let Inst{28-28} = n1{4-4}; + let Inst{24-23} = n1{3-2}; + let Inst{13-13} = n1{1-1}; + let Inst{8-8} = n1{0-0}; +} +class Enc_04c959 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; + bits <6> II; + let Inst{11-8} = II{5-2}; + let Inst{6-5} = II{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Ryy32; + let Inst{4-0} = Ryy32{4-0}; +} +class Enc_0527db : OpcodeHexagon { + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; + bits <4> Rx16; + let Inst{3-0} = Rx16{3-0}; +} +class Enc_052c7d : OpcodeHexagon { + bits <5> Ii; + let Inst{6-3} = Ii{4-1}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_08d755 : OpcodeHexagon { + bits <8> Ii; + let Inst{12-5} = Ii{7-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_0aa344 : OpcodeHexagon { + bits <5> Gss32; + let Inst{20-16} = Gss32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_0b2e5b : OpcodeHexagon { + bits <3> Ii; + let Inst{7-5} = Ii{2-0}; + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_0b51ce : OpcodeHexagon { + bits <3> Ii; + let Inst{10-8} = Ii{2-0}; + bits <2> Qv4; + let Inst{12-11} = Qv4{1-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_0cb018 : OpcodeHexagon { + bits <5> Cs32; + let Inst{20-16} = Cs32{4-0}; bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; } -class Enc_b9c5fb : OpcodeHexagon { +class Enc_0d8870 : OpcodeHexagon { + bits <12> Ii; + let Inst{26-25} = Ii{11-10}; + let Inst{13-13} = Ii{9-9}; + let Inst{7-0} = Ii{8-1}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; +} +class Enc_0d8adb : OpcodeHexagon { + bits <8> Ii; + let Inst{12-5} = Ii{7-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_0e41fa : OpcodeHexagon { + bits <5> Vuu32; + let Inst{12-8} = Vuu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_0ed752 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Cdd32; + let Inst{4-0} = Cdd32{4-0}; +} +class Enc_0f8bab : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <2> Qd4; + let Inst{1-0} = Qd4{1-0}; +} +class Enc_0fa531 : OpcodeHexagon { + bits <15> Ii; + let Inst{21-21} = Ii{14-14}; + let Inst{13-13} = Ii{13-13}; + let Inst{11-1} = Ii{12-2}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} +class Enc_10bc21 : OpcodeHexagon { + bits <4> Ii; + let Inst{6-3} = Ii{3-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_1178da : OpcodeHexagon { + bits <3> Ii; + let Inst{7-5} = Ii{2-0}; + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vxx32; + let Inst{4-0} = Vxx32{4-0}; +} +class Enc_11a146 : OpcodeHexagon { + bits <4> Ii; + let Inst{11-8} = Ii{3-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_12b6e9 : OpcodeHexagon { + bits <4> Ii; + let Inst{11-8} = Ii{3-0}; bits <5> Rss32; let Inst{20-16} = Rss32{4-0}; bits <5> Rdd32; let Inst{4-0} = Rdd32{4-0}; } -class Enc_5ab2be : OpcodeHexagon { - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_bd6011 : OpcodeHexagon { - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_cb9321 : OpcodeHexagon { - bits <16> Ii; - let Inst{27-21} = Ii{15-9}; - let Inst{13-5} = Ii{8-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_a56825 : OpcodeHexagon { - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <5> Rtt32; - let Inst{12-8} = Rtt32{4-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; +class Enc_134437 : OpcodeHexagon { + bits <2> Qs4; + let Inst{9-8} = Qs4{1-0}; + bits <2> Qt4; + let Inst{23-22} = Qt4{1-0}; + bits <2> Qd4; + let Inst{1-0} = Qd4{1-0}; } class Enc_140c83 : OpcodeHexagon { bits <10> Ii; @@ -62,6 +209,103 @@ class Enc_140c83 : OpcodeHexagon { bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; } +class Enc_143445 : OpcodeHexagon { + bits <13> Ii; + let Inst{26-25} = Ii{12-11}; + let Inst{13-13} = Ii{10-10}; + let Inst{7-0} = Ii{9-2}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; +} +class Enc_143a3c : OpcodeHexagon { + bits <6> Ii; + let Inst{13-8} = Ii{5-0}; + bits <6> II; + let Inst{23-21} = II{5-3}; + let Inst{7-5} = II{2-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rxx32; + let Inst{4-0} = Rxx32{4-0}; +} +class Enc_14640c : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <5> n1; + let Inst{28-28} = n1{4-4}; + let Inst{24-22} = n1{3-1}; + let Inst{13-13} = n1{0-0}; +} +class Enc_14d27a : OpcodeHexagon { + bits <5> II; + let Inst{12-8} = II{4-0}; + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; +} +class Enc_152467 : OpcodeHexagon { + bits <5> Ii; + let Inst{8-5} = Ii{4-1}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_158beb : OpcodeHexagon { + bits <2> Qs4; + let Inst{6-5} = Qs4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vv32; + let Inst{4-0} = Vv32{4-0}; +} +class Enc_163a3c : OpcodeHexagon { + bits <7> Ii; + let Inst{12-7} = Ii{6-1}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{4-0} = Rt32{4-0}; +} +class Enc_16c48b : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vw32; + let Inst{4-0} = Vw32{4-0}; +} +class Enc_178717 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <6> n1; + let Inst{28-28} = n1{5-5}; + let Inst{25-23} = n1{4-2}; + let Inst{13-13} = n1{1-1}; + let Inst{8-8} = n1{0-0}; +} +class Enc_179b35 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rx32; + let Inst{4-0} = Rx32{4-0}; +} class Enc_18c338 : OpcodeHexagon { bits <8> Ii; let Inst{12-5} = Ii{7-0}; @@ -71,109 +315,271 @@ class Enc_18c338 : OpcodeHexagon { bits <5> Rdd32; let Inst{4-0} = Rdd32{4-0}; } -class Enc_be32a5 : OpcodeHexagon { +class Enc_1a9974 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; + bits <2> Pv4; + let Inst{6-5} = Pv4{1-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; -} -class Enc_ea23e4 : OpcodeHexagon { + bits <5> Ru32; + let Inst{12-8} = Ru32{4-0}; bits <5> Rtt32; - let Inst{12-8} = Rtt32{4-0}; + let Inst{4-0} = Rtt32{4-0}; +} +class Enc_1aa186 : OpcodeHexagon { bits <5> Rss32; let Inst{20-16} = Rss32{4-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; -} -class Enc_e3b0c4 : OpcodeHexagon { - -} -class Enc_ea4c54 : OpcodeHexagon { - bits <2> Pu4; - let Inst{6-5} = Pu4{1-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; bits <5> Rt32; let Inst{12-8} = Rt32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; + bits <5> Rxx32; + let Inst{4-0} = Rxx32{4-0}; } -class Enc_e38e1f : OpcodeHexagon { - bits <8> Ii; - let Inst{12-5} = Ii{7-0}; - bits <2> Pu4; - let Inst{22-21} = Pu4{1-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_9b0bc1 : OpcodeHexagon { - bits <2> Pu4; - let Inst{6-5} = Pu4{1-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_90cd8b : OpcodeHexagon { - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_3a3d62 : OpcodeHexagon { - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; -} -class Enc_0cb018 : OpcodeHexagon { - bits <5> Cs32; - let Inst{20-16} = Cs32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_51436c : OpcodeHexagon { - bits <16> Ii; - let Inst{23-22} = Ii{15-14}; - let Inst{13-0} = Ii{13-0}; +class Enc_1aaec1 : OpcodeHexagon { + bits <3> Ii; + let Inst{10-8} = Ii{2-0}; + bits <3> Os8; + let Inst{2-0} = Os8{2-0}; bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } -class Enc_bd811a : OpcodeHexagon { +class Enc_1b64fb : OpcodeHexagon { + bits <16> Ii; + let Inst{26-25} = Ii{15-14}; + let Inst{20-16} = Ii{13-9}; + let Inst{13-13} = Ii{8-8}; + let Inst{7-0} = Ii{7-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; +} +class Enc_1bd127 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <3> Rt8; + let Inst{18-16} = Rt8{2-0}; + bits <5> Vdddd32; + let Inst{4-0} = Vdddd32{4-0}; +} +class Enc_1cf4ca : OpcodeHexagon { + bits <6> Ii; + let Inst{17-16} = Ii{5-4}; + let Inst{6-3} = Ii{3-0}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; +} +class Enc_1de724 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <4> n1; + let Inst{28-28} = n1{3-3}; + let Inst{24-22} = n1{2-0}; +} +class Enc_1ef990 : OpcodeHexagon { + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_1f19b5 : OpcodeHexagon { + bits <5> Ii; + let Inst{9-5} = Ii{4-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_1f5ba6 : OpcodeHexagon { + bits <4> Rd16; + let Inst{3-0} = Rd16{3-0}; +} +class Enc_1f5d8f : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Ryy32; + let Inst{4-0} = Ryy32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_211aaa : OpcodeHexagon { + bits <11> Ii; + let Inst{26-25} = Ii{10-9}; + let Inst{13-5} = Ii{8-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; - bits <5> Cd32; - let Inst{4-0} = Cd32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; } -class Enc_5e87ce : OpcodeHexagon { +class Enc_217147 : OpcodeHexagon { + bits <2> Qv4; + let Inst{23-22} = Qv4{1-0}; +} +class Enc_222336 : OpcodeHexagon { + bits <4> Ii; + let Inst{8-5} = Ii{3-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_223005 : OpcodeHexagon { + bits <6> Ii; + let Inst{6-3} = Ii{5-2}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_226535 : OpcodeHexagon { + bits <8> Ii; + let Inst{12-7} = Ii{7-2}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{4-0} = Rt32{4-0}; +} +class Enc_22c845 : OpcodeHexagon { + bits <14> Ii; + let Inst{10-0} = Ii{13-3}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_2301d6 : OpcodeHexagon { + bits <6> Ii; + let Inst{20-16} = Ii{5-1}; + let Inst{8-8} = Ii{0-0}; + bits <2> Pt4; + let Inst{10-9} = Pt4{1-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_245865 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{23-19} = Vv32{4-0}; + bits <3> Rt8; + let Inst{18-16} = Rt8{2-0}; + bits <5> Vx32; + let Inst{4-0} = Vx32{4-0}; +} +class Enc_24a7dc : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{23-19} = Vv32{4-0}; + bits <3> Rt8; + let Inst{18-16} = Rt8{2-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; +} +class Enc_25bef0 : OpcodeHexagon { bits <16> Ii; - let Inst{23-22} = Ii{15-14}; + let Inst{26-25} = Ii{15-14}; let Inst{20-16} = Ii{13-9}; let Inst{13-5} = Ii{8-0}; bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; } -class Enc_fcf7a7 : OpcodeHexagon { - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; +class Enc_263841 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; bits <5> Rtt32; - let Inst{12-8} = Rtt32{4-0}; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_277737 : OpcodeHexagon { + bits <8> Ii; + let Inst{22-21} = Ii{7-6}; + let Inst{13-13} = Ii{5-5}; + let Inst{7-5} = Ii{4-2}; + bits <5> Ru32; + let Inst{4-0} = Ru32{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{12-8} = Rd32{4-0}; +} +class Enc_27b757 : OpcodeHexagon { + bits <4> Ii; + let Inst{13-13} = Ii{3-3}; + let Inst{10-8} = Ii{2-0}; + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; +} +class Enc_27fd0e : OpcodeHexagon { + bits <6> Ii; + let Inst{8-5} = Ii{5-2}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_284ebb : OpcodeHexagon { + bits <2> Ps4; + let Inst{17-16} = Ps4{1-0}; + bits <2> Pt4; + let Inst{9-8} = Pt4{1-0}; bits <2> Pd4; let Inst{1-0} = Pd4{1-0}; } -class Enc_88c16c : OpcodeHexagon { - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <5> Rtt32; - let Inst{12-8} = Rtt32{4-0}; - bits <5> Rxx32; - let Inst{4-0} = Rxx32{4-0}; +class Enc_28a2dc : OpcodeHexagon { + bits <5> Ii; + let Inst{12-8} = Ii{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rx32; + let Inst{4-0} = Rx32{4-0}; +} +class Enc_28dcbb : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vvv32; + let Inst{4-0} = Vvv32{4-0}; +} +class Enc_2a3787 : OpcodeHexagon { + bits <13> Ii; + let Inst{26-25} = Ii{12-11}; + let Inst{13-5} = Ii{10-2}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_2a7b91 : OpcodeHexagon { + bits <6> Ii; + let Inst{20-16} = Ii{5-1}; + let Inst{8-8} = Ii{0-0}; + bits <2> Pt4; + let Inst{10-9} = Pt4{1-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_2ae154 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rx32; + let Inst{4-0} = Rx32{4-0}; } class Enc_2b3f60 : OpcodeHexagon { bits <5> Rss32; @@ -185,6 +591,98 @@ class Enc_2b3f60 : OpcodeHexagon { bits <2> Px4; let Inst{6-5} = Px4{1-0}; } +class Enc_2b518f : OpcodeHexagon { + bits <32> Ii; + let Inst{27-16} = Ii{31-20}; + let Inst{13-0} = Ii{19-6}; +} +class Enc_2bae10 : OpcodeHexagon { + bits <4> Ii; + let Inst{10-8} = Ii{3-1}; + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; + bits <4> Rd16; + let Inst{3-0} = Rd16{3-0}; +} +class Enc_2d7491 : OpcodeHexagon { + bits <13> Ii; + let Inst{26-25} = Ii{12-11}; + let Inst{13-5} = Ii{10-2}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_2d829e : OpcodeHexagon { + bits <14> Ii; + let Inst{10-0} = Ii{13-3}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} +class Enc_2df31d : OpcodeHexagon { + bits <8> Ii; + let Inst{9-4} = Ii{7-2}; + bits <4> Rd16; + let Inst{3-0} = Rd16{3-0}; +} +class Enc_2e1979 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; + bits <2> Pv4; + let Inst{6-5} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_2ea740 : OpcodeHexagon { + bits <4> Ii; + let Inst{13-13} = Ii{3-3}; + let Inst{10-8} = Ii{2-0}; + bits <2> Qv4; + let Inst{12-11} = Qv4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; +} +class Enc_2ebe3b : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_2f2f04 : OpcodeHexagon { + bits <1> Ii; + let Inst{5-5} = Ii{0-0}; + bits <5> Vuu32; + let Inst{12-8} = Vuu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; +} +class Enc_2fbf3c : OpcodeHexagon { + bits <3> Ii; + let Inst{10-8} = Ii{2-0}; + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; + bits <4> Rd16; + let Inst{3-0} = Rd16{3-0}; +} +class Enc_310ba1 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vx32; + let Inst{4-0} = Vx32{4-0}; +} class Enc_311abd : OpcodeHexagon { bits <5> Ii; let Inst{12-8} = Ii{4-0}; @@ -193,103 +691,64 @@ class Enc_311abd : OpcodeHexagon { bits <5> Rdd32; let Inst{4-0} = Rdd32{4-0}; } -class Enc_c2b48e : OpcodeHexagon { - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <2> Pd4; - let Inst{1-0} = Pd4{1-0}; -} -class Enc_08d755 : OpcodeHexagon { - bits <8> Ii; - let Inst{12-5} = Ii{7-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <2> Pd4; - let Inst{1-0} = Pd4{1-0}; -} -class Enc_02553a : OpcodeHexagon { - bits <7> Ii; - let Inst{11-5} = Ii{6-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <2> Pd4; - let Inst{1-0} = Pd4{1-0}; -} -class Enc_f0cca7 : OpcodeHexagon { - bits <8> Ii; - let Inst{12-5} = Ii{7-0}; - bits <6> II; - let Inst{20-16} = II{5-1}; - let Inst{13-13} = II{0-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; -} -class Enc_9cdba7 : OpcodeHexagon { - bits <8> Ii; - let Inst{12-5} = Ii{7-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; -} -class Enc_a05677 : OpcodeHexagon { +class Enc_31aa6a : OpcodeHexagon { bits <5> Ii; - let Inst{12-8} = Ii{4-0}; + let Inst{6-3} = Ii{4-1}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_31db33 : OpcodeHexagon { + bits <2> Qt4; + let Inst{6-5} = Qt4{1-0}; + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_322e1b : OpcodeHexagon { + bits <6> Ii; + let Inst{22-21} = Ii{5-4}; + let Inst{13-13} = Ii{3-3}; + let Inst{7-5} = Ii{2-0}; + bits <6> II; + let Inst{23-23} = II{5-5}; + let Inst{4-0} = II{4-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; bits <5> Rd32; + let Inst{12-8} = Rd32{4-0}; +} +class Enc_323f2d : OpcodeHexagon { + bits <6> II; + let Inst{11-8} = II{5-2}; + let Inst{6-5} = II{1-0}; + bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; + bits <5> Re32; + let Inst{20-16} = Re32{4-0}; } -class Enc_2b518f : OpcodeHexagon { - bits <32> Ii; - let Inst{27-16} = Ii{31-20}; - let Inst{13-0} = Ii{19-6}; -} -class Enc_fb6577 : OpcodeHexagon { +class Enc_329361 : OpcodeHexagon { bits <2> Pu4; - let Inst{9-8} = Pu4{1-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_b8c967 : OpcodeHexagon { - bits <8> Ii; - let Inst{12-5} = Ii{7-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_667b39 : OpcodeHexagon { - bits <5> Css32; - let Inst{20-16} = Css32{4-0}; + let Inst{6-5} = Pu4{1-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; bits <5> Rdd32; let Inst{4-0} = Rdd32{4-0}; } -class Enc_0ed752 : OpcodeHexagon { - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <5> Cdd32; - let Inst{4-0} = Cdd32{4-0}; -} -class Enc_03833b : OpcodeHexagon { - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <2> Pd4; - let Inst{1-0} = Pd4{1-0}; -} -class Enc_0d8adb : OpcodeHexagon { +class Enc_33f8ba : OpcodeHexagon { bits <8> Ii; - let Inst{12-5} = Ii{7-0}; - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <2> Pd4; - let Inst{1-0} = Pd4{1-0}; + let Inst{12-8} = Ii{7-3}; + let Inst{4-2} = Ii{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; } class Enc_3680c2 : OpcodeHexagon { bits <7> Ii; @@ -299,6 +758,156 @@ class Enc_3680c2 : OpcodeHexagon { bits <2> Pd4; let Inst{1-0} = Pd4{1-0}; } +class Enc_3694bd : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; + bits <5> n1; + let Inst{29-29} = n1{4-4}; + let Inst{26-25} = n1{3-2}; + let Inst{23-22} = n1{1-0}; +} +class Enc_372c9d : OpcodeHexagon { + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <3> Os8; + let Inst{2-0} = Os8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_395cc4 : OpcodeHexagon { + bits <7> Ii; + let Inst{6-3} = Ii{6-3}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_397f23 : OpcodeHexagon { + bits <8> Ii; + let Inst{13-13} = Ii{7-7}; + let Inst{7-3} = Ii{6-2}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; +} +class Enc_399e12 : OpcodeHexagon { + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; + bits <3> Rdd8; + let Inst{2-0} = Rdd8{2-0}; +} +class Enc_3a2484 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <4> n1; + let Inst{28-28} = n1{3-3}; + let Inst{24-23} = n1{2-1}; + let Inst{13-13} = n1{0-0}; +} +class Enc_3a3d62 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_3b7631 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vdddd32; + let Inst{4-0} = Vdddd32{4-0}; + bits <3> Rx8; + let Inst{18-16} = Rx8{2-0}; +} +class Enc_3d5b28 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_3d6d37 : OpcodeHexagon { + bits <2> Qs4; + let Inst{6-5} = Qs4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vvv32; + let Inst{12-8} = Vvv32{4-0}; + bits <5> Vw32; + let Inst{4-0} = Vw32{4-0}; +} +class Enc_3d920a : OpcodeHexagon { + bits <6> Ii; + let Inst{8-5} = Ii{5-2}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_3dac0b : OpcodeHexagon { + bits <2> Qt4; + let Inst{6-5} = Qt4{1-0}; + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; +} +class Enc_3e3989 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <6> n1; + let Inst{28-28} = n1{5-5}; + let Inst{25-22} = n1{4-1}; + let Inst{8-8} = n1{0-0}; +} +class Enc_3f97c8 : OpcodeHexagon { + bits <6> Ii; + let Inst{6-3} = Ii{5-2}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_3fc427 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vxx32; + let Inst{4-0} = Vxx32{4-0}; +} +class Enc_405228 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <3> n1; + let Inst{28-28} = n1{2-2}; + let Inst{24-23} = n1{1-0}; +} class Enc_412ff0 : OpcodeHexagon { bits <5> Rss32; let Inst{20-16} = Rss32{4-0}; @@ -307,6 +916,886 @@ class Enc_412ff0 : OpcodeHexagon { bits <5> Rxx32; let Inst{12-8} = Rxx32{4-0}; } +class Enc_420cf3 : OpcodeHexagon { + bits <6> Ii; + let Inst{22-21} = Ii{5-4}; + let Inst{13-13} = Ii{3-3}; + let Inst{7-5} = Ii{2-0}; + bits <5> Ru32; + let Inst{4-0} = Ru32{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{12-8} = Rd32{4-0}; +} +class Enc_437f33 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <2> Pu4; + let Inst{6-5} = Pu4{1-0}; + bits <5> Rx32; + let Inst{4-0} = Rx32{4-0}; +} +class Enc_44215c : OpcodeHexagon { + bits <6> Ii; + let Inst{17-16} = Ii{5-4}; + let Inst{6-3} = Ii{3-0}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; +} +class Enc_44271f : OpcodeHexagon { + bits <5> Gs32; + let Inst{20-16} = Gs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_44661f : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_448f7f : OpcodeHexagon { + bits <11> Ii; + let Inst{26-25} = Ii{10-9}; + let Inst{13-13} = Ii{8-8}; + let Inst{7-0} = Ii{7-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; +} +class Enc_45364e : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_454a26 : OpcodeHexagon { + bits <2> Pt4; + let Inst{9-8} = Pt4{1-0}; + bits <2> Ps4; + let Inst{17-16} = Ps4{1-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_46c951 : OpcodeHexagon { + bits <6> Ii; + let Inst{12-7} = Ii{5-0}; + bits <5> II; + let Inst{4-0} = II{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} +class Enc_47ee5e : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; + bits <2> Pv4; + let Inst{6-5} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Ru32; + let Inst{12-8} = Ru32{4-0}; + bits <3> Nt8; + let Inst{2-0} = Nt8{2-0}; +} +class Enc_47ef61 : OpcodeHexagon { + bits <3> Ii; + let Inst{7-5} = Ii{2-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_48b75f : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_4aca3a : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; + bits <3> n1; + let Inst{29-29} = n1{2-2}; + let Inst{26-25} = n1{1-0}; +} +class Enc_4b39e4 : OpcodeHexagon { + bits <3> Ii; + let Inst{7-5} = Ii{2-0}; + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; +} +class Enc_4dc228 : OpcodeHexagon { + bits <9> Ii; + let Inst{12-8} = Ii{8-4}; + let Inst{4-3} = Ii{3-2}; + bits <10> II; + let Inst{20-16} = II{9-5}; + let Inst{7-5} = II{4-2}; + let Inst{1-0} = II{1-0}; +} +class Enc_4df4e9 : OpcodeHexagon { + bits <11> Ii; + let Inst{26-25} = Ii{10-9}; + let Inst{13-13} = Ii{8-8}; + let Inst{7-0} = Ii{7-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; +} +class Enc_4dff07 : OpcodeHexagon { + bits <2> Qv4; + let Inst{12-11} = Qv4{1-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_4e4a80 : OpcodeHexagon { + bits <2> Qs4; + let Inst{6-5} = Qs4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vvv32; + let Inst{4-0} = Vvv32{4-0}; +} +class Enc_4f4ed7 : OpcodeHexagon { + bits <18> Ii; + let Inst{26-25} = Ii{17-16}; + let Inst{20-16} = Ii{15-11}; + let Inst{13-5} = Ii{10-2}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_4f677b : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; + bits <6> II; + let Inst{11-8} = II{5-2}; + let Inst{6-5} = II{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_500cb0 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vxx32; + let Inst{4-0} = Vxx32{4-0}; +} +class Enc_509701 : OpcodeHexagon { + bits <19> Ii; + let Inst{26-25} = Ii{18-17}; + let Inst{20-16} = Ii{16-12}; + let Inst{13-5} = Ii{11-3}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_50b5ac : OpcodeHexagon { + bits <6> Ii; + let Inst{17-16} = Ii{5-4}; + let Inst{6-3} = Ii{3-0}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; +} +class Enc_50e578 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_5138b3 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vx32; + let Inst{4-0} = Vx32{4-0}; +} +class Enc_51436c : OpcodeHexagon { + bits <16> Ii; + let Inst{23-22} = Ii{15-14}; + let Inst{13-0} = Ii{13-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_51635c : OpcodeHexagon { + bits <7> Ii; + let Inst{8-4} = Ii{6-2}; + bits <4> Rd16; + let Inst{3-0} = Rd16{3-0}; +} +class Enc_527412 : OpcodeHexagon { + bits <2> Ps4; + let Inst{17-16} = Ps4{1-0}; + bits <2> Pt4; + let Inst{9-8} = Pt4{1-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_52a5dd : OpcodeHexagon { + bits <4> Ii; + let Inst{6-3} = Ii{3-0}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_53dca9 : OpcodeHexagon { + bits <6> Ii; + let Inst{11-8} = Ii{5-2}; + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; + bits <4> Rd16; + let Inst{3-0} = Rd16{3-0}; +} +class Enc_541f26 : OpcodeHexagon { + bits <18> Ii; + let Inst{26-25} = Ii{17-16}; + let Inst{20-16} = Ii{15-11}; + let Inst{13-13} = Ii{10-10}; + let Inst{7-0} = Ii{9-2}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; +} +class Enc_55355c : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Ru32; + let Inst{12-8} = Ru32{4-0}; + bits <5> Rtt32; + let Inst{4-0} = Rtt32{4-0}; +} +class Enc_569cfe : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vx32; + let Inst{4-0} = Vx32{4-0}; +} +class Enc_57a33e : OpcodeHexagon { + bits <9> Ii; + let Inst{13-13} = Ii{8-8}; + let Inst{7-3} = Ii{7-3}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; +} +class Enc_585242 : OpcodeHexagon { + bits <6> Ii; + let Inst{13-13} = Ii{5-5}; + let Inst{7-3} = Ii{4-0}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; +} +class Enc_58a8bf : OpcodeHexagon { + bits <3> Ii; + let Inst{10-8} = Ii{2-0}; + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_5a18b3 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; + bits <5> n1; + let Inst{29-29} = n1{4-4}; + let Inst{26-25} = n1{3-2}; + let Inst{22-22} = n1{1-1}; + let Inst{13-13} = n1{0-0}; +} +class Enc_5ab2be : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_5bdd42 : OpcodeHexagon { + bits <7> Ii; + let Inst{8-5} = Ii{6-3}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_5c124a : OpcodeHexagon { + bits <19> Ii; + let Inst{26-25} = Ii{18-17}; + let Inst{20-16} = Ii{16-12}; + let Inst{13-13} = Ii{11-11}; + let Inst{7-0} = Ii{10-3}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; +} +class Enc_5ccba9 : OpcodeHexagon { + bits <8> Ii; + let Inst{12-7} = Ii{7-2}; + bits <6> II; + let Inst{13-13} = II{5-5}; + let Inst{4-0} = II{4-0}; + bits <2> Pv4; + let Inst{6-5} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} +class Enc_5cd7e9 : OpcodeHexagon { + bits <12> Ii; + let Inst{26-25} = Ii{11-10}; + let Inst{13-5} = Ii{9-1}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Ryy32; + let Inst{4-0} = Ryy32{4-0}; +} +class Enc_5d6c34 : OpcodeHexagon { + bits <6> Ii; + let Inst{13-8} = Ii{5-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_5de85f : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; +} +class Enc_5e2823 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_5e8512 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vxx32; + let Inst{4-0} = Vxx32{4-0}; +} +class Enc_5e87ce : OpcodeHexagon { + bits <16> Ii; + let Inst{23-22} = Ii{15-14}; + let Inst{20-16} = Ii{13-9}; + let Inst{13-5} = Ii{8-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_5eac98 : OpcodeHexagon { + bits <6> Ii; + let Inst{13-8} = Ii{5-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_607661 : OpcodeHexagon { + bits <6> Ii; + let Inst{12-7} = Ii{5-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_6185fe : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; + bits <6> II; + let Inst{11-8} = II{5-2}; + let Inst{6-5} = II{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_61f0b0 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rxx32; + let Inst{4-0} = Rxx32{4-0}; +} +class Enc_621fba : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Gd32; + let Inst{4-0} = Gd32{4-0}; +} +class Enc_625deb : OpcodeHexagon { + bits <4> Ii; + let Inst{10-8} = Ii{3-1}; + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; + bits <4> Rt16; + let Inst{3-0} = Rt16{3-0}; +} +class Enc_6339d5 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; + bits <2> Pv4; + let Inst{6-5} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Ru32; + let Inst{12-8} = Ru32{4-0}; + bits <5> Rt32; + let Inst{4-0} = Rt32{4-0}; +} +class Enc_63eaeb : OpcodeHexagon { + bits <2> Ii; + let Inst{1-0} = Ii{1-0}; + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; +} +class Enc_6413b6 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; + bits <5> n1; + let Inst{29-29} = n1{4-4}; + let Inst{26-25} = n1{3-2}; + let Inst{23-23} = n1{1-1}; + let Inst{13-13} = n1{0-0}; +} +class Enc_645d54 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{5-5} = Ii{0-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_65d691 : OpcodeHexagon { + bits <2> Ps4; + let Inst{17-16} = Ps4{1-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_65f095 : OpcodeHexagon { + bits <6> Ii; + let Inst{6-3} = Ii{5-2}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_667b39 : OpcodeHexagon { + bits <5> Css32; + let Inst{20-16} = Css32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_668704 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <5> n1; + let Inst{28-28} = n1{4-4}; + let Inst{25-22} = n1{3-0}; +} +class Enc_66bce1 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <4> Rd16; + let Inst{11-8} = Rd16{3-0}; +} +class Enc_690862 : OpcodeHexagon { + bits <13> Ii; + let Inst{26-25} = Ii{12-11}; + let Inst{13-13} = Ii{10-10}; + let Inst{7-0} = Ii{9-2}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; +} +class Enc_691712 : OpcodeHexagon { + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_69d63b : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; +} +class Enc_6a5972 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <4> Rt16; + let Inst{11-8} = Rt16{3-0}; +} +class Enc_6b197f : OpcodeHexagon { + bits <4> Ii; + let Inst{8-5} = Ii{3-0}; + bits <5> Ryy32; + let Inst{4-0} = Ryy32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_6baed4 : OpcodeHexagon { + bits <3> Ii; + let Inst{10-8} = Ii{2-0}; + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_6c9440 : OpcodeHexagon { + bits <10> Ii; + let Inst{21-21} = Ii{9-9}; + let Inst{13-5} = Ii{8-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_6c9ee0 : OpcodeHexagon { + bits <3> Ii; + let Inst{10-8} = Ii{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_6f70ca : OpcodeHexagon { + bits <8> Ii; + let Inst{8-4} = Ii{7-3}; +} +class Enc_6f83e7 : OpcodeHexagon { + bits <2> Qv4; + let Inst{23-22} = Qv4{1-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_70b24b : OpcodeHexagon { + bits <6> Ii; + let Inst{8-5} = Ii{5-2}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_70fb07 : OpcodeHexagon { + bits <6> Ii; + let Inst{13-8} = Ii{5-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rxx32; + let Inst{4-0} = Rxx32{4-0}; +} +class Enc_71bb9b : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; +} +class Enc_71f1b4 : OpcodeHexagon { + bits <6> Ii; + let Inst{8-5} = Ii{5-2}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_7222b7 : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <2> Qd4; + let Inst{1-0} = Qd4{1-0}; +} +class Enc_724154 : OpcodeHexagon { + bits <6> II; + let Inst{5-0} = II{5-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; + bits <5> Re32; + let Inst{20-16} = Re32{4-0}; +} +class Enc_729ff7 : OpcodeHexagon { + bits <3> Ii; + let Inst{7-5} = Ii{2-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_733b27 : OpcodeHexagon { + bits <5> Ii; + let Inst{8-5} = Ii{4-1}; + bits <2> Pt4; + let Inst{10-9} = Pt4{1-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_736575 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <4> n1; + let Inst{28-28} = n1{3-3}; + let Inst{25-23} = n1{2-0}; +} +class Enc_74aef2 : OpcodeHexagon { + bits <4> Ii; + let Inst{8-5} = Ii{3-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Ryy32; + let Inst{4-0} = Ryy32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_74d4e5 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_770858 : OpcodeHexagon { + bits <2> Ps4; + let Inst{6-5} = Ps4{1-0}; + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_784502 : OpcodeHexagon { + bits <3> Ii; + let Inst{10-8} = Ii{2-0}; + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <3> Os8; + let Inst{2-0} = Os8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_78cbf0 : OpcodeHexagon { + bits <18> Ii; + let Inst{26-25} = Ii{17-16}; + let Inst{20-16} = Ii{15-11}; + let Inst{13-13} = Ii{10-10}; + let Inst{7-0} = Ii{9-2}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; +} +class Enc_78e566 : OpcodeHexagon { + bits <2> Pt4; + let Inst{9-8} = Pt4{1-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_79b8c8 : OpcodeHexagon { + bits <6> Ii; + let Inst{6-3} = Ii{5-2}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_7a0ea6 : OpcodeHexagon { + bits <4> Rd16; + let Inst{3-0} = Rd16{3-0}; + bits <1> n1; + let Inst{9-9} = n1{0-0}; +} +class Enc_7b523d : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{23-19} = Vv32{4-0}; + bits <3> Rt8; + let Inst{18-16} = Rt8{2-0}; + bits <5> Vxx32; + let Inst{4-0} = Vxx32{4-0}; +} +class Enc_7b7ba8 : OpcodeHexagon { + bits <2> Qu4; + let Inst{9-8} = Qu4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_7e5a82 : OpcodeHexagon { + bits <5> Ii; + let Inst{12-8} = Ii{4-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_7eaeb6 : OpcodeHexagon { + bits <6> Ii; + let Inst{6-3} = Ii{5-2}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_7eb485 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{6-6} = Ii{0-0}; + bits <6> II; + let Inst{5-0} = II{5-0}; + bits <5> Ru32; + let Inst{20-16} = Ru32{4-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; +} +class Enc_7eee72 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_7f1a05 : OpcodeHexagon { + bits <5> Ru32; + let Inst{4-0} = Ru32{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Ry32; + let Inst{12-8} = Ry32{4-0}; +} +class Enc_7fa7f6 : OpcodeHexagon { + bits <6> II; + let Inst{11-8} = II{5-2}; + let Inst{6-5} = II{1-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; + bits <5> Re32; + let Inst{20-16} = Re32{4-0}; +} +class Enc_800e04 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <6> n1; + let Inst{28-28} = n1{5-5}; + let Inst{25-22} = n1{4-1}; + let Inst{13-13} = n1{0-0}; +} +class Enc_802dc0 : OpcodeHexagon { + bits <1> Ii; + let Inst{8-8} = Ii{0-0}; + bits <2> Qv4; + let Inst{23-22} = Qv4{1-0}; +} +class Enc_81ac1d : OpcodeHexagon { + bits <24> Ii; + let Inst{24-16} = Ii{23-15}; + let Inst{13-1} = Ii{14-2}; +} +class Enc_8203bb : OpcodeHexagon { + bits <6> Ii; + let Inst{12-7} = Ii{5-0}; + bits <8> II; + let Inst{13-13} = II{7-7}; + let Inst{6-0} = II{6-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} +class Enc_830e5d : OpcodeHexagon { + bits <8> Ii; + let Inst{12-5} = Ii{7-0}; + bits <8> II; + let Inst{22-16} = II{7-1}; + let Inst{13-13} = II{0-0}; + bits <2> Pu4; + let Inst{24-23} = Pu4{1-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} class Enc_831a7d : OpcodeHexagon { bits <5> Rss32; let Inst{20-16} = Rss32{4-0}; @@ -317,6 +1806,1138 @@ class Enc_831a7d : OpcodeHexagon { bits <2> Pe4; let Inst{6-5} = Pe4{1-0}; } +class Enc_83ee64 : OpcodeHexagon { + bits <5> Ii; + let Inst{12-8} = Ii{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_84b2cd : OpcodeHexagon { + bits <8> Ii; + let Inst{12-7} = Ii{7-2}; + bits <5> II; + let Inst{4-0} = II{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} +class Enc_84bff1 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_84d359 : OpcodeHexagon { + bits <4> Ii; + let Inst{3-0} = Ii{3-0}; + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; +} +class Enc_85bf58 : OpcodeHexagon { + bits <7> Ii; + let Inst{6-3} = Ii{6-3}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_864a5a : OpcodeHexagon { + bits <9> Ii; + let Inst{12-8} = Ii{8-4}; + let Inst{4-3} = Ii{3-2}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} +class Enc_865390 : OpcodeHexagon { + bits <3> Ii; + let Inst{10-8} = Ii{2-0}; + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_86a14b : OpcodeHexagon { + bits <8> Ii; + let Inst{7-3} = Ii{7-3}; + bits <3> Rdd8; + let Inst{2-0} = Rdd8{2-0}; +} +class Enc_87c142 : OpcodeHexagon { + bits <7> Ii; + let Inst{8-4} = Ii{6-2}; + bits <4> Rt16; + let Inst{3-0} = Rt16{3-0}; +} +class Enc_88c16c : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rxx32; + let Inst{4-0} = Rxx32{4-0}; +} +class Enc_88d4d9 : OpcodeHexagon { + bits <2> Pu4; + let Inst{9-8} = Pu4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} +class Enc_890909 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; + bits <2> Pe4; + let Inst{6-5} = Pe4{1-0}; +} +class Enc_895bd9 : OpcodeHexagon { + bits <2> Qu4; + let Inst{9-8} = Qu4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vx32; + let Inst{4-0} = Vx32{4-0}; +} +class Enc_8b8927 : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vv32; + let Inst{4-0} = Vv32{4-0}; +} +class Enc_8b8d61 : OpcodeHexagon { + bits <6> Ii; + let Inst{22-21} = Ii{5-4}; + let Inst{13-13} = Ii{3-3}; + let Inst{7-5} = Ii{2-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Ru32; + let Inst{4-0} = Ru32{4-0}; + bits <5> Rd32; + let Inst{12-8} = Rd32{4-0}; +} +class Enc_8bcba4 : OpcodeHexagon { + bits <6> II; + let Inst{5-0} = II{5-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Re32; + let Inst{20-16} = Re32{4-0}; +} +class Enc_8c2412 : OpcodeHexagon { + bits <2> Ps4; + let Inst{6-5} = Ps4{1-0}; + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; +} +class Enc_8c6530 : OpcodeHexagon { + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <2> Pu4; + let Inst{6-5} = Pu4{1-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_8d8a30 : OpcodeHexagon { + bits <4> Ii; + let Inst{13-13} = Ii{3-3}; + let Inst{10-8} = Ii{2-0}; + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_8dbdfe : OpcodeHexagon { + bits <8> Ii; + let Inst{13-13} = Ii{7-7}; + let Inst{7-3} = Ii{6-2}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; +} +class Enc_8dbe85 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_8dec2e : OpcodeHexagon { + bits <5> Ii; + let Inst{12-8} = Ii{4-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_8df4be : OpcodeHexagon { + bits <17> Ii; + let Inst{26-25} = Ii{16-15}; + let Inst{20-16} = Ii{14-10}; + let Inst{13-5} = Ii{9-1}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_8e583a : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <5> n1; + let Inst{28-28} = n1{4-4}; + let Inst{25-23} = n1{3-1}; + let Inst{13-13} = n1{0-0}; +} +class Enc_90cd8b : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_91b9fe : OpcodeHexagon { + bits <5> Ii; + let Inst{6-3} = Ii{4-1}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_927852 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_928ca1 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_935d9b : OpcodeHexagon { + bits <5> Ii; + let Inst{6-3} = Ii{4-1}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_93af4c : OpcodeHexagon { + bits <7> Ii; + let Inst{10-4} = Ii{6-0}; + bits <4> Rx16; + let Inst{3-0} = Rx16{3-0}; +} +class Enc_95441f : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <2> Qd4; + let Inst{1-0} = Qd4{1-0}; +} +class Enc_96ce4f : OpcodeHexagon { + bits <4> Ii; + let Inst{6-3} = Ii{3-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_97d666 : OpcodeHexagon { + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; + bits <4> Rd16; + let Inst{3-0} = Rd16{3-0}; +} +class Enc_989021 : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vy32; + let Inst{12-8} = Vy32{4-0}; + bits <5> Vx32; + let Inst{4-0} = Vx32{4-0}; +} +class Enc_98c0b8 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; + bits <2> Pv4; + let Inst{6-5} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_9a33d5 : OpcodeHexagon { + bits <7> Ii; + let Inst{6-3} = Ii{6-3}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_9ac432 : OpcodeHexagon { + bits <2> Ps4; + let Inst{17-16} = Ps4{1-0}; + bits <2> Pt4; + let Inst{9-8} = Pt4{1-0}; + bits <2> Pu4; + let Inst{7-6} = Pu4{1-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_9b0bc1 : OpcodeHexagon { + bits <2> Pu4; + let Inst{6-5} = Pu4{1-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_9be1de : OpcodeHexagon { + bits <2> Qs4; + let Inst{6-5} = Qs4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vw32; + let Inst{4-0} = Vw32{4-0}; +} +class Enc_9cdba7 : OpcodeHexagon { + bits <8> Ii; + let Inst{12-5} = Ii{7-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_9d1247 : OpcodeHexagon { + bits <7> Ii; + let Inst{8-5} = Ii{6-3}; + bits <2> Pt4; + let Inst{10-9} = Pt4{1-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_9e2e1c : OpcodeHexagon { + bits <5> Ii; + let Inst{8-5} = Ii{4-1}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Ryy32; + let Inst{4-0} = Ryy32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_9e4c3f : OpcodeHexagon { + bits <6> II; + let Inst{13-8} = II{5-0}; + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rd16; + let Inst{19-16} = Rd16{3-0}; +} +class Enc_9ea4cf : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{6-6} = Ii{0-0}; + bits <6> II; + let Inst{5-0} = II{5-0}; + bits <5> Ru32; + let Inst{20-16} = Ru32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; +} +class Enc_9fae8a : OpcodeHexagon { + bits <6> Ii; + let Inst{13-8} = Ii{5-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_a05677 : OpcodeHexagon { + bits <5> Ii; + let Inst{12-8} = Ii{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_a1640c : OpcodeHexagon { + bits <6> Ii; + let Inst{13-8} = Ii{5-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_a198f6 : OpcodeHexagon { + bits <7> Ii; + let Inst{10-5} = Ii{6-1}; + bits <2> Pt4; + let Inst{12-11} = Pt4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_a1e29d : OpcodeHexagon { + bits <5> Ii; + let Inst{12-8} = Ii{4-0}; + bits <5> II; + let Inst{22-21} = II{4-3}; + let Inst{7-5} = II{2-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rx32; + let Inst{4-0} = Rx32{4-0}; +} +class Enc_a21d47 : OpcodeHexagon { + bits <6> Ii; + let Inst{10-5} = Ii{5-0}; + bits <2> Pt4; + let Inst{12-11} = Pt4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_a255dc : OpcodeHexagon { + bits <3> Ii; + let Inst{10-8} = Ii{2-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_a27588 : OpcodeHexagon { + bits <11> Ii; + let Inst{26-25} = Ii{10-9}; + let Inst{13-5} = Ii{8-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Ryy32; + let Inst{4-0} = Ryy32{4-0}; +} +class Enc_a30110 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{23-19} = Vv32{4-0}; + bits <3> Rt8; + let Inst{18-16} = Rt8{2-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_a42857 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <5> n1; + let Inst{28-28} = n1{4-4}; + let Inst{24-22} = n1{3-1}; + let Inst{8-8} = n1{0-0}; +} +class Enc_a4ef14 : OpcodeHexagon { + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_a51a9a : OpcodeHexagon { + bits <8> Ii; + let Inst{12-8} = Ii{7-3}; + let Inst{4-2} = Ii{2-0}; +} +class Enc_a56825 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_a568d4 : OpcodeHexagon { + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rx32; + let Inst{4-0} = Rx32{4-0}; +} +class Enc_a5ed8a : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_a641d0 : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vvv32; + let Inst{12-8} = Vvv32{4-0}; + bits <5> Vw32; + let Inst{4-0} = Vw32{4-0}; +} +class Enc_a6853f : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; + bits <6> n1; + let Inst{29-29} = n1{5-5}; + let Inst{26-25} = n1{4-3}; + let Inst{23-22} = n1{2-1}; + let Inst{13-13} = n1{0-0}; +} +class Enc_a6ce9c : OpcodeHexagon { + bits <6> Ii; + let Inst{3-0} = Ii{5-2}; + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; +} +class Enc_a7341a : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vx32; + let Inst{4-0} = Vx32{4-0}; +} +class Enc_a75aa6 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; +} +class Enc_a7b8e8 : OpcodeHexagon { + bits <6> Ii; + let Inst{22-21} = Ii{5-4}; + let Inst{13-13} = Ii{3-3}; + let Inst{7-5} = Ii{2-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_a803e0 : OpcodeHexagon { + bits <7> Ii; + let Inst{12-7} = Ii{6-1}; + bits <8> II; + let Inst{13-13} = II{7-7}; + let Inst{6-0} = II{6-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} +class Enc_a90628 : OpcodeHexagon { + bits <2> Qv4; + let Inst{23-22} = Qv4{1-0}; + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vx32; + let Inst{4-0} = Vx32{4-0}; +} +class Enc_a94f3b : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; + bits <2> Pe4; + let Inst{6-5} = Pe4{1-0}; +} +class Enc_aad80c : OpcodeHexagon { + bits <5> Vuu32; + let Inst{12-8} = Vuu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; +} +class Enc_acd6ed : OpcodeHexagon { + bits <9> Ii; + let Inst{10-5} = Ii{8-3}; + bits <2> Pt4; + let Inst{12-11} = Pt4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_ad1831 : OpcodeHexagon { + bits <16> Ii; + let Inst{26-25} = Ii{15-14}; + let Inst{20-16} = Ii{13-9}; + let Inst{13-13} = Ii{8-8}; + let Inst{7-0} = Ii{7-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; +} +class Enc_ad1c74 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; +} +class Enc_ad9bef : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vxx32; + let Inst{4-0} = Vxx32{4-0}; +} +class Enc_adf111 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <2> Qx4; + let Inst{1-0} = Qx4{1-0}; +} +class Enc_b00112 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; +} +class Enc_b05839 : OpcodeHexagon { + bits <7> Ii; + let Inst{8-5} = Ii{6-3}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_b087ac : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_b0e9d8 : OpcodeHexagon { + bits <10> Ii; + let Inst{21-21} = Ii{9-9}; + let Inst{13-5} = Ii{8-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rx32; + let Inst{4-0} = Rx32{4-0}; +} +class Enc_b15941 : OpcodeHexagon { + bits <4> Ii; + let Inst{6-3} = Ii{3-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_b1e1fb : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <5> n1; + let Inst{28-28} = n1{4-4}; + let Inst{25-23} = n1{3-1}; + let Inst{8-8} = n1{0-0}; +} +class Enc_b388cf : OpcodeHexagon { + bits <5> Ii; + let Inst{12-8} = Ii{4-0}; + bits <5> II; + let Inst{22-21} = II{4-3}; + let Inst{7-5} = II{2-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_b38ffc : OpcodeHexagon { + bits <4> Ii; + let Inst{11-8} = Ii{3-0}; + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; + bits <4> Rt16; + let Inst{3-0} = Rt16{3-0}; +} +class Enc_b43b67 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; + bits <2> Qx4; + let Inst{6-5} = Qx4{1-0}; +} +class Enc_b4e6cf : OpcodeHexagon { + bits <10> Ii; + let Inst{21-21} = Ii{9-9}; + let Inst{13-5} = Ii{8-0}; + bits <5> Ru32; + let Inst{4-0} = Ru32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_b62ef7 : OpcodeHexagon { + bits <3> Ii; + let Inst{10-8} = Ii{2-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_b72622 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{5-5} = Ii{0-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rxx32; + let Inst{4-0} = Rxx32{4-0}; +} +class Enc_b78edd : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <4> n1; + let Inst{28-28} = n1{3-3}; + let Inst{24-23} = n1{2-1}; + let Inst{8-8} = n1{0-0}; +} +class Enc_b7fad3 : OpcodeHexagon { + bits <2> Pv4; + let Inst{9-8} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_b8309d : OpcodeHexagon { + bits <9> Ii; + let Inst{8-3} = Ii{8-3}; + bits <3> Rtt8; + let Inst{2-0} = Rtt8{2-0}; +} +class Enc_b84c4c : OpcodeHexagon { + bits <6> Ii; + let Inst{13-8} = Ii{5-0}; + bits <6> II; + let Inst{23-21} = II{5-3}; + let Inst{7-5} = II{2-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_b886fd : OpcodeHexagon { + bits <5> Ii; + let Inst{6-3} = Ii{4-1}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_b8c967 : OpcodeHexagon { + bits <8> Ii; + let Inst{12-5} = Ii{7-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_b909d2 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <7> n1; + let Inst{28-28} = n1{6-6}; + let Inst{25-22} = n1{5-2}; + let Inst{13-13} = n1{1-1}; + let Inst{8-8} = n1{0-0}; +} +class Enc_b91167 : OpcodeHexagon { + bits <2> Ii; + let Inst{6-5} = Ii{1-0}; + bits <5> Vuu32; + let Inst{12-8} = Vuu32{4-0}; + bits <5> Vvv32; + let Inst{20-16} = Vvv32{4-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; +} +class Enc_b97f71 : OpcodeHexagon { + bits <6> Ii; + let Inst{8-5} = Ii{5-2}; + bits <2> Pt4; + let Inst{10-9} = Pt4{1-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_b9c5fb : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_bc03e5 : OpcodeHexagon { + bits <17> Ii; + let Inst{26-25} = Ii{16-15}; + let Inst{20-16} = Ii{14-10}; + let Inst{13-13} = Ii{9-9}; + let Inst{7-0} = Ii{8-1}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; +} +class Enc_bd0b33 : OpcodeHexagon { + bits <10> Ii; + let Inst{21-21} = Ii{9-9}; + let Inst{13-5} = Ii{8-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_bd1cbc : OpcodeHexagon { + bits <5> Ii; + let Inst{8-5} = Ii{4-1}; + bits <5> Ryy32; + let Inst{4-0} = Ryy32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_bd6011 : OpcodeHexagon { + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_bd811a : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Cd32; + let Inst{4-0} = Cd32{4-0}; +} +class Enc_bddee3 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vyyyy32; + let Inst{4-0} = Vyyyy32{4-0}; + bits <3> Rx8; + let Inst{18-16} = Rx8{2-0}; +} +class Enc_be32a5 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_bfbf03 : OpcodeHexagon { + bits <2> Qs4; + let Inst{9-8} = Qs4{1-0}; + bits <2> Qd4; + let Inst{1-0} = Qd4{1-0}; +} +class Enc_c0cdde : OpcodeHexagon { + bits <9> Ii; + let Inst{13-5} = Ii{8-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_c175d0 : OpcodeHexagon { + bits <4> Ii; + let Inst{11-8} = Ii{3-0}; + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; + bits <4> Rd16; + let Inst{3-0} = Rd16{3-0}; +} +class Enc_c1d806 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; + bits <2> Qe4; + let Inst{6-5} = Qe4{1-0}; +} +class Enc_c2b48e : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_c31910 : OpcodeHexagon { + bits <8> Ii; + let Inst{23-21} = Ii{7-5}; + let Inst{13-13} = Ii{4-4}; + let Inst{7-5} = Ii{3-1}; + let Inst{3-3} = Ii{0-0}; + bits <5> II; + let Inst{12-8} = II{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_c4dc92 : OpcodeHexagon { + bits <2> Qv4; + let Inst{23-22} = Qv4{1-0}; + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_c6220b : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Ru32; + let Inst{12-8} = Ru32{4-0}; + bits <3> Nt8; + let Inst{2-0} = Nt8{2-0}; +} +class Enc_c7a204 : OpcodeHexagon { + bits <6> II; + let Inst{5-0} = II{5-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Re32; + let Inst{20-16} = Re32{4-0}; +} +class Enc_c7cd90 : OpcodeHexagon { + bits <4> Ii; + let Inst{6-3} = Ii{3-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_c85e2a : OpcodeHexagon { + bits <5> Ii; + let Inst{12-8} = Ii{4-0}; + bits <5> II; + let Inst{22-21} = II{4-3}; + let Inst{7-5} = II{2-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_c90aca : OpcodeHexagon { + bits <8> Ii; + let Inst{12-5} = Ii{7-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rx32; + let Inst{4-0} = Rx32{4-0}; +} +class Enc_c9a18e : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; +} +class Enc_c9e3bc : OpcodeHexagon { + bits <4> Ii; + let Inst{13-13} = Ii{3-3}; + let Inst{10-8} = Ii{2-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; +} +class Enc_ca3887 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; +} +class Enc_cb4b4e : OpcodeHexagon { + bits <2> Pu4; + let Inst{6-5} = Pu4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_cb785b : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; +} +class Enc_cb9321 : OpcodeHexagon { + bits <16> Ii; + let Inst{27-21} = Ii{15-9}; + let Inst{13-5} = Ii{8-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_cc449f : OpcodeHexagon { + bits <4> Ii; + let Inst{6-3} = Ii{3-0}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_cc857d : OpcodeHexagon { + bits <5> Vuu32; + let Inst{12-8} = Vuu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vx32; + let Inst{4-0} = Vx32{4-0}; +} +class Enc_cd4705 : OpcodeHexagon { + bits <3> Ii; + let Inst{7-5} = Ii{2-0}; + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vx32; + let Inst{4-0} = Vx32{4-0}; +} +class Enc_cd82bc : OpcodeHexagon { + bits <4> Ii; + let Inst{21-21} = Ii{3-3}; + let Inst{7-5} = Ii{2-0}; + bits <6> II; + let Inst{13-8} = II{5-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rx32; + let Inst{4-0} = Rx32{4-0}; +} +class Enc_cda00a : OpcodeHexagon { + bits <12> Ii; + let Inst{19-16} = Ii{11-8}; + let Inst{12-5} = Ii{7-0}; + bits <2> Pu4; + let Inst{22-21} = Pu4{1-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_ce6828 : OpcodeHexagon { + bits <14> Ii; + let Inst{26-25} = Ii{13-12}; + let Inst{13-13} = Ii{11-11}; + let Inst{7-0} = Ii{10-3}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; +} +class Enc_cf1927 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <3> Os8; + let Inst{2-0} = Os8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_d15d19 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} class Enc_d2216a : OpcodeHexagon { bits <5> Rss32; let Inst{20-16} = Rss32{4-0}; @@ -335,977 +2956,6 @@ class Enc_d2c7f1 : OpcodeHexagon { bits <2> Pe4; let Inst{6-5} = Pe4{1-0}; } -class Enc_5eac98 : OpcodeHexagon { - bits <6> Ii; - let Inst{13-8} = Ii{5-0}; - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; -} -class Enc_927852 : OpcodeHexagon { - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; -} -class Enc_7e5a82 : OpcodeHexagon { - bits <5> Ii; - let Inst{12-8} = Ii{4-0}; - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; -} -class Enc_65d691 : OpcodeHexagon { - bits <2> Ps4; - let Inst{17-16} = Ps4{1-0}; - bits <2> Pd4; - let Inst{1-0} = Pd4{1-0}; -} -class Enc_454a26 : OpcodeHexagon { - bits <2> Pt4; - let Inst{9-8} = Pt4{1-0}; - bits <2> Ps4; - let Inst{17-16} = Ps4{1-0}; - bits <2> Pd4; - let Inst{1-0} = Pd4{1-0}; -} -class Enc_5d6c34 : OpcodeHexagon { - bits <6> Ii; - let Inst{13-8} = Ii{5-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <2> Pd4; - let Inst{1-0} = Pd4{1-0}; -} -class Enc_cb4b4e : OpcodeHexagon { - bits <2> Pu4; - let Inst{6-5} = Pu4{1-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; -} -class Enc_cda00a : OpcodeHexagon { - bits <12> Ii; - let Inst{19-16} = Ii{11-8}; - let Inst{12-5} = Ii{7-0}; - bits <2> Pu4; - let Inst{22-21} = Pu4{1-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_bd0b33 : OpcodeHexagon { - bits <10> Ii; - let Inst{21-21} = Ii{9-9}; - let Inst{13-5} = Ii{8-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <2> Pd4; - let Inst{1-0} = Pd4{1-0}; -} -class Enc_c0cdde : OpcodeHexagon { - bits <9> Ii; - let Inst{13-5} = Ii{8-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <2> Pd4; - let Inst{1-0} = Pd4{1-0}; -} -class Enc_78e566 : OpcodeHexagon { - bits <2> Pt4; - let Inst{9-8} = Pt4{1-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; -} -class Enc_830e5d : OpcodeHexagon { - bits <8> Ii; - let Inst{12-5} = Ii{7-0}; - bits <8> II; - let Inst{22-16} = II{7-1}; - let Inst{13-13} = II{0-0}; - bits <2> Pu4; - let Inst{24-23} = Pu4{1-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_f5e933 : OpcodeHexagon { - bits <2> Ps4; - let Inst{17-16} = Ps4{1-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_48b75f : OpcodeHexagon { - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <2> Pd4; - let Inst{1-0} = Pd4{1-0}; -} -class Enc_527412 : OpcodeHexagon { - bits <2> Ps4; - let Inst{17-16} = Ps4{1-0}; - bits <2> Pt4; - let Inst{9-8} = Pt4{1-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_329361 : OpcodeHexagon { - bits <2> Pu4; - let Inst{6-5} = Pu4{1-0}; - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <5> Rtt32; - let Inst{12-8} = Rtt32{4-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; -} -class Enc_284ebb : OpcodeHexagon { - bits <2> Ps4; - let Inst{17-16} = Ps4{1-0}; - bits <2> Pt4; - let Inst{9-8} = Pt4{1-0}; - bits <2> Pd4; - let Inst{1-0} = Pd4{1-0}; -} -class Enc_607661 : OpcodeHexagon { - bits <6> Ii; - let Inst{12-7} = Ii{5-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_9ac432 : OpcodeHexagon { - bits <2> Ps4; - let Inst{17-16} = Ps4{1-0}; - bits <2> Pt4; - let Inst{9-8} = Pt4{1-0}; - bits <2> Pu4; - let Inst{7-6} = Pu4{1-0}; - bits <2> Pd4; - let Inst{1-0} = Pd4{1-0}; -} -class Enc_1f19b5 : OpcodeHexagon { - bits <5> Ii; - let Inst{9-5} = Ii{4-0}; - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <2> Pd4; - let Inst{1-0} = Pd4{1-0}; -} -class Enc_e6c957 : OpcodeHexagon { - bits <10> Ii; - let Inst{21-21} = Ii{9-9}; - let Inst{13-5} = Ii{8-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; -} -class Enc_83ee64 : OpcodeHexagon { - bits <5> Ii; - let Inst{12-8} = Ii{4-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <2> Pd4; - let Inst{1-0} = Pd4{1-0}; -} -class Enc_2ae154 : OpcodeHexagon { - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Rx32; - let Inst{4-0} = Rx32{4-0}; -} -class Enc_437f33 : OpcodeHexagon { - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <2> Pu4; - let Inst{6-5} = Pu4{1-0}; - bits <5> Rx32; - let Inst{4-0} = Rx32{4-0}; -} -class Enc_6c9440 : OpcodeHexagon { - bits <10> Ii; - let Inst{21-21} = Ii{9-9}; - let Inst{13-5} = Ii{8-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_890909 : OpcodeHexagon { - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; - bits <2> Pe4; - let Inst{6-5} = Pe4{1-0}; -} -class Enc_a94f3b : OpcodeHexagon { - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; - bits <2> Pe4; - let Inst{6-5} = Pe4{1-0}; -} -class Enc_0aa344 : OpcodeHexagon { - bits <5> Gss32; - let Inst{20-16} = Gss32{4-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; -} -class Enc_44271f : OpcodeHexagon { - bits <5> Gs32; - let Inst{20-16} = Gs32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_ed5027 : OpcodeHexagon { - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <5> Gdd32; - let Inst{4-0} = Gdd32{4-0}; -} -class Enc_621fba : OpcodeHexagon { - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Gd32; - let Inst{4-0} = Gd32{4-0}; -} -class Enc_81ac1d : OpcodeHexagon { - bits <24> Ii; - let Inst{24-16} = Ii{23-15}; - let Inst{13-1} = Ii{14-2}; -} -class Enc_daea09 : OpcodeHexagon { - bits <17> Ii; - let Inst{23-22} = Ii{16-15}; - let Inst{20-16} = Ii{14-10}; - let Inst{13-13} = Ii{9-9}; - let Inst{7-1} = Ii{8-2}; - bits <2> Pu4; - let Inst{9-8} = Pu4{1-0}; -} -class Enc_ecbcc8 : OpcodeHexagon { - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; -} -class Enc_88d4d9 : OpcodeHexagon { - bits <2> Pu4; - let Inst{9-8} = Pu4{1-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; -} -class Enc_0fa531 : OpcodeHexagon { - bits <15> Ii; - let Inst{21-21} = Ii{14-14}; - let Inst{13-13} = Ii{13-13}; - let Inst{11-1} = Ii{12-2}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; -} -class Enc_4dc228 : OpcodeHexagon { - bits <9> Ii; - let Inst{12-8} = Ii{8-4}; - let Inst{4-3} = Ii{3-2}; - bits <10> II; - let Inst{20-16} = II{9-5}; - let Inst{7-5} = II{4-2}; - let Inst{1-0} = II{1-0}; -} -class Enc_864a5a : OpcodeHexagon { - bits <9> Ii; - let Inst{12-8} = Ii{8-4}; - let Inst{4-3} = Ii{3-2}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; -} -class Enc_a51a9a : OpcodeHexagon { - bits <8> Ii; - let Inst{12-8} = Ii{7-3}; - let Inst{4-2} = Ii{2-0}; -} -class Enc_33f8ba : OpcodeHexagon { - bits <8> Ii; - let Inst{12-8} = Ii{7-3}; - let Inst{4-2} = Ii{2-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_c9a18e : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <3> Ns8; - let Inst{18-16} = Ns8{2-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; -} -class Enc_6a5972 : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <4> Rs16; - let Inst{19-16} = Rs16{3-0}; - bits <4> Rt16; - let Inst{11-8} = Rt16{3-0}; -} -class Enc_eafd18 : OpcodeHexagon { - bits <5> II; - let Inst{12-8} = II{4-0}; - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <3> Ns8; - let Inst{18-16} = Ns8{2-0}; -} -class Enc_14d27a : OpcodeHexagon { - bits <5> II; - let Inst{12-8} = II{4-0}; - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <4> Rs16; - let Inst{19-16} = Rs16{3-0}; -} -class Enc_e90a15 : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <3> Ns8; - let Inst{18-16} = Ns8{2-0}; - bits <4> n1; - let Inst{29-29} = n1{3-3}; - let Inst{26-25} = n1{2-1}; - let Inst{22-22} = n1{0-0}; -} -class Enc_5a18b3 : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <3> Ns8; - let Inst{18-16} = Ns8{2-0}; - bits <5> n1; - let Inst{29-29} = n1{4-4}; - let Inst{26-25} = n1{3-2}; - let Inst{22-22} = n1{1-1}; - let Inst{13-13} = n1{0-0}; -} -class Enc_1de724 : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <4> Rs16; - let Inst{19-16} = Rs16{3-0}; - bits <4> n1; - let Inst{28-28} = n1{3-3}; - let Inst{24-22} = n1{2-0}; -} -class Enc_14640c : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <4> Rs16; - let Inst{19-16} = Rs16{3-0}; - bits <5> n1; - let Inst{28-28} = n1{4-4}; - let Inst{24-22} = n1{3-1}; - let Inst{13-13} = n1{0-0}; -} -class Enc_668704 : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <4> Rs16; - let Inst{19-16} = Rs16{3-0}; - bits <5> n1; - let Inst{28-28} = n1{4-4}; - let Inst{25-22} = n1{3-0}; -} -class Enc_800e04 : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <4> Rs16; - let Inst{19-16} = Rs16{3-0}; - bits <6> n1; - let Inst{28-28} = n1{5-5}; - let Inst{25-22} = n1{4-1}; - let Inst{13-13} = n1{0-0}; -} -class Enc_4aca3a : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <3> Ns8; - let Inst{18-16} = Ns8{2-0}; - bits <3> n1; - let Inst{29-29} = n1{2-2}; - let Inst{26-25} = n1{1-0}; -} -class Enc_f7ea77 : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <3> Ns8; - let Inst{18-16} = Ns8{2-0}; - bits <4> n1; - let Inst{29-29} = n1{3-3}; - let Inst{26-25} = n1{2-1}; - let Inst{13-13} = n1{0-0}; -} -class Enc_405228 : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <4> Rs16; - let Inst{19-16} = Rs16{3-0}; - bits <3> n1; - let Inst{28-28} = n1{2-2}; - let Inst{24-23} = n1{1-0}; -} -class Enc_3a2484 : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <4> Rs16; - let Inst{19-16} = Rs16{3-0}; - bits <4> n1; - let Inst{28-28} = n1{3-3}; - let Inst{24-23} = n1{2-1}; - let Inst{13-13} = n1{0-0}; -} -class Enc_736575 : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <4> Rs16; - let Inst{19-16} = Rs16{3-0}; - bits <4> n1; - let Inst{28-28} = n1{3-3}; - let Inst{25-23} = n1{2-0}; -} -class Enc_8e583a : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <4> Rs16; - let Inst{19-16} = Rs16{3-0}; - bits <5> n1; - let Inst{28-28} = n1{4-4}; - let Inst{25-23} = n1{3-1}; - let Inst{13-13} = n1{0-0}; -} -class Enc_3694bd : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <3> Ns8; - let Inst{18-16} = Ns8{2-0}; - bits <5> n1; - let Inst{29-29} = n1{4-4}; - let Inst{26-25} = n1{3-2}; - let Inst{23-22} = n1{1-0}; -} -class Enc_a6853f : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <3> Ns8; - let Inst{18-16} = Ns8{2-0}; - bits <6> n1; - let Inst{29-29} = n1{5-5}; - let Inst{26-25} = n1{4-3}; - let Inst{23-22} = n1{2-1}; - let Inst{13-13} = n1{0-0}; -} -class Enc_a42857 : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <4> Rs16; - let Inst{19-16} = Rs16{3-0}; - bits <5> n1; - let Inst{28-28} = n1{4-4}; - let Inst{24-22} = n1{3-1}; - let Inst{8-8} = n1{0-0}; -} -class Enc_f6fe0b : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <4> Rs16; - let Inst{19-16} = Rs16{3-0}; - bits <6> n1; - let Inst{28-28} = n1{5-5}; - let Inst{24-22} = n1{4-2}; - let Inst{13-13} = n1{1-1}; - let Inst{8-8} = n1{0-0}; -} -class Enc_3e3989 : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <4> Rs16; - let Inst{19-16} = Rs16{3-0}; - bits <6> n1; - let Inst{28-28} = n1{5-5}; - let Inst{25-22} = n1{4-1}; - let Inst{8-8} = n1{0-0}; -} -class Enc_b909d2 : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <4> Rs16; - let Inst{19-16} = Rs16{3-0}; - bits <7> n1; - let Inst{28-28} = n1{6-6}; - let Inst{25-22} = n1{5-2}; - let Inst{13-13} = n1{1-1}; - let Inst{8-8} = n1{0-0}; -} -class Enc_f82302 : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <3> Ns8; - let Inst{18-16} = Ns8{2-0}; - bits <4> n1; - let Inst{29-29} = n1{3-3}; - let Inst{26-25} = n1{2-1}; - let Inst{23-23} = n1{0-0}; -} -class Enc_6413b6 : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <3> Ns8; - let Inst{18-16} = Ns8{2-0}; - bits <5> n1; - let Inst{29-29} = n1{4-4}; - let Inst{26-25} = n1{3-2}; - let Inst{23-23} = n1{1-1}; - let Inst{13-13} = n1{0-0}; -} -class Enc_b78edd : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <4> Rs16; - let Inst{19-16} = Rs16{3-0}; - bits <4> n1; - let Inst{28-28} = n1{3-3}; - let Inst{24-23} = n1{2-1}; - let Inst{8-8} = n1{0-0}; -} -class Enc_041d7b : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <4> Rs16; - let Inst{19-16} = Rs16{3-0}; - bits <5> n1; - let Inst{28-28} = n1{4-4}; - let Inst{24-23} = n1{3-2}; - let Inst{13-13} = n1{1-1}; - let Inst{8-8} = n1{0-0}; -} -class Enc_b1e1fb : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <4> Rs16; - let Inst{19-16} = Rs16{3-0}; - bits <5> n1; - let Inst{28-28} = n1{4-4}; - let Inst{25-23} = n1{3-1}; - let Inst{8-8} = n1{0-0}; -} -class Enc_178717 : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <4> Rs16; - let Inst{19-16} = Rs16{3-0}; - bits <6> n1; - let Inst{28-28} = n1{5-5}; - let Inst{25-23} = n1{4-2}; - let Inst{13-13} = n1{1-1}; - let Inst{8-8} = n1{0-0}; -} -class Enc_5de85f : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <3> Ns8; - let Inst{18-16} = Ns8{2-0}; -} -class Enc_9e4c3f : OpcodeHexagon { - bits <6> II; - let Inst{13-8} = II{5-0}; - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <4> Rd16; - let Inst{19-16} = Rd16{3-0}; -} -class Enc_66bce1 : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <4> Rs16; - let Inst{19-16} = Rs16{3-0}; - bits <4> Rd16; - let Inst{11-8} = Rd16{3-0}; -} -class Enc_69d63b : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <3> Ns8; - let Inst{18-16} = Ns8{2-0}; -} -class Enc_ad1c74 : OpcodeHexagon { - bits <11> Ii; - let Inst{21-20} = Ii{10-9}; - let Inst{7-1} = Ii{8-2}; - bits <4> Rs16; - let Inst{19-16} = Rs16{3-0}; -} -class Enc_a27588 : OpcodeHexagon { - bits <11> Ii; - let Inst{26-25} = Ii{10-9}; - let Inst{13-5} = Ii{8-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Ryy32; - let Inst{4-0} = Ryy32{4-0}; -} -class Enc_1f5d8f : OpcodeHexagon { - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Ryy32; - let Inst{4-0} = Ryy32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_74aef2 : OpcodeHexagon { - bits <4> Ii; - let Inst{8-5} = Ii{3-0}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Ryy32; - let Inst{4-0} = Ryy32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_6b197f : OpcodeHexagon { - bits <4> Ii; - let Inst{8-5} = Ii{3-0}; - bits <5> Ryy32; - let Inst{4-0} = Ryy32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_5cd7e9 : OpcodeHexagon { - bits <12> Ii; - let Inst{26-25} = Ii{11-10}; - let Inst{13-5} = Ii{9-1}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Ryy32; - let Inst{4-0} = Ryy32{4-0}; -} -class Enc_9e2e1c : OpcodeHexagon { - bits <5> Ii; - let Inst{8-5} = Ii{4-1}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Ryy32; - let Inst{4-0} = Ryy32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_bd1cbc : OpcodeHexagon { - bits <5> Ii; - let Inst{8-5} = Ii{4-1}; - bits <5> Ryy32; - let Inst{4-0} = Ryy32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_de0214 : OpcodeHexagon { - bits <12> Ii; - let Inst{26-25} = Ii{11-10}; - let Inst{13-5} = Ii{9-1}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_74d4e5 : OpcodeHexagon { - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_e83554 : OpcodeHexagon { - bits <5> Ii; - let Inst{8-5} = Ii{4-1}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_152467 : OpcodeHexagon { - bits <5> Ii; - let Inst{8-5} = Ii{4-1}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_2d7491 : OpcodeHexagon { - bits <13> Ii; - let Inst{26-25} = Ii{12-11}; - let Inst{13-5} = Ii{10-2}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; -} -class Enc_7eee72 : OpcodeHexagon { - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_70b24b : OpcodeHexagon { - bits <6> Ii; - let Inst{8-5} = Ii{5-2}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_71f1b4 : OpcodeHexagon { - bits <6> Ii; - let Inst{8-5} = Ii{5-2}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_211aaa : OpcodeHexagon { - bits <11> Ii; - let Inst{26-25} = Ii{10-9}; - let Inst{13-5} = Ii{8-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_e0a47a : OpcodeHexagon { - bits <4> Ii; - let Inst{8-5} = Ii{3-0}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_222336 : OpcodeHexagon { - bits <4> Ii; - let Inst{8-5} = Ii{3-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_25bef0 : OpcodeHexagon { - bits <16> Ii; - let Inst{26-25} = Ii{15-14}; - let Inst{20-16} = Ii{13-9}; - let Inst{13-5} = Ii{8-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_fa3ba4 : OpcodeHexagon { - bits <14> Ii; - let Inst{26-25} = Ii{13-12}; - let Inst{13-5} = Ii{11-3}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; -} -class Enc_b05839 : OpcodeHexagon { - bits <7> Ii; - let Inst{8-5} = Ii{6-3}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_5bdd42 : OpcodeHexagon { - bits <7> Ii; - let Inst{8-5} = Ii{6-3}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_509701 : OpcodeHexagon { - bits <19> Ii; - let Inst{26-25} = Ii{18-17}; - let Inst{20-16} = Ii{16-12}; - let Inst{13-5} = Ii{11-3}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; -} -class Enc_8df4be : OpcodeHexagon { - bits <17> Ii; - let Inst{26-25} = Ii{16-15}; - let Inst{20-16} = Ii{14-10}; - let Inst{13-5} = Ii{9-1}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_2a3787 : OpcodeHexagon { - bits <13> Ii; - let Inst{26-25} = Ii{12-11}; - let Inst{13-5} = Ii{10-2}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_27fd0e : OpcodeHexagon { - bits <6> Ii; - let Inst{8-5} = Ii{5-2}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_3d920a : OpcodeHexagon { - bits <6> Ii; - let Inst{8-5} = Ii{5-2}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_4f4ed7 : OpcodeHexagon { - bits <18> Ii; - let Inst{26-25} = Ii{17-16}; - let Inst{20-16} = Ii{15-11}; - let Inst{13-5} = Ii{10-2}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_a21d47 : OpcodeHexagon { - bits <6> Ii; - let Inst{10-5} = Ii{5-0}; - bits <2> Pt4; - let Inst{12-11} = Pt4{1-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_f4413a : OpcodeHexagon { - bits <4> Ii; - let Inst{8-5} = Ii{3-0}; - bits <2> Pt4; - let Inst{10-9} = Pt4{1-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_acd6ed : OpcodeHexagon { - bits <9> Ii; - let Inst{10-5} = Ii{8-3}; - bits <2> Pt4; - let Inst{12-11} = Pt4{1-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; -} -class Enc_9d1247 : OpcodeHexagon { - bits <7> Ii; - let Inst{8-5} = Ii{6-3}; - bits <2> Pt4; - let Inst{10-9} = Pt4{1-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_a198f6 : OpcodeHexagon { - bits <7> Ii; - let Inst{10-5} = Ii{6-1}; - bits <2> Pt4; - let Inst{12-11} = Pt4{1-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_733b27 : OpcodeHexagon { - bits <5> Ii; - let Inst{8-5} = Ii{4-1}; - bits <2> Pt4; - let Inst{10-9} = Pt4{1-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_f82eaf : OpcodeHexagon { - bits <8> Ii; - let Inst{10-5} = Ii{7-2}; - bits <2> Pt4; - let Inst{12-11} = Pt4{1-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_b97f71 : OpcodeHexagon { - bits <6> Ii; - let Inst{8-5} = Ii{5-2}; - bits <2> Pt4; - let Inst{10-9} = Pt4{1-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} class Enc_d44e31 : OpcodeHexagon { bits <6> Ii; let Inst{12-7} = Ii{5-0}; @@ -1314,108 +2964,68 @@ class Enc_d44e31 : OpcodeHexagon { bits <5> Rt32; let Inst{4-0} = Rt32{4-0}; } -class Enc_163a3c : OpcodeHexagon { - bits <7> Ii; - let Inst{12-7} = Ii{6-1}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; +class Enc_d483b9 : OpcodeHexagon { + bits <1> Ii; + let Inst{5-5} = Ii{0-0}; + bits <5> Vuu32; + let Inst{12-8} = Vuu32{4-0}; bits <5> Rt32; - let Inst{4-0} = Rt32{4-0}; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vxx32; + let Inst{4-0} = Vxx32{4-0}; } -class Enc_226535 : OpcodeHexagon { - bits <8> Ii; - let Inst{12-7} = Ii{7-2}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; +class Enc_d50cd3 : OpcodeHexagon { + bits <3> Ii; + let Inst{7-5} = Ii{2-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_d5c73f : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; bits <5> Rt32; - let Inst{4-0} = Rt32{4-0}; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; } -class Enc_46c951 : OpcodeHexagon { +class Enc_d6990d : OpcodeHexagon { + bits <5> Vuu32; + let Inst{12-8} = Vuu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vxx32; + let Inst{4-0} = Vxx32{4-0}; +} +class Enc_d7a65e : OpcodeHexagon { bits <6> Ii; let Inst{12-7} = Ii{5-0}; - bits <5> II; + bits <6> II; + let Inst{13-13} = II{5-5}; let Inst{4-0} = II{4-0}; + bits <2> Pv4; + let Inst{6-5} = Pv4{1-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; } -class Enc_e66a97 : OpcodeHexagon { - bits <7> Ii; - let Inst{12-7} = Ii{6-1}; - bits <5> II; - let Inst{4-0} = II{4-0}; +class Enc_d7bc34 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <3> Rt8; + let Inst{18-16} = Rt8{2-0}; + bits <5> Vyyyy32; + let Inst{4-0} = Vyyyy32{4-0}; +} +class Enc_d7dc10 : OpcodeHexagon { bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; -} -class Enc_84b2cd : OpcodeHexagon { - bits <8> Ii; - let Inst{12-7} = Ii{7-2}; - bits <5> II; - let Inst{4-0} = II{4-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; -} -class Enc_f394d3 : OpcodeHexagon { - bits <6> II; - let Inst{11-8} = II{5-2}; - let Inst{6-5} = II{1-0}; - bits <5> Ryy32; - let Inst{4-0} = Ryy32{4-0}; - bits <5> Re32; - let Inst{20-16} = Re32{4-0}; -} -class Enc_04c959 : OpcodeHexagon { - bits <2> Ii; - let Inst{13-13} = Ii{1-1}; - let Inst{7-7} = Ii{0-0}; - bits <6> II; - let Inst{11-8} = II{5-2}; - let Inst{6-5} = II{1-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Ryy32; - let Inst{4-0} = Ryy32{4-0}; -} -class Enc_323f2d : OpcodeHexagon { - bits <6> II; - let Inst{11-8} = II{5-2}; - let Inst{6-5} = II{1-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; - bits <5> Re32; - let Inst{20-16} = Re32{4-0}; -} -class Enc_4f677b : OpcodeHexagon { - bits <2> Ii; - let Inst{13-13} = Ii{1-1}; - let Inst{7-7} = Ii{0-0}; - bits <6> II; - let Inst{11-8} = II{5-2}; - let Inst{6-5} = II{1-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_7fa7f6 : OpcodeHexagon { - bits <6> II; - let Inst{11-8} = II{5-2}; - let Inst{6-5} = II{1-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; - bits <5> Re32; - let Inst{20-16} = Re32{4-0}; -} -class Enc_6185fe : OpcodeHexagon { - bits <2> Ii; - let Inst{13-13} = Ii{1-1}; - let Inst{7-7} = Ii{0-0}; - bits <6> II; - let Inst{11-8} = II{5-2}; - let Inst{6-5} = II{1-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; } class Enc_da664b : OpcodeHexagon { bits <2> Ii; @@ -1428,354 +3038,6 @@ class Enc_da664b : OpcodeHexagon { bits <5> Rd32; let Inst{4-0} = Rd32{4-0}; } -class Enc_84bff1 : OpcodeHexagon { - bits <2> Ii; - let Inst{13-13} = Ii{1-1}; - let Inst{7-7} = Ii{0-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; -} -class Enc_2301d6 : OpcodeHexagon { - bits <6> Ii; - let Inst{20-16} = Ii{5-1}; - let Inst{8-8} = Ii{0-0}; - bits <2> Pt4; - let Inst{10-9} = Pt4{1-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_2e1979 : OpcodeHexagon { - bits <2> Ii; - let Inst{13-13} = Ii{1-1}; - let Inst{7-7} = Ii{0-0}; - bits <2> Pv4; - let Inst{6-5} = Pv4{1-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_2a7b91 : OpcodeHexagon { - bits <6> Ii; - let Inst{20-16} = Ii{5-1}; - let Inst{8-8} = Ii{0-0}; - bits <2> Pt4; - let Inst{10-9} = Pt4{1-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; -} -class Enc_98c0b8 : OpcodeHexagon { - bits <2> Ii; - let Inst{13-13} = Ii{1-1}; - let Inst{7-7} = Ii{0-0}; - bits <2> Pv4; - let Inst{6-5} = Pv4{1-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; -} -class Enc_b7fad3 : OpcodeHexagon { - bits <2> Pv4; - let Inst{9-8} = Pv4{1-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; -} -class Enc_a75aa6 : OpcodeHexagon { - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; -} -class Enc_c90aca : OpcodeHexagon { - bits <8> Ii; - let Inst{12-5} = Ii{7-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rx32; - let Inst{4-0} = Rx32{4-0}; -} -class Enc_61f0b0 : OpcodeHexagon { - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Rxx32; - let Inst{4-0} = Rxx32{4-0}; -} -class Enc_a568d4 : OpcodeHexagon { - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rx32; - let Inst{4-0} = Rx32{4-0}; -} -class Enc_3d5b28 : OpcodeHexagon { - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_322e1b : OpcodeHexagon { - bits <6> Ii; - let Inst{22-21} = Ii{5-4}; - let Inst{13-13} = Ii{3-3}; - let Inst{7-5} = Ii{2-0}; - bits <6> II; - let Inst{23-23} = II{5-5}; - let Inst{4-0} = II{4-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rd32; - let Inst{12-8} = Rd32{4-0}; -} -class Enc_420cf3 : OpcodeHexagon { - bits <6> Ii; - let Inst{22-21} = Ii{5-4}; - let Inst{13-13} = Ii{3-3}; - let Inst{7-5} = Ii{2-0}; - bits <5> Ru32; - let Inst{4-0} = Ru32{4-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rd32; - let Inst{12-8} = Rd32{4-0}; -} -class Enc_277737 : OpcodeHexagon { - bits <8> Ii; - let Inst{22-21} = Ii{7-6}; - let Inst{13-13} = Ii{5-5}; - let Inst{7-5} = Ii{4-2}; - bits <5> Ru32; - let Inst{4-0} = Ru32{4-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rd32; - let Inst{12-8} = Rd32{4-0}; -} -class Enc_a7b8e8 : OpcodeHexagon { - bits <6> Ii; - let Inst{22-21} = Ii{5-4}; - let Inst{13-13} = Ii{3-3}; - let Inst{7-5} = Ii{2-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_7f1a05 : OpcodeHexagon { - bits <5> Ru32; - let Inst{4-0} = Ru32{4-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Ry32; - let Inst{12-8} = Ry32{4-0}; -} -class Enc_1b64fb : OpcodeHexagon { - bits <16> Ii; - let Inst{26-25} = Ii{15-14}; - let Inst{20-16} = Ii{13-9}; - let Inst{13-13} = Ii{8-8}; - let Inst{7-0} = Ii{7-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; -} -class Enc_ad1831 : OpcodeHexagon { - bits <16> Ii; - let Inst{26-25} = Ii{15-14}; - let Inst{20-16} = Ii{13-9}; - let Inst{13-13} = Ii{8-8}; - let Inst{7-0} = Ii{7-0}; - bits <3> Nt8; - let Inst{10-8} = Nt8{2-0}; -} -class Enc_5c124a : OpcodeHexagon { - bits <19> Ii; - let Inst{26-25} = Ii{18-17}; - let Inst{20-16} = Ii{16-12}; - let Inst{13-13} = Ii{11-11}; - let Inst{7-0} = Ii{10-3}; - bits <5> Rtt32; - let Inst{12-8} = Rtt32{4-0}; -} -class Enc_fda92c : OpcodeHexagon { - bits <17> Ii; - let Inst{26-25} = Ii{16-15}; - let Inst{20-16} = Ii{14-10}; - let Inst{13-13} = Ii{9-9}; - let Inst{7-0} = Ii{8-1}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; -} -class Enc_bc03e5 : OpcodeHexagon { - bits <17> Ii; - let Inst{26-25} = Ii{16-15}; - let Inst{20-16} = Ii{14-10}; - let Inst{13-13} = Ii{9-9}; - let Inst{7-0} = Ii{8-1}; - bits <3> Nt8; - let Inst{10-8} = Nt8{2-0}; -} -class Enc_541f26 : OpcodeHexagon { - bits <18> Ii; - let Inst{26-25} = Ii{17-16}; - let Inst{20-16} = Ii{15-11}; - let Inst{13-13} = Ii{10-10}; - let Inst{7-0} = Ii{9-2}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; -} -class Enc_78cbf0 : OpcodeHexagon { - bits <18> Ii; - let Inst{26-25} = Ii{17-16}; - let Inst{20-16} = Ii{15-11}; - let Inst{13-13} = Ii{10-10}; - let Inst{7-0} = Ii{9-2}; - bits <3> Nt8; - let Inst{10-8} = Nt8{2-0}; -} -class Enc_47ef61 : OpcodeHexagon { - bits <3> Ii; - let Inst{7-5} = Ii{2-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_22c845 : OpcodeHexagon { - bits <14> Ii; - let Inst{10-0} = Ii{13-3}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_70fb07 : OpcodeHexagon { - bits <6> Ii; - let Inst{13-8} = Ii{5-0}; - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <5> Rxx32; - let Inst{4-0} = Rxx32{4-0}; -} -class Enc_28a2dc : OpcodeHexagon { - bits <5> Ii; - let Inst{12-8} = Ii{4-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rx32; - let Inst{4-0} = Rx32{4-0}; -} -class Enc_12b6e9 : OpcodeHexagon { - bits <4> Ii; - let Inst{11-8} = Ii{3-0}; - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; -} -class Enc_1aa186 : OpcodeHexagon { - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Rxx32; - let Inst{4-0} = Rxx32{4-0}; -} -class Enc_8dec2e : OpcodeHexagon { - bits <5> Ii; - let Inst{12-8} = Ii{4-0}; - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_b388cf : OpcodeHexagon { - bits <5> Ii; - let Inst{12-8} = Ii{4-0}; - bits <5> II; - let Inst{22-21} = II{4-3}; - let Inst{7-5} = II{2-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_e07374 : OpcodeHexagon { - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rtt32; - let Inst{12-8} = Rtt32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_b84c4c : OpcodeHexagon { - bits <6> Ii; - let Inst{13-8} = Ii{5-0}; - bits <6> II; - let Inst{23-21} = II{5-3}; - let Inst{7-5} = II{2-0}; - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; -} -class Enc_a1e29d : OpcodeHexagon { - bits <5> Ii; - let Inst{12-8} = Ii{4-0}; - bits <5> II; - let Inst{22-21} = II{4-3}; - let Inst{7-5} = II{2-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rx32; - let Inst{4-0} = Rx32{4-0}; -} -class Enc_179b35 : OpcodeHexagon { - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rtt32; - let Inst{12-8} = Rtt32{4-0}; - bits <5> Rx32; - let Inst{4-0} = Rx32{4-0}; -} -class Enc_143a3c : OpcodeHexagon { - bits <6> Ii; - let Inst{13-8} = Ii{5-0}; - bits <6> II; - let Inst{23-21} = II{5-3}; - let Inst{7-5} = II{2-0}; - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <5> Rxx32; - let Inst{4-0} = Rxx32{4-0}; -} -class Enc_c85e2a : OpcodeHexagon { - bits <5> Ii; - let Inst{12-8} = Ii{4-0}; - bits <5> II; - let Inst{22-21} = II{4-3}; - let Inst{7-5} = II{2-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} class Enc_da8d43 : OpcodeHexagon { bits <6> Ii; let Inst{13-13} = Ii{5-5}; @@ -1787,55 +3049,137 @@ class Enc_da8d43 : OpcodeHexagon { bits <5> Rt32; let Inst{12-8} = Rt32{4-0}; } -class Enc_cc449f : OpcodeHexagon { - bits <4> Ii; - let Inst{6-3} = Ii{3-0}; - bits <2> Pv4; - let Inst{1-0} = Pv4{1-0}; +class Enc_daea09 : OpcodeHexagon { + bits <17> Ii; + let Inst{23-22} = Ii{16-15}; + let Inst{20-16} = Ii{14-10}; + let Inst{13-13} = Ii{9-9}; + let Inst{7-1} = Ii{8-2}; + bits <2> Pu4; + let Inst{9-8} = Pu4{1-0}; +} +class Enc_db40cd : OpcodeHexagon { + bits <6> Ii; + let Inst{6-3} = Ii{5-2}; bits <5> Rt32; let Inst{12-8} = Rt32{4-0}; bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } -class Enc_585242 : OpcodeHexagon { - bits <6> Ii; - let Inst{13-13} = Ii{5-5}; - let Inst{7-3} = Ii{4-0}; - bits <2> Pv4; - let Inst{1-0} = Pv4{1-0}; +class Enc_dbd70c : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <2> Pu4; + let Inst{6-5} = Pu4{1-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_dd766a : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; +} +class Enc_de0214 : OpcodeHexagon { + bits <12> Ii; + let Inst{26-25} = Ii{11-10}; + let Inst{13-5} = Ii{9-1}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; - bits <3> Nt8; - let Inst{10-8} = Nt8{2-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; } -class Enc_52a5dd : OpcodeHexagon { +class Enc_e07374 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_e0820b : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <2> Qs4; + let Inst{6-5} = Qs4{1-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_e0a47a : OpcodeHexagon { bits <4> Ii; - let Inst{6-3} = Ii{3-0}; - bits <2> Pv4; - let Inst{1-0} = Pv4{1-0}; + let Inst{8-5} = Ii{3-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_e26546 : OpcodeHexagon { + bits <5> Ii; + let Inst{6-3} = Ii{4-1}; bits <3> Nt8; let Inst{10-8} = Nt8{2-0}; bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } -class Enc_57a33e : OpcodeHexagon { - bits <9> Ii; - let Inst{13-13} = Ii{8-8}; - let Inst{7-3} = Ii{7-3}; - bits <2> Pv4; - let Inst{1-0} = Pv4{1-0}; +class Enc_e38e1f : OpcodeHexagon { + bits <8> Ii; + let Inst{12-5} = Ii{7-0}; + bits <2> Pu4; + let Inst{22-21} = Pu4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_e39bb2 : OpcodeHexagon { + bits <6> Ii; + let Inst{9-4} = Ii{5-0}; + bits <4> Rd16; + let Inst{3-0} = Rd16{3-0}; +} +class Enc_e3b0c4 : OpcodeHexagon { + +} +class Enc_e66a97 : OpcodeHexagon { + bits <7> Ii; + let Inst{12-7} = Ii{6-1}; + bits <5> II; + let Inst{4-0} = II{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} +class Enc_e6abcf : OpcodeHexagon { bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; bits <5> Rtt32; let Inst{12-8} = Rtt32{4-0}; } -class Enc_9a33d5 : OpcodeHexagon { - bits <7> Ii; - let Inst{6-3} = Ii{6-3}; - bits <2> Pv4; - let Inst{1-0} = Pv4{1-0}; - bits <5> Rtt32; - let Inst{12-8} = Rtt32{4-0}; +class Enc_e6c957 : OpcodeHexagon { + bits <10> Ii; + let Inst{21-21} = Ii{9-9}; + let Inst{13-5} = Ii{8-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_e7581c : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_e83554 : OpcodeHexagon { + bits <5> Ii; + let Inst{8-5} = Ii{4-1}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } @@ -1850,186 +3194,16 @@ class Enc_e8c45e : OpcodeHexagon { bits <5> Rt32; let Inst{12-8} = Rt32{4-0}; } -class Enc_b886fd : OpcodeHexagon { - bits <5> Ii; - let Inst{6-3} = Ii{4-1}; - bits <2> Pv4; - let Inst{1-0} = Pv4{1-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_f44229 : OpcodeHexagon { - bits <7> Ii; - let Inst{13-13} = Ii{6-6}; - let Inst{7-3} = Ii{5-1}; - bits <2> Pv4; - let Inst{1-0} = Pv4{1-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <3> Nt8; - let Inst{10-8} = Nt8{2-0}; -} -class Enc_31aa6a : OpcodeHexagon { - bits <5> Ii; - let Inst{6-3} = Ii{4-1}; - bits <2> Pv4; - let Inst{1-0} = Pv4{1-0}; - bits <3> Nt8; - let Inst{10-8} = Nt8{2-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_397f23 : OpcodeHexagon { - bits <8> Ii; - let Inst{13-13} = Ii{7-7}; - let Inst{7-3} = Ii{6-2}; - bits <2> Pv4; - let Inst{1-0} = Pv4{1-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; -} -class Enc_7eaeb6 : OpcodeHexagon { - bits <6> Ii; - let Inst{6-3} = Ii{5-2}; - bits <2> Pv4; - let Inst{1-0} = Pv4{1-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_8dbdfe : OpcodeHexagon { - bits <8> Ii; - let Inst{13-13} = Ii{7-7}; - let Inst{7-3} = Ii{6-2}; - bits <2> Pv4; - let Inst{1-0} = Pv4{1-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <3> Nt8; - let Inst{10-8} = Nt8{2-0}; -} -class Enc_65f095 : OpcodeHexagon { - bits <6> Ii; - let Inst{6-3} = Ii{5-2}; - bits <2> Pv4; - let Inst{1-0} = Pv4{1-0}; - bits <3> Nt8; - let Inst{10-8} = Nt8{2-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_448f7f : OpcodeHexagon { +class Enc_e90a15 : OpcodeHexagon { bits <11> Ii; - let Inst{26-25} = Ii{10-9}; - let Inst{13-13} = Ii{8-8}; - let Inst{7-0} = Ii{7-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; -} -class Enc_d5c73f : OpcodeHexagon { - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_b15941 : OpcodeHexagon { - bits <4> Ii; - let Inst{6-3} = Ii{3-0}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_10bc21 : OpcodeHexagon { - bits <4> Ii; - let Inst{6-3} = Ii{3-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_4df4e9 : OpcodeHexagon { - bits <11> Ii; - let Inst{26-25} = Ii{10-9}; - let Inst{13-13} = Ii{8-8}; - let Inst{7-0} = Ii{7-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <3> Nt8; - let Inst{10-8} = Nt8{2-0}; -} -class Enc_8dbe85 : OpcodeHexagon { - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <3> Nt8; - let Inst{10-8} = Nt8{2-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_96ce4f : OpcodeHexagon { - bits <4> Ii; - let Inst{6-3} = Ii{3-0}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <3> Nt8; - let Inst{10-8} = Nt8{2-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_c7cd90 : OpcodeHexagon { - bits <4> Ii; - let Inst{6-3} = Ii{3-0}; - bits <3> Nt8; - let Inst{10-8} = Nt8{2-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_ce6828 : OpcodeHexagon { - bits <14> Ii; - let Inst{26-25} = Ii{13-12}; - let Inst{13-13} = Ii{11-11}; - let Inst{7-0} = Ii{10-3}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rtt32; - let Inst{12-8} = Rtt32{4-0}; -} -class Enc_928ca1 : OpcodeHexagon { - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Rtt32; - let Inst{12-8} = Rtt32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_395cc4 : OpcodeHexagon { - bits <7> Ii; - let Inst{6-3} = Ii{6-3}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Rtt32; - let Inst{12-8} = Rtt32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_85bf58 : OpcodeHexagon { - bits <7> Ii; - let Inst{6-3} = Ii{6-3}; - bits <5> Rtt32; - let Inst{12-8} = Rtt32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; + bits <4> n1; + let Inst{29-29} = n1{3-3}; + let Inst{26-25} = n1{2-1}; + let Inst{22-22} = n1{0-0}; } class Enc_e957fb : OpcodeHexagon { bits <12> Ii; @@ -2041,122 +3215,7 @@ class Enc_e957fb : OpcodeHexagon { bits <5> Rt32; let Inst{12-8} = Rt32{4-0}; } -class Enc_935d9b : OpcodeHexagon { - bits <5> Ii; - let Inst{6-3} = Ii{4-1}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_052c7d : OpcodeHexagon { - bits <5> Ii; - let Inst{6-3} = Ii{4-1}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_0d8870 : OpcodeHexagon { - bits <12> Ii; - let Inst{26-25} = Ii{11-10}; - let Inst{13-13} = Ii{9-9}; - let Inst{7-0} = Ii{8-1}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <3> Nt8; - let Inst{10-8} = Nt8{2-0}; -} -class Enc_91b9fe : OpcodeHexagon { - bits <5> Ii; - let Inst{6-3} = Ii{4-1}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <3> Nt8; - let Inst{10-8} = Nt8{2-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_e26546 : OpcodeHexagon { - bits <5> Ii; - let Inst{6-3} = Ii{4-1}; - bits <3> Nt8; - let Inst{10-8} = Nt8{2-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_143445 : OpcodeHexagon { - bits <13> Ii; - let Inst{26-25} = Ii{12-11}; - let Inst{13-13} = Ii{10-10}; - let Inst{7-0} = Ii{9-2}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; -} -class Enc_79b8c8 : OpcodeHexagon { - bits <6> Ii; - let Inst{6-3} = Ii{5-2}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_db40cd : OpcodeHexagon { - bits <6> Ii; - let Inst{6-3} = Ii{5-2}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_690862 : OpcodeHexagon { - bits <13> Ii; - let Inst{26-25} = Ii{12-11}; - let Inst{13-13} = Ii{10-10}; - let Inst{7-0} = Ii{9-2}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <3> Nt8; - let Inst{10-8} = Nt8{2-0}; -} -class Enc_3f97c8 : OpcodeHexagon { - bits <6> Ii; - let Inst{6-3} = Ii{5-2}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <3> Nt8; - let Inst{10-8} = Nt8{2-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_223005 : OpcodeHexagon { - bits <6> Ii; - let Inst{6-3} = Ii{5-2}; - bits <3> Nt8; - let Inst{10-8} = Nt8{2-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_cd82bc : OpcodeHexagon { - bits <4> Ii; - let Inst{21-21} = Ii{3-3}; - let Inst{7-5} = Ii{2-0}; - bits <6> II; - let Inst{13-8} = II{5-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rx32; - let Inst{4-0} = Rx32{4-0}; -} -class Enc_729ff7 : OpcodeHexagon { - bits <3> Ii; - let Inst{7-5} = Ii{2-0}; +class Enc_ea23e4 : OpcodeHexagon { bits <5> Rtt32; let Inst{12-8} = Rtt32{4-0}; bits <5> Rss32; @@ -2164,117 +3223,37 @@ class Enc_729ff7 : OpcodeHexagon { bits <5> Rdd32; let Inst{4-0} = Rdd32{4-0}; } -class Enc_8c6530 : OpcodeHexagon { - bits <5> Rtt32; - let Inst{12-8} = Rtt32{4-0}; - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; +class Enc_ea4c54 : OpcodeHexagon { bits <2> Pu4; let Inst{6-5} = Pu4{1-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; -} -class Enc_d50cd3 : OpcodeHexagon { - bits <3> Ii; - let Inst{7-5} = Ii{2-0}; - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <5> Rtt32; - let Inst{12-8} = Rtt32{4-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; -} -class Enc_dbd70c : OpcodeHexagon { - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <5> Rtt32; - let Inst{12-8} = Rtt32{4-0}; - bits <2> Pu4; - let Inst{6-5} = Pu4{1-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; -} -class Enc_8b8d61 : OpcodeHexagon { - bits <6> Ii; - let Inst{22-21} = Ii{5-4}; - let Inst{13-13} = Ii{3-3}; - let Inst{7-5} = Ii{2-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; - bits <5> Ru32; - let Inst{4-0} = Ru32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; bits <5> Rd32; - let Inst{12-8} = Rd32{4-0}; + let Inst{4-0} = Rd32{4-0}; } -class Enc_c31910 : OpcodeHexagon { - bits <8> Ii; - let Inst{23-21} = Ii{7-5}; - let Inst{13-13} = Ii{4-4}; - let Inst{7-5} = Ii{3-1}; - let Inst{3-3} = Ii{0-0}; +class Enc_eaa9f8 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <2> Qx4; + let Inst{1-0} = Qx4{1-0}; +} +class Enc_eafd18 : OpcodeHexagon { bits <5> II; let Inst{12-8} = II{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; } -class Enc_9fae8a : OpcodeHexagon { - bits <6> Ii; - let Inst{13-8} = Ii{5-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_a1640c : OpcodeHexagon { - bits <6> Ii; - let Inst{13-8} = Ii{5-0}; - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_fef969 : OpcodeHexagon { - bits <6> Ii; - let Inst{20-16} = Ii{5-1}; - let Inst{5-5} = Ii{0-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_b0e9d8 : OpcodeHexagon { - bits <10> Ii; - let Inst{21-21} = Ii{9-9}; - let Inst{13-5} = Ii{8-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rx32; - let Inst{4-0} = Rx32{4-0}; -} -class Enc_b4e6cf : OpcodeHexagon { - bits <10> Ii; - let Inst{21-21} = Ii{9-9}; - let Inst{13-5} = Ii{8-0}; - bits <5> Ru32; - let Inst{4-0} = Ru32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_1cf4ca : OpcodeHexagon { - bits <6> Ii; - let Inst{17-16} = Ii{5-4}; - let Inst{6-3} = Ii{3-0}; - bits <2> Pv4; - let Inst{1-0} = Pv4{1-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; -} -class Enc_6339d5 : OpcodeHexagon { +class Enc_eca7c8 : OpcodeHexagon { bits <2> Ii; let Inst{13-13} = Ii{1-1}; let Inst{7-7} = Ii{0-0}; - bits <2> Pv4; - let Inst{6-5} = Pv4{1-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; bits <5> Ru32; @@ -2282,86 +3261,51 @@ class Enc_6339d5 : OpcodeHexagon { bits <5> Rt32; let Inst{4-0} = Rt32{4-0}; } -class Enc_44215c : OpcodeHexagon { - bits <6> Ii; - let Inst{17-16} = Ii{5-4}; - let Inst{6-3} = Ii{3-0}; - bits <2> Pv4; - let Inst{1-0} = Pv4{1-0}; - bits <3> Nt8; - let Inst{10-8} = Nt8{2-0}; +class Enc_ecbcc8 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; } -class Enc_47ee5e : OpcodeHexagon { +class Enc_ed48be : OpcodeHexagon { bits <2> Ii; - let Inst{13-13} = Ii{1-1}; - let Inst{7-7} = Ii{0-0}; + let Inst{6-5} = Ii{1-0}; + bits <3> Rdd8; + let Inst{2-0} = Rdd8{2-0}; +} +class Enc_ed5027 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Gdd32; + let Inst{4-0} = Gdd32{4-0}; +} +class Enc_ee5ed0 : OpcodeHexagon { + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; + bits <4> Rd16; + let Inst{3-0} = Rd16{3-0}; + bits <2> n1; + let Inst{9-8} = n1{1-0}; +} +class Enc_ef601b : OpcodeHexagon { + bits <4> Ii; + let Inst{13-13} = Ii{3-3}; + let Inst{10-8} = Ii{2-0}; bits <2> Pv4; - let Inst{6-5} = Pv4{1-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Ru32; - let Inst{12-8} = Ru32{4-0}; - bits <3> Nt8; - let Inst{2-0} = Nt8{2-0}; + let Inst{12-11} = Pv4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; } -class Enc_50b5ac : OpcodeHexagon { - bits <6> Ii; - let Inst{17-16} = Ii{5-4}; - let Inst{6-3} = Ii{3-0}; - bits <2> Pv4; - let Inst{1-0} = Pv4{1-0}; - bits <5> Rtt32; - let Inst{12-8} = Rtt32{4-0}; +class Enc_efaed8 : OpcodeHexagon { + bits <1> Ii; + let Inst{8-8} = Ii{0-0}; } -class Enc_1a9974 : OpcodeHexagon { - bits <2> Ii; - let Inst{13-13} = Ii{1-1}; - let Inst{7-7} = Ii{0-0}; - bits <2> Pv4; - let Inst{6-5} = Pv4{1-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Ru32; - let Inst{12-8} = Ru32{4-0}; - bits <5> Rtt32; - let Inst{4-0} = Rtt32{4-0}; -} -class Enc_d7dc10 : OpcodeHexagon { - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rtt32; - let Inst{12-8} = Rtt32{4-0}; - bits <2> Pd4; - let Inst{1-0} = Pd4{1-0}; -} -class Enc_8203bb : OpcodeHexagon { - bits <6> Ii; - let Inst{12-7} = Ii{5-0}; - bits <8> II; - let Inst{13-13} = II{7-7}; - let Inst{6-0} = II{6-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; -} -class Enc_d7a65e : OpcodeHexagon { - bits <6> Ii; - let Inst{12-7} = Ii{5-0}; +class Enc_f0cca7 : OpcodeHexagon { + bits <8> Ii; + let Inst{12-5} = Ii{7-0}; bits <6> II; - let Inst{13-13} = II{5-5}; - let Inst{4-0} = II{4-0}; - bits <2> Pv4; - let Inst{6-5} = Pv4{1-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; -} -class Enc_a803e0 : OpcodeHexagon { - bits <7> Ii; - let Inst{12-7} = Ii{6-1}; - bits <8> II; - let Inst{13-13} = II{7-7}; - let Inst{6-0} = II{6-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; + let Inst{20-16} = II{5-1}; + let Inst{13-13} = II{0-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; } class Enc_f20719 : OpcodeHexagon { bits <7> Ii; @@ -2383,965 +3327,15 @@ class Enc_f37377 : OpcodeHexagon { bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; } -class Enc_5ccba9 : OpcodeHexagon { - bits <8> Ii; - let Inst{12-7} = Ii{7-2}; +class Enc_f394d3 : OpcodeHexagon { bits <6> II; - let Inst{13-13} = II{5-5}; - let Inst{4-0} = II{4-0}; - bits <2> Pv4; - let Inst{6-5} = Pv4{1-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; -} -class Enc_8bcba4 : OpcodeHexagon { - bits <6> II; - let Inst{5-0} = II{5-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; + let Inst{11-8} = II{5-2}; + let Inst{6-5} = II{1-0}; + bits <5> Ryy32; + let Inst{4-0} = Ryy32{4-0}; bits <5> Re32; let Inst{20-16} = Re32{4-0}; } -class Enc_eca7c8 : OpcodeHexagon { - bits <2> Ii; - let Inst{13-13} = Ii{1-1}; - let Inst{7-7} = Ii{0-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Ru32; - let Inst{12-8} = Ru32{4-0}; - bits <5> Rt32; - let Inst{4-0} = Rt32{4-0}; -} -class Enc_9ea4cf : OpcodeHexagon { - bits <2> Ii; - let Inst{13-13} = Ii{1-1}; - let Inst{6-6} = Ii{0-0}; - bits <6> II; - let Inst{5-0} = II{5-0}; - bits <5> Ru32; - let Inst{20-16} = Ru32{4-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; -} -class Enc_724154 : OpcodeHexagon { - bits <6> II; - let Inst{5-0} = II{5-0}; - bits <3> Nt8; - let Inst{10-8} = Nt8{2-0}; - bits <5> Re32; - let Inst{20-16} = Re32{4-0}; -} -class Enc_c6220b : OpcodeHexagon { - bits <2> Ii; - let Inst{13-13} = Ii{1-1}; - let Inst{7-7} = Ii{0-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Ru32; - let Inst{12-8} = Ru32{4-0}; - bits <3> Nt8; - let Inst{2-0} = Nt8{2-0}; -} -class Enc_7eb485 : OpcodeHexagon { - bits <2> Ii; - let Inst{13-13} = Ii{1-1}; - let Inst{6-6} = Ii{0-0}; - bits <6> II; - let Inst{5-0} = II{5-0}; - bits <5> Ru32; - let Inst{20-16} = Ru32{4-0}; - bits <3> Nt8; - let Inst{10-8} = Nt8{2-0}; -} -class Enc_c7a204 : OpcodeHexagon { - bits <6> II; - let Inst{5-0} = II{5-0}; - bits <5> Rtt32; - let Inst{12-8} = Rtt32{4-0}; - bits <5> Re32; - let Inst{20-16} = Re32{4-0}; -} -class Enc_55355c : OpcodeHexagon { - bits <2> Ii; - let Inst{13-13} = Ii{1-1}; - let Inst{7-7} = Ii{0-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Ru32; - let Inst{12-8} = Ru32{4-0}; - bits <5> Rtt32; - let Inst{4-0} = Rtt32{4-0}; -} -class Enc_f79415 : OpcodeHexagon { - bits <2> Ii; - let Inst{13-13} = Ii{1-1}; - let Inst{6-6} = Ii{0-0}; - bits <6> II; - let Inst{5-0} = II{5-0}; - bits <5> Ru32; - let Inst{20-16} = Ru32{4-0}; - bits <5> Rtt32; - let Inst{12-8} = Rtt32{4-0}; -} -class Enc_645d54 : OpcodeHexagon { - bits <2> Ii; - let Inst{13-13} = Ii{1-1}; - let Inst{5-5} = Ii{0-0}; - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; -} -class Enc_b72622 : OpcodeHexagon { - bits <2> Ii; - let Inst{13-13} = Ii{1-1}; - let Inst{5-5} = Ii{0-0}; - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Rxx32; - let Inst{4-0} = Rxx32{4-0}; -} -class Enc_11a146 : OpcodeHexagon { - bits <4> Ii; - let Inst{11-8} = Ii{3-0}; - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_93af4c : OpcodeHexagon { - bits <7> Ii; - let Inst{10-4} = Ii{6-0}; - bits <4> Rx16; - let Inst{3-0} = Rx16{3-0}; -} -class Enc_0527db : OpcodeHexagon { - bits <4> Rs16; - let Inst{7-4} = Rs16{3-0}; - bits <4> Rx16; - let Inst{3-0} = Rx16{3-0}; -} -class Enc_2df31d : OpcodeHexagon { - bits <8> Ii; - let Inst{9-4} = Ii{7-2}; - bits <4> Rd16; - let Inst{3-0} = Rd16{3-0}; -} -class Enc_97d666 : OpcodeHexagon { - bits <4> Rs16; - let Inst{7-4} = Rs16{3-0}; - bits <4> Rd16; - let Inst{3-0} = Rd16{3-0}; -} -class Enc_1f5ba6 : OpcodeHexagon { - bits <4> Rd16; - let Inst{3-0} = Rd16{3-0}; -} -class Enc_63eaeb : OpcodeHexagon { - bits <2> Ii; - let Inst{1-0} = Ii{1-0}; - bits <4> Rs16; - let Inst{7-4} = Rs16{3-0}; -} -class Enc_ed48be : OpcodeHexagon { - bits <2> Ii; - let Inst{6-5} = Ii{1-0}; - bits <3> Rdd8; - let Inst{2-0} = Rdd8{2-0}; -} -class Enc_399e12 : OpcodeHexagon { - bits <4> Rs16; - let Inst{7-4} = Rs16{3-0}; - bits <3> Rdd8; - let Inst{2-0} = Rdd8{2-0}; -} -class Enc_ee5ed0 : OpcodeHexagon { - bits <4> Rs16; - let Inst{7-4} = Rs16{3-0}; - bits <4> Rd16; - let Inst{3-0} = Rd16{3-0}; - bits <2> n1; - let Inst{9-8} = n1{1-0}; -} -class Enc_e39bb2 : OpcodeHexagon { - bits <6> Ii; - let Inst{9-4} = Ii{5-0}; - bits <4> Rd16; - let Inst{3-0} = Rd16{3-0}; -} -class Enc_7a0ea6 : OpcodeHexagon { - bits <4> Rd16; - let Inst{3-0} = Rd16{3-0}; - bits <1> n1; - let Inst{9-9} = n1{0-0}; -} -class Enc_53dca9 : OpcodeHexagon { - bits <6> Ii; - let Inst{11-8} = Ii{5-2}; - bits <4> Rs16; - let Inst{7-4} = Rs16{3-0}; - bits <4> Rd16; - let Inst{3-0} = Rd16{3-0}; -} -class Enc_c175d0 : OpcodeHexagon { - bits <4> Ii; - let Inst{11-8} = Ii{3-0}; - bits <4> Rs16; - let Inst{7-4} = Rs16{3-0}; - bits <4> Rd16; - let Inst{3-0} = Rd16{3-0}; -} -class Enc_2fbf3c : OpcodeHexagon { - bits <3> Ii; - let Inst{10-8} = Ii{2-0}; - bits <4> Rs16; - let Inst{7-4} = Rs16{3-0}; - bits <4> Rd16; - let Inst{3-0} = Rd16{3-0}; -} -class Enc_86a14b : OpcodeHexagon { - bits <8> Ii; - let Inst{7-3} = Ii{7-3}; - bits <3> Rdd8; - let Inst{2-0} = Rdd8{2-0}; -} -class Enc_2bae10 : OpcodeHexagon { - bits <4> Ii; - let Inst{10-8} = Ii{3-1}; - bits <4> Rs16; - let Inst{7-4} = Rs16{3-0}; - bits <4> Rd16; - let Inst{3-0} = Rd16{3-0}; -} -class Enc_51635c : OpcodeHexagon { - bits <7> Ii; - let Inst{8-4} = Ii{6-2}; - bits <4> Rd16; - let Inst{3-0} = Rd16{3-0}; -} -class Enc_b38ffc : OpcodeHexagon { - bits <4> Ii; - let Inst{11-8} = Ii{3-0}; - bits <4> Rs16; - let Inst{7-4} = Rs16{3-0}; - bits <4> Rt16; - let Inst{3-0} = Rt16{3-0}; -} -class Enc_f55a0c : OpcodeHexagon { - bits <6> Ii; - let Inst{11-8} = Ii{5-2}; - bits <4> Rs16; - let Inst{7-4} = Rs16{3-0}; - bits <4> Rt16; - let Inst{3-0} = Rt16{3-0}; -} -class Enc_6f70ca : OpcodeHexagon { - bits <8> Ii; - let Inst{8-4} = Ii{7-3}; -} -class Enc_84d359 : OpcodeHexagon { - bits <4> Ii; - let Inst{3-0} = Ii{3-0}; - bits <4> Rs16; - let Inst{7-4} = Rs16{3-0}; -} -class Enc_b8309d : OpcodeHexagon { - bits <9> Ii; - let Inst{8-3} = Ii{8-3}; - bits <3> Rtt8; - let Inst{2-0} = Rtt8{2-0}; -} -class Enc_625deb : OpcodeHexagon { - bits <4> Ii; - let Inst{10-8} = Ii{3-1}; - bits <4> Rs16; - let Inst{7-4} = Rs16{3-0}; - bits <4> Rt16; - let Inst{3-0} = Rt16{3-0}; -} -class Enc_87c142 : OpcodeHexagon { - bits <7> Ii; - let Inst{8-4} = Ii{6-2}; - bits <4> Rt16; - let Inst{3-0} = Rt16{3-0}; -} -class Enc_a6ce9c : OpcodeHexagon { - bits <6> Ii; - let Inst{3-0} = Ii{5-2}; - bits <4> Rs16; - let Inst{7-4} = Rs16{3-0}; -} -class Enc_2146c1 : OpcodeHexagon { - bits <5> Vuu32; - let Inst{20-16} = Vuu32{4-0}; - bits <5> Vvv32; - let Inst{12-8} = Vvv32{4-0}; - bits <3> Qss8; - let Inst{2-0} = Qss8{2-0}; - bits <5> Vd32; - let Inst{7-3} = Vd32{4-0}; -} -class Enc_843e80 : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vd32; - let Inst{7-3} = Vd32{4-0}; - bits <3> Qxx8; - let Inst{2-0} = Qxx8{2-0}; -} -class Enc_1f3376 : OpcodeHexagon { - bits <5> Vu32; - let Inst{20-16} = Vu32{4-0}; - bits <5> Vv32; - let Inst{12-8} = Vv32{4-0}; - bits <5> Vxx32; - let Inst{7-3} = Vxx32{4-0}; -} -class Enc_8e9fbd : OpcodeHexagon { - bits <5> Vu32; - let Inst{20-16} = Vu32{4-0}; - bits <3> Rt8; - let Inst{2-0} = Rt8{2-0}; - bits <5> Vd32; - let Inst{7-3} = Vd32{4-0}; - bits <5> Vy32; - let Inst{12-8} = Vy32{4-0}; -} -class Enc_57e245 : OpcodeHexagon { - bits <5> Vu32; - let Inst{20-16} = Vu32{4-0}; - bits <3> Rt8; - let Inst{2-0} = Rt8{2-0}; - bits <5> Vdd32; - let Inst{7-3} = Vdd32{4-0}; - bits <5> Vy32; - let Inst{12-8} = Vy32{4-0}; -} -class Enc_274a4c : OpcodeHexagon { - bits <5> Vu32; - let Inst{20-16} = Vu32{4-0}; - bits <3> Rt8; - let Inst{2-0} = Rt8{2-0}; - bits <5> Vx32; - let Inst{7-3} = Vx32{4-0}; - bits <5> Vy32; - let Inst{12-8} = Vy32{4-0}; -} -class Enc_fbacc2 : OpcodeHexagon { - bits <5> Vu32; - let Inst{20-16} = Vu32{4-0}; - bits <3> Rt8; - let Inst{2-0} = Rt8{2-0}; - bits <5> Vxx32; - let Inst{7-3} = Vxx32{4-0}; - bits <5> Vy32; - let Inst{12-8} = Vy32{4-0}; -} -class Enc_2a736a : OpcodeHexagon { - bits <5> Vuu32; - let Inst{20-16} = Vuu32{4-0}; - bits <5> Vdd32; - let Inst{7-3} = Vdd32{4-0}; -} -class Enc_b8513b : OpcodeHexagon { - bits <5> Vuu32; - let Inst{20-16} = Vuu32{4-0}; - bits <5> Vvv32; - let Inst{12-8} = Vvv32{4-0}; - bits <5> Vdd32; - let Inst{7-3} = Vdd32{4-0}; -} -class Enc_b5e54d : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rdd32; - let Inst{4-0} = Rdd32{4-0}; -} -class Enc_50e578 : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_b5b643 : OpcodeHexagon { - bits <5> Rtt32; - let Inst{20-16} = Rtt32{4-0}; - bits <5> Vx32; - let Inst{7-3} = Vx32{4-0}; -} -class Enc_2516bf : OpcodeHexagon { - bits <5> Vu32; - let Inst{20-16} = Vu32{4-0}; - bits <5> Vd32; - let Inst{7-3} = Vd32{4-0}; -} -class Enc_8d04c3 : OpcodeHexagon { - bits <5> Vu32; - let Inst{20-16} = Vu32{4-0}; - bits <5> Vv32; - let Inst{12-8} = Vv32{4-0}; - bits <5> Vd32; - let Inst{7-3} = Vd32{4-0}; -} -class Enc_2ad23d : OpcodeHexagon { - bits <5> Vu32; - let Inst{20-16} = Vu32{4-0}; - bits <5> Vv32; - let Inst{12-8} = Vv32{4-0}; - bits <5> Vx32; - let Inst{7-3} = Vx32{4-0}; -} -class Enc_85daf5 : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Rtt32; - let Inst{20-16} = Rtt32{4-0}; - bits <5> Vx32; - let Inst{7-3} = Vx32{4-0}; -} -class Enc_e570b0 : OpcodeHexagon { - bits <5> Rtt32; - let Inst{20-16} = Rtt32{4-0}; - bits <5> Vdd32; - let Inst{7-3} = Vdd32{4-0}; -} -class Enc_41dcc3 : OpcodeHexagon { - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vdd32; - let Inst{7-3} = Vdd32{4-0}; -} -class Enc_3126d7 : OpcodeHexagon { - bits <5> Vu32; - let Inst{20-16} = Vu32{4-0}; - bits <5> Vv32; - let Inst{12-8} = Vv32{4-0}; - bits <5> Vdd32; - let Inst{7-3} = Vdd32{4-0}; -} -class Enc_1cd70f : OpcodeHexagon { - bits <5> Vu32; - let Inst{20-16} = Vu32{4-0}; - bits <5> Vv32; - let Inst{12-8} = Vv32{4-0}; - bits <3> Rt8; - let Inst{2-0} = Rt8{2-0}; - bits <5> Vd32; - let Inst{7-3} = Vd32{4-0}; -} -class Enc_12dd8f : OpcodeHexagon { - bits <5> Vu32; - let Inst{20-16} = Vu32{4-0}; - bits <5> Vv32; - let Inst{12-8} = Vv32{4-0}; - bits <3> Rt8; - let Inst{2-0} = Rt8{2-0}; - bits <5> Vx32; - let Inst{7-3} = Vx32{4-0}; -} -class Enc_8d5d98 : OpcodeHexagon { - bits <5> Vu32; - let Inst{20-16} = Vu32{4-0}; - bits <5> Vv32; - let Inst{12-8} = Vv32{4-0}; - bits <3> Rt8; - let Inst{2-0} = Rt8{2-0}; - bits <5> Vxx32; - let Inst{7-3} = Vxx32{4-0}; -} -class Enc_fc563d : OpcodeHexagon { - bits <5> Vuu32; - let Inst{20-16} = Vuu32{4-0}; - bits <5> Vv32; - let Inst{12-8} = Vv32{4-0}; - bits <5> Vd32; - let Inst{7-3} = Vd32{4-0}; -} -class Enc_c84567 : OpcodeHexagon { - bits <5> Vuu32; - let Inst{20-16} = Vuu32{4-0}; - bits <5> Vv32; - let Inst{12-8} = Vv32{4-0}; - bits <5> Vdd32; - let Inst{7-3} = Vdd32{4-0}; -} -class Enc_334c2b : OpcodeHexagon { - bits <5> Vuu32; - let Inst{12-8} = Vuu32{4-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vd32; - let Inst{7-3} = Vd32{4-0}; -} -class Enc_3c46e8 : OpcodeHexagon { - bits <5> Vuu32; - let Inst{12-8} = Vuu32{4-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vdd32; - let Inst{7-3} = Vdd32{4-0}; -} -class Enc_129701 : OpcodeHexagon { - bits <5> Vuu32; - let Inst{20-16} = Vuu32{4-0}; - bits <5> Vvv32; - let Inst{12-8} = Vvv32{4-0}; - bits <5> Vd32; - let Inst{7-3} = Vd32{4-0}; -} -class Enc_790d6e : OpcodeHexagon { - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vd32; - let Inst{7-3} = Vd32{4-0}; -} -class Enc_880793 : OpcodeHexagon { - bits <3> Qt8; - let Inst{2-0} = Qt8{2-0}; - bits <5> Vu32; - let Inst{20-16} = Vu32{4-0}; - bits <5> Vv32; - let Inst{12-8} = Vv32{4-0}; - bits <5> Vdd32; - let Inst{7-3} = Vdd32{4-0}; -} -class Enc_a265b7 : OpcodeHexagon { - bits <5> Vuu32; - let Inst{20-16} = Vuu32{4-0}; - bits <5> Vd32; - let Inst{7-3} = Vd32{4-0}; -} -class Enc_6b1bc4 : OpcodeHexagon { - bits <5> Vuu32; - let Inst{20-16} = Vuu32{4-0}; - bits <3> Qt8; - let Inst{10-8} = Qt8{2-0}; - bits <5> Vdd32; - let Inst{7-3} = Vdd32{4-0}; -} -class Enc_b2ffce : OpcodeHexagon { - bits <5> Vd32; - let Inst{7-3} = Vd32{4-0}; -} -class Enc_fde0e3 : OpcodeHexagon { - bits <5> Rtt32; - let Inst{20-16} = Rtt32{4-0}; - bits <5> Vd32; - let Inst{7-3} = Vd32{4-0}; -} -class Enc_b3bac4 : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Rtt32; - let Inst{20-16} = Rtt32{4-0}; - bits <5> Vd32; - let Inst{7-3} = Vd32{4-0}; -} -class Enc_e7c9de : OpcodeHexagon { - bits <5> Vu32; - let Inst{20-16} = Vu32{4-0}; -} -class Enc_5c3a80 : OpcodeHexagon { - bits <3> Qt8; - let Inst{10-8} = Qt8{2-0}; - bits <3> Qd8; - let Inst{5-3} = Qd8{2-0}; -} -class Enc_8f7cc3 : OpcodeHexagon { - bits <3> Qtt8; - let Inst{10-8} = Qtt8{2-0}; - bits <3> Qdd8; - let Inst{5-3} = Qdd8{2-0}; -} -class Enc_f106e0 : OpcodeHexagon { - bits <5> Vu32; - let Inst{20-16} = Vu32{4-0}; - bits <5> Vv32; - let Inst{8-4} = Vv32{4-0}; - bits <5> Vt32; - let Inst{13-9} = Vt32{4-0}; - bits <4> Vdd16; - let Inst{3-0} = Vdd16{3-0}; -} -class Enc_7db2f8 : OpcodeHexagon { - bits <5> Vu32; - let Inst{13-9} = Vu32{4-0}; - bits <5> Vv32; - let Inst{8-4} = Vv32{4-0}; - bits <4> Vdd16; - let Inst{3-0} = Vdd16{3-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_37c406 : OpcodeHexagon { - bits <5> Vu32; - let Inst{20-16} = Vu32{4-0}; - bits <5> Vv32; - let Inst{12-8} = Vv32{4-0}; - bits <3> Rt8; - let Inst{2-0} = Rt8{2-0}; - bits <4> Vdd16; - let Inst{7-4} = Vdd16{3-0}; -} -class Enc_72a92d : OpcodeHexagon { - bits <5> Vuu32; - let Inst{12-8} = Vuu32{4-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vxx32; - let Inst{7-3} = Vxx32{4-0}; -} -class Enc_d7e8ba : OpcodeHexagon { - bits <5> Vu32; - let Inst{20-16} = Vu32{4-0}; - bits <5> Vdd32; - let Inst{7-3} = Vdd32{4-0}; -} -class Enc_ce4c54 : OpcodeHexagon { - bits <16> Ii; - let Inst{21-21} = Ii{15-15}; - let Inst{13-8} = Ii{14-9}; - let Inst{2-0} = Ii{8-6}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vd32; - let Inst{7-3} = Vd32{4-0}; -} -class Enc_3a81ac : OpcodeHexagon { - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Vd32; - let Inst{7-3} = Vd32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_6c4697 : OpcodeHexagon { - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Vd32; - let Inst{7-3} = Vd32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_b0e553 : OpcodeHexagon { - bits <16> Ii; - let Inst{21-21} = Ii{15-15}; - let Inst{13-8} = Ii{14-9}; - let Inst{2-0} = Ii{8-6}; - bits <5> Vd32; - let Inst{7-3} = Vd32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_5883d0 : OpcodeHexagon { - bits <16> Ii; - let Inst{21-21} = Ii{15-15}; - let Inst{13-8} = Ii{14-9}; - let Inst{2-0} = Ii{8-6}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vdd32; - let Inst{7-3} = Vdd32{4-0}; -} -class Enc_9a895f : OpcodeHexagon { - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Vdd32; - let Inst{7-3} = Vdd32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_f3adb6 : OpcodeHexagon { - bits <16> Ii; - let Inst{21-21} = Ii{15-15}; - let Inst{13-8} = Ii{14-9}; - let Inst{2-0} = Ii{8-6}; - bits <5> Vdd32; - let Inst{7-3} = Vdd32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_b5d5a7 : OpcodeHexagon { - bits <16> Ii; - let Inst{21-21} = Ii{15-15}; - let Inst{13-8} = Ii{14-9}; - let Inst{2-0} = Ii{8-6}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vs32; - let Inst{7-3} = Vs32{4-0}; -} -class Enc_5b76ab : OpcodeHexagon { - bits <10> Ii; - let Inst{21-21} = Ii{9-9}; - let Inst{13-8} = Ii{8-3}; - let Inst{2-0} = Ii{2-0}; - bits <5> Vs32; - let Inst{7-3} = Vs32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_17a474 : OpcodeHexagon { - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Vs32; - let Inst{7-3} = Vs32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_9a9d62 : OpcodeHexagon { - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; - bits <5> Vs32; - let Inst{7-3} = Vs32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_3a527f : OpcodeHexagon { - bits <16> Ii; - let Inst{21-21} = Ii{15-15}; - let Inst{13-8} = Ii{14-9}; - let Inst{2-0} = Ii{8-6}; - bits <5> Vs32; - let Inst{7-3} = Vs32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_c39a8b : OpcodeHexagon { - bits <16> Ii; - let Inst{21-21} = Ii{15-15}; - let Inst{13-8} = Ii{14-9}; - let Inst{2-0} = Ii{8-6}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vss32; - let Inst{7-3} = Vss32{4-0}; -} -class Enc_908985 : OpcodeHexagon { - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Vss32; - let Inst{7-3} = Vss32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_e8ddd5 : OpcodeHexagon { - bits <16> Ii; - let Inst{21-21} = Ii{15-15}; - let Inst{13-8} = Ii{14-9}; - let Inst{2-0} = Ii{8-6}; - bits <5> Vss32; - let Inst{7-3} = Vss32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_6a4549 : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vd32; - let Inst{7-3} = Vd32{4-0}; -} -class Enc_932b58 : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; -} -class Enc_124cac : OpcodeHexagon { - bits <5> Vuu32; - let Inst{20-16} = Vuu32{4-0}; - bits <5> Vxx32; - let Inst{7-3} = Vxx32{4-0}; -} -class Enc_aceeef : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vdd32; - let Inst{7-3} = Vdd32{4-0}; -} -class Enc_2c3281 : OpcodeHexagon { - bits <5> Vdd32; - let Inst{7-3} = Vdd32{4-0}; -} -class Enc_a4ae28 : OpcodeHexagon { - bits <5> Vu32; - let Inst{20-16} = Vu32{4-0}; - bits <5> Vv32; - let Inst{12-8} = Vv32{4-0}; - bits <3> Qd8; - let Inst{5-3} = Qd8{2-0}; -} -class Enc_c1652e : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <3> Qd8; - let Inst{5-3} = Qd8{2-0}; -} -class Enc_9aae4a : OpcodeHexagon { - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vx32; - let Inst{7-3} = Vx32{4-0}; - bits <3> Qd8; - let Inst{2-0} = Qd8{2-0}; -} -class Enc_dcfcbb : OpcodeHexagon { - bits <5> Vu32; - let Inst{20-16} = Vu32{4-0}; - bits <5> Vvv32; - let Inst{12-8} = Vvv32{4-0}; - bits <5> Vd32; - let Inst{7-3} = Vd32{4-0}; -} -class Enc_a7ca29 : OpcodeHexagon { - bits <3> Qt8; - let Inst{2-0} = Qt8{2-0}; - bits <5> Vu32; - let Inst{20-16} = Vu32{4-0}; - bits <5> Vv32; - let Inst{12-8} = Vv32{4-0}; - bits <5> Vd32; - let Inst{7-3} = Vd32{4-0}; -} -class Enc_dd5f9f : OpcodeHexagon { - bits <3> Qtt8; - let Inst{2-0} = Qtt8{2-0}; - bits <5> Vuu32; - let Inst{20-16} = Vuu32{4-0}; - bits <5> Vvv32; - let Inst{12-8} = Vvv32{4-0}; - bits <5> Vdd32; - let Inst{7-3} = Vdd32{4-0}; -} -class Enc_7dc746 : OpcodeHexagon { - bits <3> Quu8; - let Inst{10-8} = Quu8{2-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <3> Qdd8; - let Inst{5-3} = Qdd8{2-0}; -} -class Enc_fa5efc : OpcodeHexagon { - bits <5> Vuu32; - let Inst{20-16} = Vuu32{4-0}; - bits <5> Vv32; - let Inst{12-8} = Vv32{4-0}; - bits <3> Rt8; - let Inst{2-0} = Rt8{2-0}; - bits <5> Vx32; - let Inst{7-3} = Vx32{4-0}; -} -class Enc_aac08c : OpcodeHexagon { - bits <5> Vu32; - let Inst{20-16} = Vu32{4-0}; - bits <5> Vx32; - let Inst{7-3} = Vx32{4-0}; -} -class Enc_9a8c1f : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Rtt32; - let Inst{20-16} = Rtt32{4-0}; - bits <5> Vdd32; - let Inst{7-3} = Vdd32{4-0}; -} -class Enc_a9eee0 : OpcodeHexagon { - bits <5> Vu32; - let Inst{20-16} = Vu32{4-0}; - bits <5> Vxx32; - let Inst{7-3} = Vxx32{4-0}; -} -class Enc_9ce456 : OpcodeHexagon { - bits <10> Ii; - let Inst{21-21} = Ii{9-9}; - let Inst{13-8} = Ii{8-3}; - let Inst{2-0} = Ii{2-0}; - bits <5> Vss32; - let Inst{7-3} = Vss32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_96f0fd : OpcodeHexagon { - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vx32; - let Inst{7-3} = Vx32{4-0}; - bits <3> Qdd8; - let Inst{2-0} = Qdd8{2-0}; -} -class Enc_a662ae : OpcodeHexagon { - bits <5> Vuu32; - let Inst{20-16} = Vuu32{4-0}; - bits <5> Vvv32; - let Inst{12-8} = Vvv32{4-0}; - bits <3> Rt8; - let Inst{2-0} = Rt8{2-0}; - bits <5> Vdd32; - let Inst{7-3} = Vdd32{4-0}; -} -class Enc_ec09c9 : OpcodeHexagon { - bits <5> Vuu32; - let Inst{20-16} = Vuu32{4-0}; - bits <5> Vvv32; - let Inst{12-8} = Vvv32{4-0}; - bits <3> Qdd8; - let Inst{5-3} = Qdd8{2-0}; -} -class Enc_400b42 : OpcodeHexagon { - bits <5> Vuu32; - let Inst{12-8} = Vuu32{4-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <3> Qdd8; - let Inst{5-3} = Qdd8{2-0}; -} -class Enc_a5ed8a : OpcodeHexagon { - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vd32; - let Inst{4-0} = Vd32{4-0}; -} -class Enc_134437 : OpcodeHexagon { - bits <2> Qs4; - let Inst{9-8} = Qs4{1-0}; - bits <2> Qt4; - let Inst{23-22} = Qt4{1-0}; - bits <2> Qd4; - let Inst{1-0} = Qd4{1-0}; -} -class Enc_bfbf03 : OpcodeHexagon { - bits <2> Qs4; - let Inst{9-8} = Qs4{1-0}; - bits <2> Qd4; - let Inst{1-0} = Qd4{1-0}; -} -class Enc_7222b7 : OpcodeHexagon { - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <2> Qd4; - let Inst{1-0} = Qd4{1-0}; -} class Enc_f3f408 : OpcodeHexagon { bits <4> Ii; let Inst{13-13} = Ii{3-3}; @@ -3351,117 +3345,62 @@ class Enc_f3f408 : OpcodeHexagon { bits <5> Vd32; let Inst{4-0} = Vd32{4-0}; } -class Enc_a255dc : OpcodeHexagon { - bits <3> Ii; - let Inst{10-8} = Ii{2-0}; - bits <5> Vd32; - let Inst{4-0} = Vd32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_2ebe3b : OpcodeHexagon { - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Vd32; - let Inst{4-0} = Vd32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_8d8a30 : OpcodeHexagon { +class Enc_f4413a : OpcodeHexagon { bits <4> Ii; - let Inst{13-13} = Ii{3-3}; - let Inst{10-8} = Ii{2-0}; - bits <2> Pv4; - let Inst{12-11} = Pv4{1-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vd32; - let Inst{4-0} = Vd32{4-0}; -} -class Enc_58a8bf : OpcodeHexagon { - bits <3> Ii; - let Inst{10-8} = Ii{2-0}; - bits <2> Pv4; - let Inst{12-11} = Pv4{1-0}; - bits <5> Vd32; - let Inst{4-0} = Vd32{4-0}; + let Inst{8-5} = Ii{3-0}; + bits <2> Pt4; + let Inst{10-9} = Pt4{1-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } -class Enc_f8c1c4 : OpcodeHexagon { +class Enc_f44229 : OpcodeHexagon { + bits <7> Ii; + let Inst{13-13} = Ii{6-6}; + let Inst{7-3} = Ii{5-1}; bits <2> Pv4; - let Inst{12-11} = Pv4{1-0}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Vd32; - let Inst{4-0} = Vd32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; + let Inst{1-0} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; } -class Enc_c9e3bc : OpcodeHexagon { - bits <4> Ii; - let Inst{13-13} = Ii{3-3}; - let Inst{10-8} = Ii{2-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vs32; - let Inst{4-0} = Vs32{4-0}; +class Enc_f4f57b : OpcodeHexagon { + bits <2> Ii; + let Inst{6-5} = Ii{1-0}; + bits <5> Vuu32; + let Inst{12-8} = Vuu32{4-0}; + bits <5> Vvv32; + let Inst{20-16} = Vvv32{4-0}; + bits <5> Vxx32; + let Inst{4-0} = Vxx32{4-0}; } -class Enc_27b757 : OpcodeHexagon { - bits <4> Ii; - let Inst{13-13} = Ii{3-3}; - let Inst{10-8} = Ii{2-0}; - bits <2> Pv4; - let Inst{12-11} = Pv4{1-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vs32; - let Inst{4-0} = Vs32{4-0}; +class Enc_f55a0c : OpcodeHexagon { + bits <6> Ii; + let Inst{11-8} = Ii{5-2}; + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; + bits <4> Rt16; + let Inst{3-0} = Rt16{3-0}; } -class Enc_865390 : OpcodeHexagon { - bits <3> Ii; - let Inst{10-8} = Ii{2-0}; - bits <2> Pv4; - let Inst{12-11} = Pv4{1-0}; - bits <5> Vs32; - let Inst{4-0} = Vs32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; +class Enc_f5e933 : OpcodeHexagon { + bits <2> Ps4; + let Inst{17-16} = Ps4{1-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; } -class Enc_1ef990 : OpcodeHexagon { - bits <2> Pv4; - let Inst{12-11} = Pv4{1-0}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Vs32; - let Inst{4-0} = Vs32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_b62ef7 : OpcodeHexagon { - bits <3> Ii; - let Inst{10-8} = Ii{2-0}; - bits <5> Vs32; - let Inst{4-0} = Vs32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_d15d19 : OpcodeHexagon { - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Vs32; - let Inst{4-0} = Vs32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_f77fbc : OpcodeHexagon { - bits <4> Ii; - let Inst{13-13} = Ii{3-3}; - let Inst{10-8} = Ii{2-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <3> Os8; - let Inst{2-0} = Os8{2-0}; +class Enc_f6fe0b : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <6> n1; + let Inst{28-28} = n1{5-5}; + let Inst{24-22} = n1{4-2}; + let Inst{13-13} = n1{1-1}; + let Inst{8-8} = n1{0-0}; } class Enc_f7430e : OpcodeHexagon { bits <4> Ii; @@ -3474,106 +3413,68 @@ class Enc_f7430e : OpcodeHexagon { bits <3> Os8; let Inst{2-0} = Os8{2-0}; } -class Enc_784502 : OpcodeHexagon { - bits <3> Ii; - let Inst{10-8} = Ii{2-0}; - bits <2> Pv4; - let Inst{12-11} = Pv4{1-0}; - bits <3> Os8; - let Inst{2-0} = Os8{2-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_372c9d : OpcodeHexagon { - bits <2> Pv4; - let Inst{12-11} = Pv4{1-0}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <3> Os8; - let Inst{2-0} = Os8{2-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_1aaec1 : OpcodeHexagon { - bits <3> Ii; - let Inst{10-8} = Ii{2-0}; - bits <3> Os8; - let Inst{2-0} = Os8{2-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_cf1927 : OpcodeHexagon { - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <3> Os8; - let Inst{2-0} = Os8{2-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_2ea740 : OpcodeHexagon { - bits <4> Ii; - let Inst{13-13} = Ii{3-3}; - let Inst{10-8} = Ii{2-0}; - bits <2> Qv4; - let Inst{12-11} = Qv4{1-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vs32; - let Inst{4-0} = Vs32{4-0}; -} -class Enc_0b51ce : OpcodeHexagon { - bits <3> Ii; - let Inst{10-8} = Ii{2-0}; - bits <2> Qv4; - let Inst{12-11} = Qv4{1-0}; - bits <5> Vs32; - let Inst{4-0} = Vs32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_4dff07 : OpcodeHexagon { - bits <2> Qv4; - let Inst{12-11} = Qv4{1-0}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Vs32; - let Inst{4-0} = Vs32{4-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_ff3442 : OpcodeHexagon { +class Enc_f77fbc : OpcodeHexagon { bits <4> Ii; let Inst{13-13} = Ii{3-3}; let Inst{10-8} = Ii{2-0}; bits <5> Rt32; let Inst{20-16} = Rt32{4-0}; + bits <3> Os8; + let Inst{2-0} = Os8{2-0}; } -class Enc_6c9ee0 : OpcodeHexagon { - bits <3> Ii; - let Inst{10-8} = Ii{2-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; +class Enc_f79415 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{6-6} = Ii{0-0}; + bits <6> II; + let Inst{5-0} = II{5-0}; + bits <5> Ru32; + let Inst{20-16} = Ru32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; } -class Enc_44661f : OpcodeHexagon { +class Enc_f7ea77 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; + bits <4> n1; + let Inst{29-29} = n1{3-3}; + let Inst{26-25} = n1{2-1}; + let Inst{13-13} = n1{0-0}; +} +class Enc_f82302 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; + bits <4> n1; + let Inst{29-29} = n1{3-3}; + let Inst{26-25} = n1{2-1}; + let Inst{23-23} = n1{0-0}; +} +class Enc_f82eaf : OpcodeHexagon { + bits <8> Ii; + let Inst{10-5} = Ii{7-2}; + bits <2> Pt4; + let Inst{12-11} = Pt4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_f8c1c4 : OpcodeHexagon { + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; bits <1> Mu2; let Inst{13-13} = Mu2{0-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; bits <5> Rx32; let Inst{20-16} = Rx32{4-0}; } -class Enc_e7581c : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vd32; - let Inst{4-0} = Vd32{4-0}; -} -class Enc_45364e : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vv32; - let Inst{20-16} = Vv32{4-0}; - bits <5> Vd32; - let Inst{4-0} = Vd32{4-0}; -} class Enc_f8ecf9 : OpcodeHexagon { bits <5> Vuu32; let Inst{12-8} = Vuu32{4-0}; @@ -3582,611 +3483,53 @@ class Enc_f8ecf9 : OpcodeHexagon { bits <5> Vdd32; let Inst{4-0} = Vdd32{4-0}; } -class Enc_a90628 : OpcodeHexagon { - bits <2> Qv4; - let Inst{23-22} = Qv4{1-0}; - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vx32; - let Inst{4-0} = Vx32{4-0}; -} -class Enc_b43b67 : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vv32; - let Inst{20-16} = Vv32{4-0}; - bits <5> Vd32; - let Inst{4-0} = Vd32{4-0}; - bits <2> Qx4; - let Inst{6-5} = Qx4{1-0}; -} -class Enc_c1d806 : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vv32; - let Inst{20-16} = Vv32{4-0}; - bits <5> Vd32; - let Inst{4-0} = Vd32{4-0}; - bits <2> Qe4; - let Inst{6-5} = Qe4{1-0}; -} -class Enc_e0820b : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vv32; - let Inst{20-16} = Vv32{4-0}; - bits <2> Qs4; - let Inst{6-5} = Qs4{1-0}; - bits <5> Vd32; - let Inst{4-0} = Vd32{4-0}; -} -class Enc_71bb9b : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vv32; - let Inst{20-16} = Vv32{4-0}; - bits <5> Vdd32; - let Inst{4-0} = Vdd32{4-0}; -} -class Enc_3fc427 : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vv32; - let Inst{20-16} = Vv32{4-0}; - bits <5> Vxx32; - let Inst{4-0} = Vxx32{4-0}; -} -class Enc_a30110 : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vv32; - let Inst{23-19} = Vv32{4-0}; - bits <3> Rt8; - let Inst{18-16} = Rt8{2-0}; - bits <5> Vd32; - let Inst{4-0} = Vd32{4-0}; -} -class Enc_0b2e5b : OpcodeHexagon { - bits <3> Ii; - let Inst{7-5} = Ii{2-0}; - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vv32; - let Inst{20-16} = Vv32{4-0}; - bits <5> Vd32; - let Inst{4-0} = Vd32{4-0}; -} -class Enc_7b7ba8 : OpcodeHexagon { - bits <2> Qu4; - let Inst{9-8} = Qu4{1-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vd32; - let Inst{4-0} = Vd32{4-0}; -} -class Enc_895bd9 : OpcodeHexagon { - bits <2> Qu4; - let Inst{9-8} = Qu4{1-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vx32; - let Inst{4-0} = Vx32{4-0}; -} -class Enc_c4dc92 : OpcodeHexagon { - bits <2> Qv4; - let Inst{23-22} = Qv4{1-0}; - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vd32; - let Inst{4-0} = Vd32{4-0}; -} -class Enc_0f8bab : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <2> Qd4; - let Inst{1-0} = Qd4{1-0}; -} -class Enc_adf111 : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <2> Qx4; - let Inst{1-0} = Qx4{1-0}; -} -class Enc_b087ac : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vd32; - let Inst{4-0} = Vd32{4-0}; -} -class Enc_5138b3 : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vx32; - let Inst{4-0} = Vx32{4-0}; -} -class Enc_8c2412 : OpcodeHexagon { - bits <2> Ps4; - let Inst{6-5} = Ps4{1-0}; - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vv32; - let Inst{20-16} = Vv32{4-0}; - bits <5> Vdd32; - let Inst{4-0} = Vdd32{4-0}; -} -class Enc_770858 : OpcodeHexagon { - bits <2> Ps4; - let Inst{6-5} = Ps4{1-0}; - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vd32; - let Inst{4-0} = Vd32{4-0}; -} -class Enc_989021 : OpcodeHexagon { - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vy32; - let Inst{12-8} = Vy32{4-0}; - bits <5> Vx32; - let Inst{4-0} = Vx32{4-0}; -} -class Enc_24a7dc : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vv32; - let Inst{23-19} = Vv32{4-0}; - bits <3> Rt8; - let Inst{18-16} = Rt8{2-0}; - bits <5> Vdd32; - let Inst{4-0} = Vdd32{4-0}; -} -class Enc_aad80c : OpcodeHexagon { - bits <5> Vuu32; - let Inst{12-8} = Vuu32{4-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vdd32; - let Inst{4-0} = Vdd32{4-0}; -} -class Enc_d6990d : OpcodeHexagon { - bits <5> Vuu32; - let Inst{12-8} = Vuu32{4-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vxx32; - let Inst{4-0} = Vxx32{4-0}; -} -class Enc_0e41fa : OpcodeHexagon { - bits <5> Vuu32; - let Inst{12-8} = Vuu32{4-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vd32; - let Inst{4-0} = Vd32{4-0}; -} -class Enc_cc857d : OpcodeHexagon { - bits <5> Vuu32; - let Inst{12-8} = Vuu32{4-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vx32; - let Inst{4-0} = Vx32{4-0}; -} -class Enc_a7341a : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vv32; - let Inst{20-16} = Vv32{4-0}; - bits <5> Vx32; - let Inst{4-0} = Vx32{4-0}; -} -class Enc_95441f : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vv32; - let Inst{20-16} = Vv32{4-0}; - bits <2> Qd4; - let Inst{1-0} = Qd4{1-0}; -} -class Enc_eaa9f8 : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vv32; - let Inst{20-16} = Vv32{4-0}; - bits <2> Qx4; - let Inst{1-0} = Qx4{1-0}; -} -class Enc_8b8927 : OpcodeHexagon { - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Vv32; - let Inst{4-0} = Vv32{4-0}; -} -class Enc_158beb : OpcodeHexagon { - bits <2> Qs4; - let Inst{6-5} = Qs4{1-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Vv32; - let Inst{4-0} = Vv32{4-0}; -} -class Enc_28dcbb : OpcodeHexagon { - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Vvv32; - let Inst{4-0} = Vvv32{4-0}; -} -class Enc_4e4a80 : OpcodeHexagon { - bits <2> Qs4; - let Inst{6-5} = Qs4{1-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Vvv32; - let Inst{4-0} = Vvv32{4-0}; -} -class Enc_217147 : OpcodeHexagon { - bits <2> Qv4; - let Inst{23-22} = Qv4{1-0}; -} -class Enc_569cfe : OpcodeHexagon { - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vx32; - let Inst{4-0} = Vx32{4-0}; -} -class Enc_263841 : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Rtt32; - let Inst{20-16} = Rtt32{4-0}; - bits <5> Vd32; - let Inst{4-0} = Vd32{4-0}; -} -class Enc_245865 : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vv32; - let Inst{23-19} = Vv32{4-0}; - bits <3> Rt8; - let Inst{18-16} = Rt8{2-0}; - bits <5> Vx32; - let Inst{4-0} = Vx32{4-0}; -} -class Enc_cd4705 : OpcodeHexagon { - bits <3> Ii; - let Inst{7-5} = Ii{2-0}; - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vv32; - let Inst{20-16} = Vv32{4-0}; - bits <5> Vx32; - let Inst{4-0} = Vx32{4-0}; -} -class Enc_7b523d : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vv32; - let Inst{23-19} = Vv32{4-0}; - bits <3> Rt8; - let Inst{18-16} = Rt8{2-0}; - bits <5> Vxx32; - let Inst{4-0} = Vxx32{4-0}; -} -class Enc_1178da : OpcodeHexagon { - bits <3> Ii; - let Inst{7-5} = Ii{2-0}; - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vv32; - let Inst{20-16} = Vv32{4-0}; - bits <5> Vxx32; - let Inst{4-0} = Vxx32{4-0}; -} -class Enc_4b39e4 : OpcodeHexagon { - bits <3> Ii; - let Inst{7-5} = Ii{2-0}; - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vv32; - let Inst{20-16} = Vv32{4-0}; - bits <5> Vdd32; - let Inst{4-0} = Vdd32{4-0}; -} -class Enc_310ba1 : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Rtt32; - let Inst{20-16} = Rtt32{4-0}; - bits <5> Vx32; - let Inst{4-0} = Vx32{4-0}; -} -class Enc_01d3d0 : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vdd32; - let Inst{4-0} = Vdd32{4-0}; -} -class Enc_5e8512 : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vxx32; - let Inst{4-0} = Vxx32{4-0}; -} -class Enc_31db33 : OpcodeHexagon { - bits <2> Qt4; - let Inst{6-5} = Qt4{1-0}; - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vv32; - let Inst{20-16} = Vv32{4-0}; - bits <5> Vd32; - let Inst{4-0} = Vd32{4-0}; -} -class Enc_6f83e7 : OpcodeHexagon { - bits <2> Qv4; - let Inst{23-22} = Qv4{1-0}; - bits <5> Vd32; - let Inst{4-0} = Vd32{4-0}; -} -class Enc_cb785b : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Rtt32; - let Inst{20-16} = Rtt32{4-0}; - bits <5> Vdd32; - let Inst{4-0} = Vdd32{4-0}; -} -class Enc_ad9bef : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Rtt32; - let Inst{20-16} = Rtt32{4-0}; - bits <5> Vxx32; - let Inst{4-0} = Vxx32{4-0}; -} -class Enc_2f2f04 : OpcodeHexagon { - bits <1> Ii; - let Inst{5-5} = Ii{0-0}; - bits <5> Vuu32; - let Inst{12-8} = Vuu32{4-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vdd32; - let Inst{4-0} = Vdd32{4-0}; -} -class Enc_d483b9 : OpcodeHexagon { - bits <1> Ii; - let Inst{5-5} = Ii{0-0}; - bits <5> Vuu32; - let Inst{12-8} = Vuu32{4-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <5> Vxx32; - let Inst{4-0} = Vxx32{4-0}; -} -class Enc_1bd127 : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <3> Rt8; - let Inst{18-16} = Rt8{2-0}; - bits <5> Vdddd32; - let Inst{4-0} = Vdddd32{4-0}; -} -class Enc_d7bc34 : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <3> Rt8; - let Inst{18-16} = Rt8{2-0}; - bits <5> Vyyyy32; - let Inst{4-0} = Vyyyy32{4-0}; -} -class Enc_3b7631 : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vdddd32; - let Inst{4-0} = Vdddd32{4-0}; - bits <3> Rx8; - let Inst{18-16} = Rx8{2-0}; -} -class Enc_bddee3 : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vyyyy32; - let Inst{4-0} = Vyyyy32{4-0}; - bits <3> Rx8; - let Inst{18-16} = Rx8{2-0}; -} -class Enc_dd766a : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vdd32; - let Inst{4-0} = Vdd32{4-0}; -} -class Enc_16c48b : OpcodeHexagon { - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Vv32; - let Inst{12-8} = Vv32{4-0}; - bits <5> Vw32; - let Inst{4-0} = Vw32{4-0}; -} -class Enc_9be1de : OpcodeHexagon { - bits <2> Qs4; - let Inst{6-5} = Qs4{1-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Vv32; - let Inst{12-8} = Vv32{4-0}; - bits <5> Vw32; - let Inst{4-0} = Vw32{4-0}; -} -class Enc_a641d0 : OpcodeHexagon { - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Vvv32; - let Inst{12-8} = Vvv32{4-0}; - bits <5> Vw32; - let Inst{4-0} = Vw32{4-0}; -} -class Enc_3d6d37 : OpcodeHexagon { - bits <2> Qs4; - let Inst{6-5} = Qs4{1-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Vvv32; - let Inst{12-8} = Vvv32{4-0}; - bits <5> Vw32; - let Inst{4-0} = Vw32{4-0}; -} -class Enc_3dac0b : OpcodeHexagon { - bits <2> Qt4; - let Inst{6-5} = Qt4{1-0}; - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vv32; - let Inst{20-16} = Vv32{4-0}; - bits <5> Vdd32; - let Inst{4-0} = Vdd32{4-0}; -} -class Enc_500cb0 : OpcodeHexagon { - bits <5> Vu32; - let Inst{12-8} = Vu32{4-0}; - bits <5> Vxx32; - let Inst{4-0} = Vxx32{4-0}; -} -class Enc_efaed8 : OpcodeHexagon { - bits <1> Ii; - let Inst{8-8} = Ii{0-0}; -} -class Enc_802dc0 : OpcodeHexagon { - bits <1> Ii; - let Inst{8-8} = Ii{0-0}; - bits <2> Qv4; - let Inst{23-22} = Qv4{1-0}; -} -class Enc_ef601b : OpcodeHexagon { - bits <4> Ii; - let Inst{13-13} = Ii{3-3}; - let Inst{10-8} = Ii{2-0}; - bits <2> Pv4; - let Inst{12-11} = Pv4{1-0}; - bits <5> Rt32; - let Inst{20-16} = Rt32{4-0}; -} -class Enc_6baed4 : OpcodeHexagon { - bits <3> Ii; - let Inst{10-8} = Ii{2-0}; - bits <2> Pv4; - let Inst{12-11} = Pv4{1-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_691712 : OpcodeHexagon { - bits <2> Pv4; - let Inst{12-11} = Pv4{1-0}; - bits <1> Mu2; - let Inst{13-13} = Mu2{0-0}; - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_403871 : OpcodeHexagon { - bits <5> Rx32; - let Inst{20-16} = Rx32{4-0}; -} -class Enc_2d829e : OpcodeHexagon { +class Enc_fa3ba4 : OpcodeHexagon { bits <14> Ii; - let Inst{10-0} = Ii{13-3}; + let Inst{26-25} = Ii{13-12}; + let Inst{13-5} = Ii{11-3}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; -} -class Enc_ca3887 : OpcodeHexagon { - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; -} -class Enc_9e9047 : OpcodeHexagon { - bits <2> Pt4; - let Inst{9-8} = Pt4{1-0}; - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; -} -class Enc_7d1542 : OpcodeHexagon { - bits <7> Ss128; - let Inst{22-16} = Ss128{6-0}; - bits <5> Rd32; - let Inst{4-0} = Rd32{4-0}; -} -class Enc_8f7633 : OpcodeHexagon { - bits <5> Rs32; - let Inst{20-16} = Rs32{4-0}; - bits <7> Sd128; - let Inst{6-0} = Sd128{6-0}; -} -class Enc_46f33d : OpcodeHexagon { - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <5> Rt32; - let Inst{12-8} = Rt32{4-0}; -} -class Enc_d0fe02 : OpcodeHexagon { - bits <5> Rxx32; - let Inst{20-16} = Rxx32{4-0}; - bits <0> sgp10; -} -class Enc_e32517 : OpcodeHexagon { - bits <7> Sss128; - let Inst{22-16} = Sss128{6-0}; bits <5> Rdd32; let Inst{4-0} = Rdd32{4-0}; } -class Enc_a705fc : OpcodeHexagon { - bits <5> Rss32; - let Inst{20-16} = Rss32{4-0}; - bits <7> Sdd128; - let Inst{6-0} = Sdd128{6-0}; -} -class Enc_e6abcf : OpcodeHexagon { +class Enc_fb6577 : OpcodeHexagon { + bits <2> Pu4; + let Inst{9-8} = Pu4{1-0}; bits <5> Rs32; let Inst{20-16} = Rs32{4-0}; - bits <5> Rtt32; - let Inst{12-8} = Rtt32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; } -class Enc_b00112 : OpcodeHexagon { +class Enc_fcf7a7 : OpcodeHexagon { bits <5> Rss32; let Inst{20-16} = Rss32{4-0}; bits <5> Rtt32; let Inst{12-8} = Rtt32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; } -class Enc_598f6c : OpcodeHexagon { - bits <5> Rtt32; - let Inst{12-8} = Rtt32{4-0}; +class Enc_fda92c : OpcodeHexagon { + bits <17> Ii; + let Inst{26-25} = Ii{16-15}; + let Inst{20-16} = Ii{14-10}; + let Inst{13-13} = Ii{9-9}; + let Inst{7-0} = Ii{8-1}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; +} +class Enc_fef969 : OpcodeHexagon { + bits <6> Ii; + let Inst{20-16} = Ii{5-1}; + let Inst{5-5} = Ii{0-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_ff3442 : OpcodeHexagon { + bits <4> Ii; + let Inst{13-13} = Ii{3-3}; + let Inst{10-8} = Ii{2-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; } diff --git a/lib/Target/Hexagon/HexagonDepInstrInfo.td b/lib/Target/Hexagon/HexagonDepInstrInfo.td index ccc3f98d837..bba36352815 100644 --- a/lib/Target/Hexagon/HexagonDepInstrInfo.td +++ b/lib/Target/Hexagon/HexagonDepInstrInfo.td @@ -217,8 +217,8 @@ let opNewValue = 0; let BaseOpcode = "A2_addi"; let CextOpcode = "A2_add"; let InputType = "imm"; -let isPredicable = 1; let isAdd = 1; +let isPredicable = 1; let isExtendable = 1; let opExtendable = 2; let isExtentSigned = 1; @@ -233,8 +233,8 @@ tc_5da50c4b, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011000; -let isCommutable = 1; let isAdd = 1; +let isCommutable = 1; } def A2_addpsat : HInst< (outs DoubleRegs:$Rdd32), @@ -410,9 +410,9 @@ def A2_combineii : HInst< "$Rdd32 = combine(#$Ii,#$II)", tc_713b66bf, TypeALU32_2op>, Enc_18c338 { let Inst{31-23} = 0b011111000; -let isReMaterializable = 1; let isAsCheapAsAMove = 1; let isMoveImm = 1; +let isReMaterializable = 1; let isExtendable = 1; let opExtendable = 1; let isExtentSigned = 1; @@ -1533,9 +1533,9 @@ def A2_tfrpi : HInst< (ins s8_0Imm:$Ii), "$Rdd32 = #$Ii", tc_713b66bf, TypeALU64> { -let isReMaterializable = 1; let isAsCheapAsAMove = 1; let isMoveImm = 1; +let isReMaterializable = 1; let isPseudo = 1; } def A2_tfrpt : HInst< @@ -1579,10 +1579,10 @@ let opNewValue = 0; let BaseOpcode = "A2_tfrsi"; let CextOpcode = "A2_tfr"; let InputType = "imm"; -let isPredicable = 1; -let isReMaterializable = 1; let isAsCheapAsAMove = 1; let isMoveImm = 1; +let isPredicable = 1; +let isReMaterializable = 1; let isExtendable = 1; let opExtendable = 1; let isExtentSigned = 1; @@ -4892,8 +4892,8 @@ let cofMax1 = 1; let Uses = [R29]; let Defs = [PC, R31]; let BaseOpcode = "J2_call"; -let isPredicable = 1; let hasSideEffects = 1; +let isPredicable = 1; let isExtendable = 1; let opExtendable = 0; let isExtentSigned = 1; @@ -10131,6 +10131,18 @@ let isExtentSigned = 0; let opExtentBits = 17; let opExtentAlign = 1; } +def L2_loadw_aq : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = memw_aq($Rs32)", +tc_2471c1c8, TypeLD>, Enc_5e2823, Requires<[HasV68]> { +let Inst{13-5} = 0b001000000; +let Inst{31-21} = 0b10010010000; +let hasNewValue = 1; +let opNewValue = 0; +let accessSize = WordAccess; +let mayLoad = 1; +} def L2_loadw_locked : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), @@ -12022,6 +12034,16 @@ let isExtentSigned = 0; let opExtentBits = 6; let opExtentAlign = 0; } +def L4_loadd_aq : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32), +"$Rdd32 = memd_aq($Rs32)", +tc_2471c1c8, TypeLD>, Enc_3a3d62, Requires<[HasV68]> { +let Inst{13-5} = 0b011000000; +let Inst{31-21} = 0b10010010000; +let accessSize = DoubleWordAccess; +let mayLoad = 1; +} def L4_loadd_locked : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), @@ -18015,8 +18037,8 @@ let isExtended = 1; let mayStore = 1; let BaseOpcode = "S2_storerbabs"; let CextOpcode = "S2_storerb"; -let isPredicable = 1; let isNVStorable = 1; +let isPredicable = 1; let DecoderNamespace = "MustExtend"; let isExtended = 1; let opExtendable = 0; @@ -18105,8 +18127,8 @@ let isExtended = 1; let mayStore = 1; let BaseOpcode = "S2_storerhabs"; let CextOpcode = "S2_storerh"; -let isPredicable = 1; let isNVStorable = 1; +let isPredicable = 1; let DecoderNamespace = "MustExtend"; let isExtended = 1; let opExtendable = 0; @@ -18153,8 +18175,8 @@ let isExtended = 1; let mayStore = 1; let BaseOpcode = "S2_storeriabs"; let CextOpcode = "S2_storeri"; -let isPredicable = 1; let isNVStorable = 1; +let isPredicable = 1; let DecoderNamespace = "MustExtend"; let isExtended = 1; let opExtendable = 0; @@ -18197,7 +18219,28 @@ let Inst{1-0} = 0b00; let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-16} = 0b0101010010000000; +} +def R6_release_at_vi : HInst< +(outs), +(ins IntRegs:$Rs32), +"release($Rs32):at", +tc_db96aa6b, TypeST>, Enc_ecbcc8, Requires<[HasV68]> { +let Inst{7-2} = 0b000011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10100000111; let isSolo = 1; +let mayStore = 1; +} +def R6_release_st_vi : HInst< +(outs), +(ins IntRegs:$Rs32), +"release($Rs32):st", +tc_db96aa6b, TypeST>, Enc_ecbcc8, Requires<[HasV68]> { +let Inst{7-2} = 0b001011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10100000111; +let isSolo = 1; +let mayStore = 1; } def S2_addasl_rrri : HInst< (outs IntRegs:$Rd32), @@ -20856,8 +20899,8 @@ let mayStore = 1; let BaseOpcode = "S2_storerb_io"; let CextOpcode = "S2_storerb"; let InputType = "imm"; -let isPredicable = 1; let isNVStorable = 1; +let isPredicable = 1; let isExtendable = 1; let opExtendable = 1; let isExtentSigned = 1; @@ -20923,8 +20966,8 @@ let accessSize = ByteAccess; let mayStore = 1; let BaseOpcode = "S2_storerb_pi"; let CextOpcode = "S2_storerb"; -let isPredicable = 1; let isNVStorable = 1; +let isPredicable = 1; let Constraints = "$Rx32 = $Rx32in"; } def S2_storerb_pr : HInst< @@ -20960,8 +21003,8 @@ let accessSize = ByteAccess; let mayStore = 1; let Uses = [GP]; let BaseOpcode = "S2_storerbabs"; -let isPredicable = 1; let isNVStorable = 1; +let isPredicable = 1; let opExtendable = 0; let isExtentSigned = 0; let opExtentBits = 16; @@ -21065,8 +21108,8 @@ let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; let BaseOpcode = "S2_storerb_pi"; -let isPredicable = 1; let isNVStorable = 1; +let isPredicable = 1; let opNewValue = 3; let Constraints = "$Rx32 = $Rx32in"; } @@ -21358,8 +21401,8 @@ let mayStore = 1; let BaseOpcode = "S2_storerh_io"; let CextOpcode = "S2_storerh"; let InputType = "imm"; -let isPredicable = 1; let isNVStorable = 1; +let isPredicable = 1; let isExtendable = 1; let opExtendable = 1; let isExtentSigned = 1; @@ -21425,8 +21468,8 @@ let accessSize = HalfWordAccess; let mayStore = 1; let BaseOpcode = "S2_storerh_pi"; let CextOpcode = "S2_storerh"; -let isPredicable = 1; let isNVStorable = 1; +let isPredicable = 1; let Constraints = "$Rx32 = $Rx32in"; } def S2_storerh_pr : HInst< @@ -21462,8 +21505,8 @@ let accessSize = HalfWordAccess; let mayStore = 1; let Uses = [GP]; let BaseOpcode = "S2_storerhabs"; -let isPredicable = 1; let isNVStorable = 1; +let isPredicable = 1; let opExtendable = 0; let isExtentSigned = 0; let opExtentBits = 17; @@ -21634,8 +21677,8 @@ let mayStore = 1; let BaseOpcode = "S2_storeri_io"; let CextOpcode = "S2_storeri"; let InputType = "imm"; -let isPredicable = 1; let isNVStorable = 1; +let isPredicable = 1; let isExtendable = 1; let opExtendable = 1; let isExtentSigned = 1; @@ -21701,8 +21744,8 @@ let accessSize = WordAccess; let mayStore = 1; let BaseOpcode = "S2_storeri_pi"; let CextOpcode = "S2_storeri"; -let isPredicable = 1; let isNVStorable = 1; +let isPredicable = 1; let Constraints = "$Rx32 = $Rx32in"; } def S2_storeri_pr : HInst< @@ -21738,8 +21781,8 @@ let accessSize = WordAccess; let mayStore = 1; let Uses = [GP]; let BaseOpcode = "S2_storeriabs"; -let isPredicable = 1; let isNVStorable = 1; +let isPredicable = 1; let opExtendable = 0; let isExtentSigned = 0; let opExtentBits = 18; @@ -21909,6 +21952,30 @@ let isPredicateLate = 1; let isSoloAX = 1; let mayStore = 1; } +def S2_storew_rl_at_vi : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"memw_rl($Rs32):at = $Rt32", +tc_7af3a37e, TypeST>, Enc_ca3887, Requires<[HasV68]> { +let Inst{7-2} = 0b000010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10100000101; +let accessSize = WordAccess; +let isSolo = 1; +let mayStore = 1; +} +def S2_storew_rl_st_vi : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"memw_rl($Rs32):st = $Rt32", +tc_7af3a37e, TypeST>, Enc_ca3887, Requires<[HasV68]> { +let Inst{7-2} = 0b001010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10100000101; +let accessSize = WordAccess; +let isSolo = 1; +let mayStore = 1; +} def S2_svsathb : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), @@ -22218,8 +22285,8 @@ let Inst{13-5} = 0b000000111; let Inst{31-21} = 0b10001100010; let hasNewValue = 1; let opNewValue = 0; -let isReMaterializable = 1; let isAsCheapAsAMove = 1; +let isReMaterializable = 1; } def S2_vsplatrh : HInst< (outs DoubleRegs:$Rdd32), @@ -22228,8 +22295,8 @@ def S2_vsplatrh : HInst< tc_9f6cd987, TypeS_2op>, Enc_3a3d62 { let Inst{13-5} = 0b000000010; let Inst{31-21} = 0b10000100010; -let isReMaterializable = 1; let isAsCheapAsAMove = 1; +let isReMaterializable = 1; } def S2_vspliceib : HInst< (outs DoubleRegs:$Rdd32), @@ -22255,8 +22322,8 @@ def S2_vsxtbh : HInst< tc_9f6cd987, TypeS_2op>, Enc_3a3d62 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10000100000; -let isReMaterializable = 1; let isAsCheapAsAMove = 1; +let isReMaterializable = 1; } def S2_vsxthw : HInst< (outs DoubleRegs:$Rdd32), @@ -22265,8 +22332,8 @@ def S2_vsxthw : HInst< tc_9f6cd987, TypeS_2op>, Enc_3a3d62 { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10000100000; -let isReMaterializable = 1; let isAsCheapAsAMove = 1; +let isReMaterializable = 1; } def S2_vtrunehb : HInst< (outs IntRegs:$Rd32), @@ -22313,8 +22380,8 @@ def S2_vzxtbh : HInst< tc_9f6cd987, TypeS_2op>, Enc_3a3d62 { let Inst{13-5} = 0b000000010; let Inst{31-21} = 0b10000100000; -let isReMaterializable = 1; let isAsCheapAsAMove = 1; +let isReMaterializable = 1; } def S2_vzxthw : HInst< (outs DoubleRegs:$Rdd32), @@ -22323,8 +22390,8 @@ def S2_vzxthw : HInst< tc_9f6cd987, TypeS_2op>, Enc_3a3d62 { let Inst{13-5} = 0b000000110; let Inst{31-21} = 0b10000100000; -let isReMaterializable = 1; let isAsCheapAsAMove = 1; +let isReMaterializable = 1; } def S4_addaddi : HInst< (outs IntRegs:$Rd32), @@ -24521,6 +24588,30 @@ let isPredicateLate = 1; let isSoloAX = 1; let mayStore = 1; } +def S4_stored_rl_at_vi : HInst< +(outs), +(ins IntRegs:$Rs32, DoubleRegs:$Rtt32), +"memd_rl($Rs32):at = $Rtt32", +tc_7af3a37e, TypeST>, Enc_e6abcf, Requires<[HasV68]> { +let Inst{7-2} = 0b000010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10100000111; +let accessSize = DoubleWordAccess; +let isSolo = 1; +let mayStore = 1; +} +def S4_stored_rl_st_vi : HInst< +(outs), +(ins IntRegs:$Rs32, DoubleRegs:$Rtt32), +"memd_rl($Rs32):st = $Rtt32", +tc_7af3a37e, TypeST>, Enc_e6abcf, Requires<[HasV68]> { +let Inst{7-2} = 0b001010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10100000111; +let accessSize = DoubleWordAccess; +let isSolo = 1; +let mayStore = 1; +} def S4_storeirb_io : HInst< (outs), (ins IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II), @@ -25800,7 +25891,7 @@ let Inst{31-21} = 0b11000001100; } def SA1_addi : HInst< (outs GeneralSubRegs:$Rx16), -(ins IntRegs:$Rx16in, s32_0Imm:$Ii), +(ins GeneralSubRegs:$Rx16in, s32_0Imm:$Ii), "$Rx16 = add($Rx16in,#$Ii)", tc_5b347363, TypeSUBINSN>, Enc_93af4c { let Inst{12-11} = 0b00; @@ -25817,7 +25908,7 @@ let Constraints = "$Rx16 = $Rx16in"; } def SA1_addrx : HInst< (outs GeneralSubRegs:$Rx16), -(ins IntRegs:$Rx16in, GeneralSubRegs:$Rs16), +(ins GeneralSubRegs:$Rx16in, GeneralSubRegs:$Rs16), "$Rx16 = add($Rx16in,$Rs16)", tc_5b347363, TypeSUBINSN>, Enc_0527db { let Inst{12-8} = 0b11000; @@ -27221,6 +27312,86 @@ let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; } +def V6_v6mpyhubs10 : HInst< +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, HvxWR:$Vvv32, u2_0Imm:$Ii), +"$Vdd32.w = v6mpy($Vuu32.ub,$Vvv32.b,#$Ii):h", +tc_2b4c548e, TypeCVI_VX_DV>, Enc_b91167, Requires<[UseHVXV68]> { +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011111010; +let hasNewValue = 1; +let opNewValue = 0; +let isCVI = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_v6mpyhubs10_alt : HInst< +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, HvxWR:$Vvv32, u2_0Imm:$Ii), +"$Vdd32.w = v6mpy($Vuu32.ub,$Vvv32.b10,#$Ii):h", +PSEUDO, TypeMAPPING>, Requires<[UseHVXV68]> { +let hasNewValue = 1; +let opNewValue = 0; +let isCVI = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_v6mpyhubs10_vxx : HInst< +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, HvxWR:$Vvv32, u2_0Imm:$Ii), +"$Vxx32.w += v6mpy($Vuu32.ub,$Vvv32.b,#$Ii):h", +tc_bb599486, TypeCVI_VX_DV>, Enc_f4f57b, Requires<[UseHVXV68]> { +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011111001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isCVI = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_v6mpyvubs10 : HInst< +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, HvxWR:$Vvv32, u2_0Imm:$Ii), +"$Vdd32.w = v6mpy($Vuu32.ub,$Vvv32.b,#$Ii):v", +tc_2b4c548e, TypeCVI_VX_DV>, Enc_b91167, Requires<[UseHVXV68]> { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011111010; +let hasNewValue = 1; +let opNewValue = 0; +let isCVI = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_v6mpyvubs10_alt : HInst< +(outs HvxWR:$Vdd32), +(ins HvxWR:$Vuu32, HvxWR:$Vvv32, u2_0Imm:$Ii), +"$Vdd32.w = v6mpy($Vuu32.ub,$Vvv32.b10,#$Ii):v", +PSEUDO, TypeMAPPING>, Requires<[UseHVXV68]> { +let hasNewValue = 1; +let opNewValue = 0; +let isCVI = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_v6mpyvubs10_vxx : HInst< +(outs HvxWR:$Vxx32), +(ins HvxWR:$Vxx32in, HvxWR:$Vuu32, HvxWR:$Vvv32, u2_0Imm:$Ii), +"$Vxx32.w += v6mpy($Vuu32.ub,$Vvv32.b,#$Ii):v", +tc_bb599486, TypeCVI_VX_DV>, Enc_f4f57b, Requires<[UseHVXV68]> { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011111001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isCVI = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} def V6_vL32Ub_ai : HInst< (outs HvxVR:$Vd32), (ins IntRegs:$Rt32, s4_0Imm:$Ii), @@ -27966,6 +28137,7 @@ let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; let isCVI = 1; +let hasTmpDst = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -27988,6 +28160,7 @@ let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; let isCVI = 1; +let hasTmpDst = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -28010,6 +28183,7 @@ let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; let isCVI = 1; +let hasTmpDst = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -28032,6 +28206,7 @@ let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; let isCVI = 1; +let hasTmpDst = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -28053,6 +28228,7 @@ let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; let isCVI = 1; +let hasTmpDst = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -28074,6 +28250,7 @@ let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; let isCVI = 1; +let hasTmpDst = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -28096,6 +28273,7 @@ let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; let isCVI = 1; +let hasTmpDst = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -28117,6 +28295,7 @@ let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; let isCVI = 1; +let hasTmpDst = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -28138,6 +28317,7 @@ let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; let isCVI = 1; +let hasTmpDst = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -28262,6 +28442,7 @@ let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; let isCVI = 1; +let hasTmpDst = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_tmp_ai"; @@ -28283,6 +28464,7 @@ let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; let isCVI = 1; +let hasTmpDst = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_tmp_ai"; @@ -28304,6 +28486,7 @@ let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; let isCVI = 1; +let hasTmpDst = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_tmp_pi"; @@ -28325,6 +28508,7 @@ let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; let isCVI = 1; +let hasTmpDst = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_tmp_ppu"; @@ -28345,6 +28529,7 @@ let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; let isCVI = 1; +let hasTmpDst = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_tmp_pi"; @@ -28365,6 +28550,7 @@ let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; let isCVI = 1; +let hasTmpDst = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_tmp_ppu"; @@ -28386,6 +28572,7 @@ let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; let isCVI = 1; +let hasTmpDst = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_tmp_ai"; @@ -28406,6 +28593,7 @@ let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; let isCVI = 1; +let hasTmpDst = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_tmp_pi"; @@ -28426,6 +28614,7 @@ let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; let isCVI = 1; +let hasTmpDst = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_tmp_ppu"; @@ -32646,7 +32835,7 @@ def V6_vgathermh : HInst< (outs), (ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32), "vtmp.h = vgather($Rt32,$Mu2,$Vv32.h).h", -tc_e8797b98, TypeCVI_GATHER>, Enc_8b8927, Requires<[UseHVXV65]> { +tc_a28f32b5, TypeCVI_GATHER>, Enc_8b8927, Requires<[UseHVXV65]> { let Inst{12-5} = 0b00001000; let Inst{31-21} = 0b00101111000; let hasNewValue = 1; @@ -32663,7 +32852,7 @@ def V6_vgathermhq : HInst< (outs), (ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32), "if ($Qs4) vtmp.h = vgather($Rt32,$Mu2,$Vv32.h).h", -tc_05ac6f98, TypeCVI_GATHER>, Enc_158beb, Requires<[UseHVXV65]> { +tc_7d68d5c2, TypeCVI_GATHER>, Enc_158beb, Requires<[UseHVXV65]> { let Inst{12-7} = 0b001010; let Inst{31-21} = 0b00101111000; let hasNewValue = 1; @@ -32680,7 +32869,7 @@ def V6_vgathermhw : HInst< (outs), (ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32), "vtmp.h = vgather($Rt32,$Mu2,$Vvv32.w).h", -tc_05058f6f, TypeCVI_GATHER_DV>, Enc_28dcbb, Requires<[UseHVXV65]> { +tc_7095ecba, TypeCVI_GATHER_DV>, Enc_28dcbb, Requires<[UseHVXV65]> { let Inst{12-5} = 0b00010000; let Inst{31-21} = 0b00101111000; let hasNewValue = 1; @@ -32697,7 +32886,7 @@ def V6_vgathermhwq : HInst< (outs), (ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32), "if ($Qs4) vtmp.h = vgather($Rt32,$Mu2,$Vvv32.w).h", -tc_fd7610da, TypeCVI_GATHER_DV>, Enc_4e4a80, Requires<[UseHVXV65]> { +tc_a69eeee1, TypeCVI_GATHER_DV>, Enc_4e4a80, Requires<[UseHVXV65]> { let Inst{12-7} = 0b001100; let Inst{31-21} = 0b00101111000; let hasNewValue = 1; @@ -32714,7 +32903,7 @@ def V6_vgathermw : HInst< (outs), (ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32), "vtmp.w = vgather($Rt32,$Mu2,$Vv32.w).w", -tc_e8797b98, TypeCVI_GATHER>, Enc_8b8927, Requires<[UseHVXV65]> { +tc_a28f32b5, TypeCVI_GATHER>, Enc_8b8927, Requires<[UseHVXV65]> { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b00101111000; let hasNewValue = 1; @@ -32731,7 +32920,7 @@ def V6_vgathermwq : HInst< (outs), (ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32), "if ($Qs4) vtmp.w = vgather($Rt32,$Mu2,$Vv32.w).w", -tc_05ac6f98, TypeCVI_GATHER>, Enc_158beb, Requires<[UseHVXV65]> { +tc_7d68d5c2, TypeCVI_GATHER>, Enc_158beb, Requires<[UseHVXV65]> { let Inst{12-7} = 0b001000; let Inst{31-21} = 0b00101111000; let hasNewValue = 1; @@ -36155,7 +36344,7 @@ let Constraints = "$Vyyyy32 = $Vyyyy32in"; } def V6_vrmpyzbb_rx : HInst< (outs HvxVQR:$Vdddd32, IntRegsLow8:$Rx8), -(ins HvxVR:$Vu32, IntRegs:$Rx8in), +(ins HvxVR:$Vu32, IntRegsLow8:$Rx8in), "$Vdddd32.w = vrmpyz($Vu32.b,$Rx8.b++)", tc_26a377fe, TypeCVI_4SLOT_MPY>, Enc_3b7631, Requires<[UseHVXV66,UseZReg]> { let Inst{7-5} = 0b000; @@ -36169,7 +36358,7 @@ let Constraints = "$Rx8 = $Rx8in"; } def V6_vrmpyzbb_rx_acc : HInst< (outs HvxVQR:$Vyyyy32, IntRegsLow8:$Rx8), -(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegs:$Rx8in), +(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rx8in), "$Vyyyy32.w += vrmpyz($Vu32.b,$Rx8.b++)", tc_2d4051cd, TypeCVI_4SLOT_MPY>, Enc_bddee3, Requires<[UseHVXV66,UseZReg]> { let Inst{7-5} = 0b010; @@ -36212,7 +36401,7 @@ let Constraints = "$Vyyyy32 = $Vyyyy32in"; } def V6_vrmpyzbub_rx : HInst< (outs HvxVQR:$Vdddd32, IntRegsLow8:$Rx8), -(ins HvxVR:$Vu32, IntRegs:$Rx8in), +(ins HvxVR:$Vu32, IntRegsLow8:$Rx8in), "$Vdddd32.w = vrmpyz($Vu32.b,$Rx8.ub++)", tc_26a377fe, TypeCVI_4SLOT_MPY>, Enc_3b7631, Requires<[UseHVXV66,UseZReg]> { let Inst{7-5} = 0b010; @@ -36226,7 +36415,7 @@ let Constraints = "$Rx8 = $Rx8in"; } def V6_vrmpyzbub_rx_acc : HInst< (outs HvxVQR:$Vyyyy32, IntRegsLow8:$Rx8), -(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegs:$Rx8in), +(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rx8in), "$Vyyyy32.w += vrmpyz($Vu32.b,$Rx8.ub++)", tc_2d4051cd, TypeCVI_4SLOT_MPY>, Enc_bddee3, Requires<[UseHVXV66,UseZReg]> { let Inst{7-5} = 0b001; @@ -36269,7 +36458,7 @@ let Constraints = "$Vyyyy32 = $Vyyyy32in"; } def V6_vrmpyzcb_rx : HInst< (outs HvxVQR:$Vdddd32, IntRegsLow8:$Rx8), -(ins HvxVR:$Vu32, IntRegs:$Rx8in), +(ins HvxVR:$Vu32, IntRegsLow8:$Rx8in), "$Vdddd32.w = vr16mpyz($Vu32.c,$Rx8.b++)", tc_26a377fe, TypeCVI_4SLOT_MPY>, Enc_3b7631, Requires<[UseHVXV66,UseZReg]> { let Inst{7-5} = 0b001; @@ -36283,7 +36472,7 @@ let Constraints = "$Rx8 = $Rx8in"; } def V6_vrmpyzcb_rx_acc : HInst< (outs HvxVQR:$Vyyyy32, IntRegsLow8:$Rx8), -(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegs:$Rx8in), +(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rx8in), "$Vyyyy32.w += vr16mpyz($Vu32.c,$Rx8.b++)", tc_2d4051cd, TypeCVI_4SLOT_MPY>, Enc_bddee3, Requires<[UseHVXV66,UseZReg]> { let Inst{7-5} = 0b011; @@ -36326,7 +36515,7 @@ let Constraints = "$Vyyyy32 = $Vyyyy32in"; } def V6_vrmpyzcbs_rx : HInst< (outs HvxVQR:$Vdddd32, IntRegsLow8:$Rx8), -(ins HvxVR:$Vu32, IntRegs:$Rx8in), +(ins HvxVR:$Vu32, IntRegsLow8:$Rx8in), "$Vdddd32.w = vr16mpyzs($Vu32.c,$Rx8.b++)", tc_26a377fe, TypeCVI_4SLOT_MPY>, Enc_3b7631, Requires<[UseHVXV66,UseZReg]> { let Inst{7-5} = 0b010; @@ -36340,7 +36529,7 @@ let Constraints = "$Rx8 = $Rx8in"; } def V6_vrmpyzcbs_rx_acc : HInst< (outs HvxVQR:$Vyyyy32, IntRegsLow8:$Rx8), -(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegs:$Rx8in), +(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rx8in), "$Vyyyy32.w += vr16mpyzs($Vu32.c,$Rx8.b++)", tc_2d4051cd, TypeCVI_4SLOT_MPY>, Enc_bddee3, Requires<[UseHVXV66,UseZReg]> { let Inst{7-5} = 0b001; @@ -36383,7 +36572,7 @@ let Constraints = "$Vyyyy32 = $Vyyyy32in"; } def V6_vrmpyznb_rx : HInst< (outs HvxVQR:$Vdddd32, IntRegsLow8:$Rx8), -(ins HvxVR:$Vu32, IntRegs:$Rx8in), +(ins HvxVR:$Vu32, IntRegsLow8:$Rx8in), "$Vdddd32.w = vr8mpyz($Vu32.n,$Rx8.b++)", tc_26a377fe, TypeCVI_4SLOT_MPY>, Enc_3b7631, Requires<[UseHVXV66,UseZReg]> { let Inst{7-5} = 0b000; @@ -36397,7 +36586,7 @@ let Constraints = "$Rx8 = $Rx8in"; } def V6_vrmpyznb_rx_acc : HInst< (outs HvxVQR:$Vyyyy32, IntRegsLow8:$Rx8), -(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegs:$Rx8in), +(ins HvxVQR:$Vyyyy32in, HvxVR:$Vu32, IntRegsLow8:$Rx8in), "$Vyyyy32.w += vr8mpyz($Vu32.n,$Rx8.b++)", tc_2d4051cd, TypeCVI_4SLOT_MPY>, Enc_bddee3, Requires<[UseHVXV66,UseZReg]> { let Inst{7-5} = 0b010; @@ -38685,7 +38874,7 @@ def Y2_wait : HInst< (outs), (ins IntRegs:$Rs32), "wait($Rs32)", -tc_d7718fbe, TypeCR>, Enc_ecbcc8 { +tc_2c3e17fc, TypeCR>, Enc_ecbcc8, Requires<[HasV65]> { let Inst{13-0} = 0b00000000000000; let Inst{31-21} = 0b01100100010; let isSolo = 1; @@ -38699,8 +38888,8 @@ let Inst{7-0} = 0b00000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10100110000; let isSoloAX = 1; -let mayStore = 1; let hasSideEffects = 1; +let mayStore = 1; } def Y4_trace : HInst< (outs), @@ -38720,8 +38909,8 @@ let Inst{7-0} = 0b00000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10100110100; let isSoloAX = 1; -let mayStore = 1; let hasSideEffects = 1; +let mayStore = 1; } def Y6_diag : HInst< (outs), @@ -38749,6 +38938,74 @@ let Inst{7-0} = 0b01100000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b01100010010; } +def Y6_dmlink : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"dmlink($Rs32,$Rt32)", +tc_7af3a37e, TypeST>, Enc_ca3887, Requires<[HasV68]> { +let Inst{7-0} = 0b01000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10100110000; +let hasSideEffects = 1; +let isSolo = 1; +let mayStore = 1; +} +def Y6_dmpause : HInst< +(outs IntRegs:$Rd32), +(ins), +"$Rd32 = dmpause", +tc_4bf903b0, TypeST>, Enc_a4ef14, Requires<[HasV68]> { +let Inst{13-5} = 0b000000011; +let Inst{31-16} = 0b1010100000000000; +let hasNewValue = 1; +let opNewValue = 0; +let hasSideEffects = 1; +let isSolo = 1; +} +def Y6_dmpoll : HInst< +(outs IntRegs:$Rd32), +(ins), +"$Rd32 = dmpoll", +tc_4bf903b0, TypeST>, Enc_a4ef14, Requires<[HasV68]> { +let Inst{13-5} = 0b000000010; +let Inst{31-16} = 0b1010100000000000; +let hasNewValue = 1; +let opNewValue = 0; +let hasSideEffects = 1; +let isSolo = 1; +} +def Y6_dmresume : HInst< +(outs), +(ins IntRegs:$Rs32), +"dmresume($Rs32)", +tc_db96aa6b, TypeST>, Enc_ecbcc8, Requires<[HasV68]> { +let Inst{13-0} = 0b00000010000000; +let Inst{31-21} = 0b10100110000; +let hasSideEffects = 1; +let isSolo = 1; +} +def Y6_dmstart : HInst< +(outs), +(ins IntRegs:$Rs32), +"dmstart($Rs32)", +tc_db96aa6b, TypeST>, Enc_ecbcc8, Requires<[HasV68]> { +let Inst{13-0} = 0b00000000100000; +let Inst{31-21} = 0b10100110000; +let hasSideEffects = 1; +let isSolo = 1; +} +def Y6_dmwait : HInst< +(outs IntRegs:$Rd32), +(ins), +"$Rd32 = dmwait", +tc_4bf903b0, TypeST>, Enc_a4ef14, Requires<[HasV68]> { +let Inst{13-5} = 0b000000001; +let Inst{31-16} = 0b1010100000000000; +let hasNewValue = 1; +let opNewValue = 0; +let hasSideEffects = 1; +let isSolo = 1; +} def dep_A2_addsat : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), @@ -38788,7 +39045,7 @@ def dup_A2_add : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = add($Rs32,$Rt32)", -tc_388f9897, TypeALU32_3op>, Requires<[HasV67]> { +tc_388f9897, TypeALU32_3op>, Requires<[HasV68]> { let hasNewValue = 1; let opNewValue = 0; let AsmVariantName = "NonParsable"; @@ -38798,7 +39055,7 @@ def dup_A2_addi : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Rd32 = add($Rs32,#$Ii)", -tc_388f9897, TypeALU32_ADDI>, Requires<[HasV67]> { +tc_388f9897, TypeALU32_ADDI>, Requires<[HasV68]> { let hasNewValue = 1; let opNewValue = 0; let AsmVariantName = "NonParsable"; @@ -38813,7 +39070,7 @@ def dup_A2_andir : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Rd32 = and($Rs32,#$Ii)", -tc_388f9897, TypeALU32_2op>, Requires<[HasV67]> { +tc_388f9897, TypeALU32_2op>, Requires<[HasV68]> { let hasNewValue = 1; let opNewValue = 0; let AsmVariantName = "NonParsable"; @@ -38828,7 +39085,7 @@ def dup_A2_combineii : HInst< (outs DoubleRegs:$Rdd32), (ins s32_0Imm:$Ii, s8_0Imm:$II), "$Rdd32 = combine(#$Ii,#$II)", -tc_388f9897, TypeALU32_2op>, Requires<[HasV67]> { +tc_388f9897, TypeALU32_2op>, Requires<[HasV68]> { let AsmVariantName = "NonParsable"; let isPseudo = 1; let isExtendable = 1; @@ -38841,7 +39098,7 @@ def dup_A2_sxtb : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = sxtb($Rs32)", -tc_9124c04f, TypeALU32_2op>, Requires<[HasV67]> { +tc_9124c04f, TypeALU32_2op>, Requires<[HasV68]> { let hasNewValue = 1; let opNewValue = 0; let AsmVariantName = "NonParsable"; @@ -38851,7 +39108,7 @@ def dup_A2_sxth : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = sxth($Rs32)", -tc_9124c04f, TypeALU32_2op>, Requires<[HasV67]> { +tc_9124c04f, TypeALU32_2op>, Requires<[HasV68]> { let hasNewValue = 1; let opNewValue = 0; let AsmVariantName = "NonParsable"; @@ -38861,7 +39118,7 @@ def dup_A2_tfr : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = $Rs32", -tc_9124c04f, TypeALU32_2op>, Requires<[HasV67]> { +tc_9124c04f, TypeALU32_2op>, Requires<[HasV68]> { let hasNewValue = 1; let opNewValue = 0; let AsmVariantName = "NonParsable"; @@ -38871,7 +39128,7 @@ def dup_A2_tfrsi : HInst< (outs IntRegs:$Rd32), (ins s32_0Imm:$Ii), "$Rd32 = #$Ii", -tc_9124c04f, TypeALU32_2op>, Requires<[HasV67]> { +tc_9124c04f, TypeALU32_2op>, Requires<[HasV68]> { let hasNewValue = 1; let opNewValue = 0; let AsmVariantName = "NonParsable"; @@ -38886,7 +39143,7 @@ def dup_A2_zxtb : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = zxtb($Rs32)", -PSEUDO, TypeMAPPING>, Requires<[HasV67]> { +PSEUDO, TypeMAPPING>, Requires<[HasV68]> { let hasNewValue = 1; let opNewValue = 0; let AsmVariantName = "NonParsable"; @@ -38896,7 +39153,7 @@ def dup_A2_zxth : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = zxth($Rs32)", -tc_9124c04f, TypeALU32_2op>, Requires<[HasV67]> { +tc_9124c04f, TypeALU32_2op>, Requires<[HasV68]> { let hasNewValue = 1; let opNewValue = 0; let AsmVariantName = "NonParsable"; @@ -38906,7 +39163,7 @@ def dup_A4_combineii : HInst< (outs DoubleRegs:$Rdd32), (ins s8_0Imm:$Ii, u32_0Imm:$II), "$Rdd32 = combine(#$Ii,#$II)", -tc_388f9897, TypeALU32_2op>, Requires<[HasV67]> { +tc_388f9897, TypeALU32_2op>, Requires<[HasV68]> { let AsmVariantName = "NonParsable"; let isPseudo = 1; let isExtendable = 1; @@ -38919,7 +39176,7 @@ def dup_A4_combineir : HInst< (outs DoubleRegs:$Rdd32), (ins s32_0Imm:$Ii, IntRegs:$Rs32), "$Rdd32 = combine(#$Ii,$Rs32)", -tc_388f9897, TypeALU32_2op>, Requires<[HasV67]> { +tc_388f9897, TypeALU32_2op>, Requires<[HasV68]> { let AsmVariantName = "NonParsable"; let isPseudo = 1; let isExtendable = 1; @@ -38932,7 +39189,7 @@ def dup_A4_combineri : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Rdd32 = combine($Rs32,#$Ii)", -tc_388f9897, TypeALU32_2op>, Requires<[HasV67]> { +tc_388f9897, TypeALU32_2op>, Requires<[HasV68]> { let AsmVariantName = "NonParsable"; let isPseudo = 1; let isExtendable = 1; @@ -38945,7 +39202,7 @@ def dup_C2_cmoveif : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, s32_0Imm:$Ii), "if (!$Pu4) $Rd32 = #$Ii", -tc_388f9897, TypeALU32_2op>, Requires<[HasV67]> { +tc_388f9897, TypeALU32_2op>, Requires<[HasV68]> { let isPredicated = 1; let isPredicatedFalse = 1; let hasNewValue = 1; @@ -38962,7 +39219,7 @@ def dup_C2_cmoveit : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, s32_0Imm:$Ii), "if ($Pu4) $Rd32 = #$Ii", -tc_388f9897, TypeALU32_2op>, Requires<[HasV67]> { +tc_388f9897, TypeALU32_2op>, Requires<[HasV68]> { let isPredicated = 1; let hasNewValue = 1; let opNewValue = 0; @@ -38978,7 +39235,7 @@ def dup_C2_cmovenewif : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, s32_0Imm:$Ii), "if (!$Pu4.new) $Rd32 = #$Ii", -tc_4ac61d92, TypeALU32_2op>, Requires<[HasV67]> { +tc_4ac61d92, TypeALU32_2op>, Requires<[HasV68]> { let isPredicated = 1; let isPredicatedFalse = 1; let hasNewValue = 1; @@ -38996,7 +39253,7 @@ def dup_C2_cmovenewit : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, s32_0Imm:$Ii), "if ($Pu4.new) $Rd32 = #$Ii", -tc_4ac61d92, TypeALU32_2op>, Requires<[HasV67]> { +tc_4ac61d92, TypeALU32_2op>, Requires<[HasV68]> { let isPredicated = 1; let hasNewValue = 1; let opNewValue = 0; @@ -39013,7 +39270,7 @@ def dup_C2_cmpeqi : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Pd4 = cmp.eq($Rs32,#$Ii)", -tc_388f9897, TypeALU32_2op>, Requires<[HasV67]> { +tc_388f9897, TypeALU32_2op>, Requires<[HasV68]> { let AsmVariantName = "NonParsable"; let isPseudo = 1; let isExtendable = 1; @@ -39026,7 +39283,7 @@ def dup_L2_deallocframe : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = deallocframe($Rs32):raw", -tc_aee6250c, TypeLD>, Requires<[HasV67]> { +tc_aee6250c, TypeLD>, Requires<[HasV68]> { let accessSize = DoubleWordAccess; let AsmVariantName = "NonParsable"; let mayLoad = 1; @@ -39038,7 +39295,7 @@ def dup_L2_loadrb_io : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Rd32 = memb($Rs32+#$Ii)", -tc_eed07714, TypeLD>, Requires<[HasV67]> { +tc_eed07714, TypeLD>, Requires<[HasV68]> { let hasNewValue = 1; let opNewValue = 0; let addrMode = BaseImmOffset; @@ -39056,7 +39313,7 @@ def dup_L2_loadrd_io : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, s29_3Imm:$Ii), "$Rdd32 = memd($Rs32+#$Ii)", -tc_eed07714, TypeLD>, Requires<[HasV67]> { +tc_eed07714, TypeLD>, Requires<[HasV68]> { let addrMode = BaseImmOffset; let accessSize = DoubleWordAccess; let AsmVariantName = "NonParsable"; @@ -39072,7 +39329,7 @@ def dup_L2_loadrh_io : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s31_1Imm:$Ii), "$Rd32 = memh($Rs32+#$Ii)", -tc_eed07714, TypeLD>, Requires<[HasV67]> { +tc_eed07714, TypeLD>, Requires<[HasV68]> { let hasNewValue = 1; let opNewValue = 0; let addrMode = BaseImmOffset; @@ -39090,7 +39347,7 @@ def dup_L2_loadri_io : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s30_2Imm:$Ii), "$Rd32 = memw($Rs32+#$Ii)", -tc_eed07714, TypeLD>, Requires<[HasV67]> { +tc_eed07714, TypeLD>, Requires<[HasV68]> { let hasNewValue = 1; let opNewValue = 0; let addrMode = BaseImmOffset; @@ -39108,7 +39365,7 @@ def dup_L2_loadrub_io : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Rd32 = memub($Rs32+#$Ii)", -tc_eed07714, TypeLD>, Requires<[HasV67]> { +tc_eed07714, TypeLD>, Requires<[HasV68]> { let hasNewValue = 1; let opNewValue = 0; let addrMode = BaseImmOffset; @@ -39126,7 +39383,7 @@ def dup_L2_loadruh_io : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s31_1Imm:$Ii), "$Rd32 = memuh($Rs32+#$Ii)", -tc_eed07714, TypeLD>, Requires<[HasV67]> { +tc_eed07714, TypeLD>, Requires<[HasV68]> { let hasNewValue = 1; let opNewValue = 0; let addrMode = BaseImmOffset; @@ -39144,7 +39401,7 @@ def dup_S2_allocframe : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, u11_3Imm:$Ii), "allocframe($Rx32,#$Ii):raw", -tc_74a42bda, TypeST>, Requires<[HasV67]> { +tc_74a42bda, TypeST>, Requires<[HasV68]> { let hasNewValue = 1; let opNewValue = 0; let addrMode = BaseImmOffset; @@ -39160,7 +39417,7 @@ def dup_S2_storerb_io : HInst< (outs), (ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Rt32), "memb($Rs32+#$Ii) = $Rt32", -tc_a9edeffa, TypeST>, Requires<[HasV67]> { +tc_a9edeffa, TypeST>, Requires<[HasV68]> { let addrMode = BaseImmOffset; let accessSize = ByteAccess; let AsmVariantName = "NonParsable"; @@ -39176,7 +39433,7 @@ def dup_S2_storerd_io : HInst< (outs), (ins IntRegs:$Rs32, s29_3Imm:$Ii, DoubleRegs:$Rtt32), "memd($Rs32+#$Ii) = $Rtt32", -tc_a9edeffa, TypeST>, Requires<[HasV67]> { +tc_a9edeffa, TypeST>, Requires<[HasV68]> { let addrMode = BaseImmOffset; let accessSize = DoubleWordAccess; let AsmVariantName = "NonParsable"; @@ -39192,7 +39449,7 @@ def dup_S2_storerh_io : HInst< (outs), (ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Rt32), "memh($Rs32+#$Ii) = $Rt32", -tc_a9edeffa, TypeST>, Requires<[HasV67]> { +tc_a9edeffa, TypeST>, Requires<[HasV68]> { let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let AsmVariantName = "NonParsable"; @@ -39208,7 +39465,7 @@ def dup_S2_storeri_io : HInst< (outs), (ins IntRegs:$Rs32, s30_2Imm:$Ii, IntRegs:$Rt32), "memw($Rs32+#$Ii) = $Rt32", -tc_a9edeffa, TypeST>, Requires<[HasV67]> { +tc_a9edeffa, TypeST>, Requires<[HasV68]> { let addrMode = BaseImmOffset; let accessSize = WordAccess; let AsmVariantName = "NonParsable"; @@ -39224,7 +39481,7 @@ def dup_S4_storeirb_io : HInst< (outs), (ins IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II), "memb($Rs32+#$Ii) = #$II", -tc_838c4d7a, TypeV4LDST>, Requires<[HasV67]> { +tc_838c4d7a, TypeV4LDST>, Requires<[HasV68]> { let addrMode = BaseImmOffset; let accessSize = ByteAccess; let AsmVariantName = "NonParsable"; @@ -39240,7 +39497,7 @@ def dup_S4_storeiri_io : HInst< (outs), (ins IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II), "memw($Rs32+#$Ii) = #$II", -tc_838c4d7a, TypeV4LDST>, Requires<[HasV67]> { +tc_838c4d7a, TypeV4LDST>, Requires<[HasV68]> { let addrMode = BaseImmOffset; let accessSize = WordAccess; let AsmVariantName = "NonParsable"; diff --git a/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td b/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td index 0143d6f44d8..e5c78d122c9 100644 --- a/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td +++ b/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td @@ -11,92 +11,452 @@ // V5 Scalar Instructions. -def: Pat<(int_hexagon_C2_cmpeq IntRegs:$src1, IntRegs:$src2), - (C2_tfrpr (C2_cmpeq IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_cmpgt IntRegs:$src1, IntRegs:$src2), - (C2_tfrpr (C2_cmpgt IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_cmpgtu IntRegs:$src1, IntRegs:$src2), - (C2_tfrpr (C2_cmpgtu IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_cmpeqp DoubleRegs:$src1, DoubleRegs:$src2), - (C2_tfrpr (C2_cmpeqp DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_cmpgtp DoubleRegs:$src1, DoubleRegs:$src2), - (C2_tfrpr (C2_cmpgtp DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_cmpgtup DoubleRegs:$src1, DoubleRegs:$src2), - (C2_tfrpr (C2_cmpgtup DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_rcmpeqi IntRegs:$src1, s32_0ImmPred_timm:$src2), - (A4_rcmpeqi IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_rcmpneqi IntRegs:$src1, s32_0ImmPred_timm:$src2), - (A4_rcmpneqi IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_abs IntRegs:$src1), + (A2_abs IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_absp DoubleRegs:$src1), + (A2_absp DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_abssat IntRegs:$src1), + (A2_abssat IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_add IntRegs:$src1, IntRegs:$src2), + (A2_add IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addh_h16_hh IntRegs:$src1, IntRegs:$src2), + (A2_addh_h16_hh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addh_h16_hl IntRegs:$src1, IntRegs:$src2), + (A2_addh_h16_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addh_h16_lh IntRegs:$src1, IntRegs:$src2), + (A2_addh_h16_lh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addh_h16_ll IntRegs:$src1, IntRegs:$src2), + (A2_addh_h16_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addh_h16_sat_hh IntRegs:$src1, IntRegs:$src2), + (A2_addh_h16_sat_hh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addh_h16_sat_hl IntRegs:$src1, IntRegs:$src2), + (A2_addh_h16_sat_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addh_h16_sat_lh IntRegs:$src1, IntRegs:$src2), + (A2_addh_h16_sat_lh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addh_h16_sat_ll IntRegs:$src1, IntRegs:$src2), + (A2_addh_h16_sat_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addh_l16_hl IntRegs:$src1, IntRegs:$src2), + (A2_addh_l16_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addh_l16_ll IntRegs:$src1, IntRegs:$src2), + (A2_addh_l16_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addh_l16_sat_hl IntRegs:$src1, IntRegs:$src2), + (A2_addh_l16_sat_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addh_l16_sat_ll IntRegs:$src1, IntRegs:$src2), + (A2_addh_l16_sat_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addi IntRegs:$src1, s32_0ImmPred_timm:$src2), + (A2_addi IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addp DoubleRegs:$src1, DoubleRegs:$src2), + (A2_addp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addpsat DoubleRegs:$src1, DoubleRegs:$src2), + (A2_addpsat DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addsat IntRegs:$src1, IntRegs:$src2), + (A2_addsat IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_addsp IntRegs:$src1, DoubleRegs:$src2), + (A2_addsp IntRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_and IntRegs:$src1, IntRegs:$src2), + (A2_and IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_andir IntRegs:$src1, s32_0ImmPred_timm:$src2), + (A2_andir IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_andp DoubleRegs:$src1, DoubleRegs:$src2), + (A2_andp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_aslh IntRegs:$src1), + (A2_aslh IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_asrh IntRegs:$src1), + (A2_asrh IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_combine_hh IntRegs:$src1, IntRegs:$src2), + (A2_combine_hh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_combine_hl IntRegs:$src1, IntRegs:$src2), + (A2_combine_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_combine_lh IntRegs:$src1, IntRegs:$src2), + (A2_combine_lh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_combine_ll IntRegs:$src1, IntRegs:$src2), + (A2_combine_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_combineii s32_0ImmPred_timm:$src1, s8_0ImmPred_timm:$src2), + (A2_combineii s32_0ImmPred_timm:$src1, s8_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_combinew IntRegs:$src1, IntRegs:$src2), + (A2_combinew IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_max IntRegs:$src1, IntRegs:$src2), + (A2_max IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_maxp DoubleRegs:$src1, DoubleRegs:$src2), + (A2_maxp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_maxu IntRegs:$src1, IntRegs:$src2), + (A2_maxu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_maxup DoubleRegs:$src1, DoubleRegs:$src2), + (A2_maxup DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_min IntRegs:$src1, IntRegs:$src2), + (A2_min IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_minp DoubleRegs:$src1, DoubleRegs:$src2), + (A2_minp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_minu IntRegs:$src1, IntRegs:$src2), + (A2_minu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_minup DoubleRegs:$src1, DoubleRegs:$src2), + (A2_minup DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_negp DoubleRegs:$src1), + (A2_negp DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_negsat IntRegs:$src1), + (A2_negsat IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_notp DoubleRegs:$src1), + (A2_notp DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_or IntRegs:$src1, IntRegs:$src2), + (A2_or IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_orir IntRegs:$src1, s32_0ImmPred_timm:$src2), + (A2_orir IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_orp DoubleRegs:$src1, DoubleRegs:$src2), + (A2_orp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_roundsat DoubleRegs:$src1), + (A2_roundsat DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_sat DoubleRegs:$src1), + (A2_sat DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_satb IntRegs:$src1), + (A2_satb IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_sath IntRegs:$src1), + (A2_sath IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_satub IntRegs:$src1), + (A2_satub IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_satuh IntRegs:$src1), + (A2_satuh IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_sub IntRegs:$src1, IntRegs:$src2), + (A2_sub IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subh_h16_hh IntRegs:$src1, IntRegs:$src2), + (A2_subh_h16_hh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subh_h16_hl IntRegs:$src1, IntRegs:$src2), + (A2_subh_h16_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subh_h16_lh IntRegs:$src1, IntRegs:$src2), + (A2_subh_h16_lh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subh_h16_ll IntRegs:$src1, IntRegs:$src2), + (A2_subh_h16_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subh_h16_sat_hh IntRegs:$src1, IntRegs:$src2), + (A2_subh_h16_sat_hh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subh_h16_sat_hl IntRegs:$src1, IntRegs:$src2), + (A2_subh_h16_sat_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subh_h16_sat_lh IntRegs:$src1, IntRegs:$src2), + (A2_subh_h16_sat_lh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subh_h16_sat_ll IntRegs:$src1, IntRegs:$src2), + (A2_subh_h16_sat_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subh_l16_hl IntRegs:$src1, IntRegs:$src2), + (A2_subh_l16_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subh_l16_ll IntRegs:$src1, IntRegs:$src2), + (A2_subh_l16_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subh_l16_sat_hl IntRegs:$src1, IntRegs:$src2), + (A2_subh_l16_sat_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subh_l16_sat_ll IntRegs:$src1, IntRegs:$src2), + (A2_subh_l16_sat_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subp DoubleRegs:$src1, DoubleRegs:$src2), + (A2_subp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subri s32_0ImmPred_timm:$src1, IntRegs:$src2), + (A2_subri s32_0ImmPred_timm:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_subsat IntRegs:$src1, IntRegs:$src2), + (A2_subsat IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_svaddh IntRegs:$src1, IntRegs:$src2), + (A2_svaddh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_svaddhs IntRegs:$src1, IntRegs:$src2), + (A2_svaddhs IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_svadduhs IntRegs:$src1, IntRegs:$src2), + (A2_svadduhs IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_svavgh IntRegs:$src1, IntRegs:$src2), + (A2_svavgh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_svavghs IntRegs:$src1, IntRegs:$src2), + (A2_svavghs IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_svnavgh IntRegs:$src1, IntRegs:$src2), + (A2_svnavgh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_svsubh IntRegs:$src1, IntRegs:$src2), + (A2_svsubh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_svsubhs IntRegs:$src1, IntRegs:$src2), + (A2_svsubhs IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_svsubuhs IntRegs:$src1, IntRegs:$src2), + (A2_svsubuhs IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_swiz IntRegs:$src1), + (A2_swiz IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_sxtb IntRegs:$src1), + (A2_sxtb IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_sxth IntRegs:$src1), + (A2_sxth IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_sxtw IntRegs:$src1), + (A2_sxtw IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_tfr IntRegs:$src1), + (A2_tfr IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_tfrih IntRegs:$src1, u16_0ImmPred_timm:$src2), + (A2_tfrih IntRegs:$src1, u16_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_tfril IntRegs:$src1, u16_0ImmPred_timm:$src2), + (A2_tfril IntRegs:$src1, u16_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_tfrp DoubleRegs:$src1), + (A2_tfrp DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_tfrsi s32_0ImmPred_timm:$src1), + (A2_tfrsi s32_0ImmPred_timm:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vabsh DoubleRegs:$src1), + (A2_vabsh DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vabshsat DoubleRegs:$src1), + (A2_vabshsat DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vabsw DoubleRegs:$src1), + (A2_vabsw DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vabswsat DoubleRegs:$src1), + (A2_vabswsat DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vaddb_map DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vaddub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vaddh DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vaddh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vaddhs DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vaddhs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vaddub DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vaddub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vaddubs DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vaddubs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vadduhs DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vadduhs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vaddw DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vaddw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vaddws DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vaddws DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vavgh DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vavgh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vavghcr DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vavghcr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vavghr DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vavghr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vavgub DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vavgub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vavgubr DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vavgubr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vavguh DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vavguh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vavguhr DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vavguhr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vavguw DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vavguw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vavguwr DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vavguwr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vavgw DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vavgw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vavgwcr DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vavgwcr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vavgwr DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vavgwr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vcmpbeq DoubleRegs:$src1, DoubleRegs:$src2), + (C2_tfrpr (A2_vcmpbeq DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vcmpbgtu DoubleRegs:$src1, DoubleRegs:$src2), + (C2_tfrpr (A2_vcmpbgtu DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vcmpheq DoubleRegs:$src1, DoubleRegs:$src2), + (C2_tfrpr (A2_vcmpheq DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vcmphgt DoubleRegs:$src1, DoubleRegs:$src2), + (C2_tfrpr (A2_vcmphgt DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vcmphgtu DoubleRegs:$src1, DoubleRegs:$src2), + (C2_tfrpr (A2_vcmphgtu DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vcmpweq DoubleRegs:$src1, DoubleRegs:$src2), + (C2_tfrpr (A2_vcmpweq DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vcmpwgt DoubleRegs:$src1, DoubleRegs:$src2), + (C2_tfrpr (A2_vcmpwgt DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vcmpwgtu DoubleRegs:$src1, DoubleRegs:$src2), + (C2_tfrpr (A2_vcmpwgtu DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vconj DoubleRegs:$src1), + (A2_vconj DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vmaxb DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vmaxb DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vmaxh DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vmaxh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vmaxub DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vmaxub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vmaxuh DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vmaxuh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vmaxuw DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vmaxuw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vmaxw DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vmaxw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vminb DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vminb DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vminh DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vminh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vminub DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vminub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vminuh DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vminuh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vminuw DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vminuw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vminw DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vminw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vnavgh DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vnavgh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vnavghcr DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vnavghcr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vnavghr DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vnavghr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vnavgw DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vnavgw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vnavgwcr DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vnavgwcr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vnavgwr DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vnavgwr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vraddub DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vraddub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vraddub_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (A2_vraddub_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vrsadub DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vrsadub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vrsadub_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (A2_vrsadub_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vsubb_map DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vsubub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vsubh DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vsubh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vsubhs DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vsubhs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vsubub DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vsubub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vsububs DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vsububs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vsubuhs DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vsubuhs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vsubw DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vsubw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_vsubws DoubleRegs:$src1, DoubleRegs:$src2), + (A2_vsubws DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_xor IntRegs:$src1, IntRegs:$src2), + (A2_xor IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_xorp DoubleRegs:$src1, DoubleRegs:$src2), + (A2_xorp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_zxtb IntRegs:$src1), + (A2_zxtb IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A2_zxth IntRegs:$src1), + (A2_zxth IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_andn IntRegs:$src1, IntRegs:$src2), + (A4_andn IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_andnp DoubleRegs:$src1, DoubleRegs:$src2), + (A4_andnp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_bitsplit IntRegs:$src1, IntRegs:$src2), + (A4_bitsplit IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_bitspliti IntRegs:$src1, u5_0ImmPred_timm:$src2), + (A4_bitspliti IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_boundscheck IntRegs:$src1, DoubleRegs:$src2), + (C2_tfrpr (A4_boundscheck IntRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_cmpbeq IntRegs:$src1, IntRegs:$src2), + (C2_tfrpr (A4_cmpbeq IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_cmpbeqi IntRegs:$src1, u8_0ImmPred_timm:$src2), + (C2_tfrpr (A4_cmpbeqi IntRegs:$src1, u8_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_cmpbgt IntRegs:$src1, IntRegs:$src2), + (C2_tfrpr (A4_cmpbgt IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_cmpbgti IntRegs:$src1, s8_0ImmPred_timm:$src2), + (C2_tfrpr (A4_cmpbgti IntRegs:$src1, s8_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_cmpbgtu IntRegs:$src1, IntRegs:$src2), + (C2_tfrpr (A4_cmpbgtu IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_cmpbgtui IntRegs:$src1, u32_0ImmPred_timm:$src2), + (C2_tfrpr (A4_cmpbgtui IntRegs:$src1, u32_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_cmpheq IntRegs:$src1, IntRegs:$src2), + (C2_tfrpr (A4_cmpheq IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_cmpheqi IntRegs:$src1, s32_0ImmPred_timm:$src2), + (C2_tfrpr (A4_cmpheqi IntRegs:$src1, s32_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_cmphgt IntRegs:$src1, IntRegs:$src2), + (C2_tfrpr (A4_cmphgt IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_cmphgti IntRegs:$src1, s32_0ImmPred_timm:$src2), + (C2_tfrpr (A4_cmphgti IntRegs:$src1, s32_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_cmphgtu IntRegs:$src1, IntRegs:$src2), + (C2_tfrpr (A4_cmphgtu IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_cmphgtui IntRegs:$src1, u32_0ImmPred_timm:$src2), + (C2_tfrpr (A4_cmphgtui IntRegs:$src1, u32_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_combineir s32_0ImmPred_timm:$src1, IntRegs:$src2), + (A4_combineir s32_0ImmPred_timm:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_combineri IntRegs:$src1, s32_0ImmPred_timm:$src2), + (A4_combineri IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_cround_ri IntRegs:$src1, u5_0ImmPred_timm:$src2), + (A4_cround_ri IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_cround_rr IntRegs:$src1, IntRegs:$src2), + (A4_cround_rr IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_modwrapu IntRegs:$src1, IntRegs:$src2), + (A4_modwrapu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_orn IntRegs:$src1, IntRegs:$src2), + (A4_orn IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_ornp DoubleRegs:$src1, DoubleRegs:$src2), + (A4_ornp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_A4_rcmpeq IntRegs:$src1, IntRegs:$src2), (A4_rcmpeq IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_rcmpeqi IntRegs:$src1, s32_0ImmPred_timm:$src2), + (A4_rcmpeqi IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_A4_rcmpneq IntRegs:$src1, IntRegs:$src2), (A4_rcmpneq IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_bitsset IntRegs:$src1, IntRegs:$src2), - (C2_tfrpr (C2_bitsset IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_bitsclr IntRegs:$src1, IntRegs:$src2), - (C2_tfrpr (C2_bitsclr IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C4_nbitsset IntRegs:$src1, IntRegs:$src2), - (C2_tfrpr (C4_nbitsset IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C4_nbitsclr IntRegs:$src1, IntRegs:$src2), - (C2_tfrpr (C4_nbitsclr IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_cmpeqi IntRegs:$src1, s32_0ImmPred_timm:$src2), - (C2_tfrpr (C2_cmpeqi IntRegs:$src1, s32_0ImmPred_timm:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_cmpgti IntRegs:$src1, s32_0ImmPred_timm:$src2), - (C2_tfrpr (C2_cmpgti IntRegs:$src1, s32_0ImmPred_timm:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_cmpgtui IntRegs:$src1, u32_0ImmPred_timm:$src2), - (C2_tfrpr (C2_cmpgtui IntRegs:$src1, u32_0ImmPred_timm:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_bitsclri IntRegs:$src1, u6_0ImmPred_timm:$src2), - (C2_tfrpr (C2_bitsclri IntRegs:$src1, u6_0ImmPred_timm:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C4_nbitsclri IntRegs:$src1, u6_0ImmPred_timm:$src2), - (C2_tfrpr (C4_nbitsclri IntRegs:$src1, u6_0ImmPred_timm:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C4_cmpneqi IntRegs:$src1, s32_0ImmPred_timm:$src2), - (C2_tfrpr (C4_cmpneqi IntRegs:$src1, s32_0ImmPred_timm:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C4_cmpltei IntRegs:$src1, s32_0ImmPred_timm:$src2), - (C2_tfrpr (C4_cmpltei IntRegs:$src1, s32_0ImmPred_timm:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C4_cmplteui IntRegs:$src1, u32_0ImmPred_timm:$src2), - (C2_tfrpr (C4_cmplteui IntRegs:$src1, u32_0ImmPred_timm:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C4_cmpneq IntRegs:$src1, IntRegs:$src2), - (C2_tfrpr (C4_cmpneq IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C4_cmplte IntRegs:$src1, IntRegs:$src2), - (C2_tfrpr (C4_cmplte IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C4_cmplteu IntRegs:$src1, IntRegs:$src2), - (C2_tfrpr (C4_cmplteu IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_and PredRegs:$src1, PredRegs:$src2), - (C2_tfrpr (C2_and (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2)))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_or PredRegs:$src1, PredRegs:$src2), - (C2_tfrpr (C2_or (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2)))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_xor PredRegs:$src1, PredRegs:$src2), - (C2_tfrpr (C2_xor (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2)))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_andn PredRegs:$src1, PredRegs:$src2), - (C2_tfrpr (C2_andn (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2)))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_not PredRegs:$src1), - (C2_tfrpr (C2_not (C2_tfrrp PredRegs:$src1)))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_orn PredRegs:$src1, PredRegs:$src2), - (C2_tfrpr (C2_orn (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2)))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C4_and_and PredRegs:$src1, PredRegs:$src2, PredRegs:$src3), - (C2_tfrpr (C4_and_and (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2), (C2_tfrrp PredRegs:$src3)))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C4_and_or PredRegs:$src1, PredRegs:$src2, PredRegs:$src3), - (C2_tfrpr (C4_and_or (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2), (C2_tfrrp PredRegs:$src3)))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C4_or_and PredRegs:$src1, PredRegs:$src2, PredRegs:$src3), - (C2_tfrpr (C4_or_and (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2), (C2_tfrrp PredRegs:$src3)))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C4_or_or PredRegs:$src1, PredRegs:$src2, PredRegs:$src3), - (C2_tfrpr (C4_or_or (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2), (C2_tfrrp PredRegs:$src3)))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C4_and_andn PredRegs:$src1, PredRegs:$src2, PredRegs:$src3), - (C2_tfrpr (C4_and_andn (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2), (C2_tfrrp PredRegs:$src3)))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C4_and_orn PredRegs:$src1, PredRegs:$src2, PredRegs:$src3), - (C2_tfrpr (C4_and_orn (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2), (C2_tfrrp PredRegs:$src3)))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C4_or_andn PredRegs:$src1, PredRegs:$src2, PredRegs:$src3), - (C2_tfrpr (C4_or_andn (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2), (C2_tfrrp PredRegs:$src3)))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C4_or_orn PredRegs:$src1, PredRegs:$src2, PredRegs:$src3), - (C2_tfrpr (C4_or_orn (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2), (C2_tfrrp PredRegs:$src3)))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_pxfer_map PredRegs:$src1), - (C2_tfrpr (C2_pxfer_map (C2_tfrrp PredRegs:$src1)))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_any8 PredRegs:$src1), - (C2_tfrpr (C2_any8 (C2_tfrrp PredRegs:$src1)))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_rcmpneqi IntRegs:$src1, s32_0ImmPred_timm:$src2), + (A4_rcmpneqi IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_round_ri IntRegs:$src1, u5_0ImmPred_timm:$src2), + (A4_round_ri IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_round_ri_sat IntRegs:$src1, u5_0ImmPred_timm:$src2), + (A4_round_ri_sat IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_round_rr IntRegs:$src1, IntRegs:$src2), + (A4_round_rr IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_round_rr_sat IntRegs:$src1, IntRegs:$src2), + (A4_round_rr_sat IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_tlbmatch DoubleRegs:$src1, IntRegs:$src2), + (C2_tfrpr (A4_tlbmatch DoubleRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vcmpbeq_any DoubleRegs:$src1, DoubleRegs:$src2), + (C2_tfrpr (A4_vcmpbeq_any DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vcmpbeqi DoubleRegs:$src1, u8_0ImmPred_timm:$src2), + (C2_tfrpr (A4_vcmpbeqi DoubleRegs:$src1, u8_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vcmpbgt DoubleRegs:$src1, DoubleRegs:$src2), + (C2_tfrpr (A4_vcmpbgt DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vcmpbgti DoubleRegs:$src1, s8_0ImmPred_timm:$src2), + (C2_tfrpr (A4_vcmpbgti DoubleRegs:$src1, s8_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vcmpbgtui DoubleRegs:$src1, u7_0ImmPred_timm:$src2), + (C2_tfrpr (A4_vcmpbgtui DoubleRegs:$src1, u7_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vcmpheqi DoubleRegs:$src1, s8_0ImmPred_timm:$src2), + (C2_tfrpr (A4_vcmpheqi DoubleRegs:$src1, s8_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vcmphgti DoubleRegs:$src1, s8_0ImmPred_timm:$src2), + (C2_tfrpr (A4_vcmphgti DoubleRegs:$src1, s8_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vcmphgtui DoubleRegs:$src1, u7_0ImmPred_timm:$src2), + (C2_tfrpr (A4_vcmphgtui DoubleRegs:$src1, u7_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vcmpweqi DoubleRegs:$src1, s8_0ImmPred_timm:$src2), + (C2_tfrpr (A4_vcmpweqi DoubleRegs:$src1, s8_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vcmpwgti DoubleRegs:$src1, s8_0ImmPred_timm:$src2), + (C2_tfrpr (A4_vcmpwgti DoubleRegs:$src1, s8_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vcmpwgtui DoubleRegs:$src1, u7_0ImmPred_timm:$src2), + (C2_tfrpr (A4_vcmpwgtui DoubleRegs:$src1, u7_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vrmaxh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (A4_vrmaxh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vrmaxuh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (A4_vrmaxuh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vrmaxuw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (A4_vrmaxuw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vrmaxw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (A4_vrmaxw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vrminh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (A4_vrminh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vrminuh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (A4_vrminuh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vrminuw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (A4_vrminuw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A4_vrminw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (A4_vrminw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_A5_vaddhubs DoubleRegs:$src1, DoubleRegs:$src2), + (A5_vaddhubs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_C2_all8 PredRegs:$src1), (C2_tfrpr (C2_all8 (C2_tfrrp PredRegs:$src1)))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_vitpack PredRegs:$src1, PredRegs:$src2), - (C2_vitpack (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_and PredRegs:$src1, PredRegs:$src2), + (C2_tfrpr (C2_and (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2)))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_andn PredRegs:$src1, PredRegs:$src2), + (C2_tfrpr (C2_andn (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2)))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_any8 PredRegs:$src1), + (C2_tfrpr (C2_any8 (C2_tfrrp PredRegs:$src1)))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_bitsclr IntRegs:$src1, IntRegs:$src2), + (C2_tfrpr (C2_bitsclr IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_bitsclri IntRegs:$src1, u6_0ImmPred_timm:$src2), + (C2_tfrpr (C2_bitsclri IntRegs:$src1, u6_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_bitsset IntRegs:$src1, IntRegs:$src2), + (C2_tfrpr (C2_bitsset IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_cmpeq IntRegs:$src1, IntRegs:$src2), + (C2_tfrpr (C2_cmpeq IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_cmpeqi IntRegs:$src1, s32_0ImmPred_timm:$src2), + (C2_tfrpr (C2_cmpeqi IntRegs:$src1, s32_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_cmpeqp DoubleRegs:$src1, DoubleRegs:$src2), + (C2_tfrpr (C2_cmpeqp DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_cmpgt IntRegs:$src1, IntRegs:$src2), + (C2_tfrpr (C2_cmpgt IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_cmpgti IntRegs:$src1, s32_0ImmPred_timm:$src2), + (C2_tfrpr (C2_cmpgti IntRegs:$src1, s32_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_cmpgtp DoubleRegs:$src1, DoubleRegs:$src2), + (C2_tfrpr (C2_cmpgtp DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_cmpgtu IntRegs:$src1, IntRegs:$src2), + (C2_tfrpr (C2_cmpgtu IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_cmpgtui IntRegs:$src1, u32_0ImmPred_timm:$src2), + (C2_tfrpr (C2_cmpgtui IntRegs:$src1, u32_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_cmpgtup DoubleRegs:$src1, DoubleRegs:$src2), + (C2_tfrpr (C2_cmpgtup DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_mask PredRegs:$src1), + (C2_mask (C2_tfrrp PredRegs:$src1))>, Requires<[HasV5]>; def: Pat<(int_hexagon_C2_mux PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), (C2_mux (C2_tfrrp PredRegs:$src1), IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; def: Pat<(int_hexagon_C2_muxii PredRegs:$src1, s32_0ImmPred_timm:$src2, s8_0ImmPred_timm:$src3), @@ -105,508 +465,176 @@ def: Pat<(int_hexagon_C2_muxir PredRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm: (C2_muxir (C2_tfrrp PredRegs:$src1), IntRegs:$src2, s32_0ImmPred_timm:$src3)>, Requires<[HasV5]>; def: Pat<(int_hexagon_C2_muxri PredRegs:$src1, s32_0ImmPred_timm:$src2, IntRegs:$src3), (C2_muxri (C2_tfrrp PredRegs:$src1), s32_0ImmPred_timm:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_vmux PredRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (C2_vmux (C2_tfrrp PredRegs:$src1), DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_C2_mask PredRegs:$src1), - (C2_mask (C2_tfrrp PredRegs:$src1))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vcmpbeq DoubleRegs:$src1, DoubleRegs:$src2), - (C2_tfrpr (A2_vcmpbeq DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_vcmpbeqi DoubleRegs:$src1, u8_0ImmPred_timm:$src2), - (C2_tfrpr (A4_vcmpbeqi DoubleRegs:$src1, u8_0ImmPred_timm:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_vcmpbeq_any DoubleRegs:$src1, DoubleRegs:$src2), - (C2_tfrpr (A4_vcmpbeq_any DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vcmpbgtu DoubleRegs:$src1, DoubleRegs:$src2), - (C2_tfrpr (A2_vcmpbgtu DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_vcmpbgtui DoubleRegs:$src1, u7_0ImmPred_timm:$src2), - (C2_tfrpr (A4_vcmpbgtui DoubleRegs:$src1, u7_0ImmPred_timm:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_vcmpbgt DoubleRegs:$src1, DoubleRegs:$src2), - (C2_tfrpr (A4_vcmpbgt DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_vcmpbgti DoubleRegs:$src1, s8_0ImmPred_timm:$src2), - (C2_tfrpr (A4_vcmpbgti DoubleRegs:$src1, s8_0ImmPred_timm:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_cmpbeq IntRegs:$src1, IntRegs:$src2), - (C2_tfrpr (A4_cmpbeq IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_cmpbeqi IntRegs:$src1, u8_0ImmPred_timm:$src2), - (C2_tfrpr (A4_cmpbeqi IntRegs:$src1, u8_0ImmPred_timm:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_cmpbgtu IntRegs:$src1, IntRegs:$src2), - (C2_tfrpr (A4_cmpbgtu IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_cmpbgtui IntRegs:$src1, u32_0ImmPred_timm:$src2), - (C2_tfrpr (A4_cmpbgtui IntRegs:$src1, u32_0ImmPred_timm:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_cmpbgt IntRegs:$src1, IntRegs:$src2), - (C2_tfrpr (A4_cmpbgt IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_cmpbgti IntRegs:$src1, s8_0ImmPred_timm:$src2), - (C2_tfrpr (A4_cmpbgti IntRegs:$src1, s8_0ImmPred_timm:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vcmpheq DoubleRegs:$src1, DoubleRegs:$src2), - (C2_tfrpr (A2_vcmpheq DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vcmphgt DoubleRegs:$src1, DoubleRegs:$src2), - (C2_tfrpr (A2_vcmphgt DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vcmphgtu DoubleRegs:$src1, DoubleRegs:$src2), - (C2_tfrpr (A2_vcmphgtu DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_vcmpheqi DoubleRegs:$src1, s8_0ImmPred_timm:$src2), - (C2_tfrpr (A4_vcmpheqi DoubleRegs:$src1, s8_0ImmPred_timm:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_vcmphgti DoubleRegs:$src1, s8_0ImmPred_timm:$src2), - (C2_tfrpr (A4_vcmphgti DoubleRegs:$src1, s8_0ImmPred_timm:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_vcmphgtui DoubleRegs:$src1, u7_0ImmPred_timm:$src2), - (C2_tfrpr (A4_vcmphgtui DoubleRegs:$src1, u7_0ImmPred_timm:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_cmpheq IntRegs:$src1, IntRegs:$src2), - (C2_tfrpr (A4_cmpheq IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_cmphgt IntRegs:$src1, IntRegs:$src2), - (C2_tfrpr (A4_cmphgt IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_cmphgtu IntRegs:$src1, IntRegs:$src2), - (C2_tfrpr (A4_cmphgtu IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_cmpheqi IntRegs:$src1, s32_0ImmPred_timm:$src2), - (C2_tfrpr (A4_cmpheqi IntRegs:$src1, s32_0ImmPred_timm:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_cmphgti IntRegs:$src1, s32_0ImmPred_timm:$src2), - (C2_tfrpr (A4_cmphgti IntRegs:$src1, s32_0ImmPred_timm:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_cmphgtui IntRegs:$src1, u32_0ImmPred_timm:$src2), - (C2_tfrpr (A4_cmphgtui IntRegs:$src1, u32_0ImmPred_timm:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vcmpweq DoubleRegs:$src1, DoubleRegs:$src2), - (C2_tfrpr (A2_vcmpweq DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vcmpwgt DoubleRegs:$src1, DoubleRegs:$src2), - (C2_tfrpr (A2_vcmpwgt DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vcmpwgtu DoubleRegs:$src1, DoubleRegs:$src2), - (C2_tfrpr (A2_vcmpwgtu DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_vcmpweqi DoubleRegs:$src1, s8_0ImmPred_timm:$src2), - (C2_tfrpr (A4_vcmpweqi DoubleRegs:$src1, s8_0ImmPred_timm:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_vcmpwgti DoubleRegs:$src1, s8_0ImmPred_timm:$src2), - (C2_tfrpr (A4_vcmpwgti DoubleRegs:$src1, s8_0ImmPred_timm:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_vcmpwgtui DoubleRegs:$src1, u7_0ImmPred_timm:$src2), - (C2_tfrpr (A4_vcmpwgtui DoubleRegs:$src1, u7_0ImmPred_timm:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_boundscheck IntRegs:$src1, DoubleRegs:$src2), - (C2_tfrpr (A4_boundscheck IntRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_tlbmatch DoubleRegs:$src1, IntRegs:$src2), - (C2_tfrpr (A4_tlbmatch DoubleRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_not PredRegs:$src1), + (C2_tfrpr (C2_not (C2_tfrrp PredRegs:$src1)))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_or PredRegs:$src1, PredRegs:$src2), + (C2_tfrpr (C2_or (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2)))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_orn PredRegs:$src1, PredRegs:$src2), + (C2_tfrpr (C2_orn (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2)))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_pxfer_map PredRegs:$src1), + (C2_tfrpr (C2_pxfer_map (C2_tfrrp PredRegs:$src1)))>, Requires<[HasV5]>; def: Pat<(int_hexagon_C2_tfrpr PredRegs:$src1), (C2_tfrpr (C2_tfrrp PredRegs:$src1))>, Requires<[HasV5]>; def: Pat<(int_hexagon_C2_tfrrp IntRegs:$src1), (C2_tfrpr (C2_tfrrp IntRegs:$src1))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_vitpack PredRegs:$src1, PredRegs:$src2), + (C2_vitpack (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_vmux PredRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (C2_vmux (C2_tfrrp PredRegs:$src1), DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C2_xor PredRegs:$src1, PredRegs:$src2), + (C2_tfrpr (C2_xor (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2)))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_and_and PredRegs:$src1, PredRegs:$src2, PredRegs:$src3), + (C2_tfrpr (C4_and_and (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2), (C2_tfrrp PredRegs:$src3)))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_and_andn PredRegs:$src1, PredRegs:$src2, PredRegs:$src3), + (C2_tfrpr (C4_and_andn (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2), (C2_tfrrp PredRegs:$src3)))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_and_or PredRegs:$src1, PredRegs:$src2, PredRegs:$src3), + (C2_tfrpr (C4_and_or (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2), (C2_tfrrp PredRegs:$src3)))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_and_orn PredRegs:$src1, PredRegs:$src2, PredRegs:$src3), + (C2_tfrpr (C4_and_orn (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2), (C2_tfrrp PredRegs:$src3)))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_cmplte IntRegs:$src1, IntRegs:$src2), + (C2_tfrpr (C4_cmplte IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_cmpltei IntRegs:$src1, s32_0ImmPred_timm:$src2), + (C2_tfrpr (C4_cmpltei IntRegs:$src1, s32_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_cmplteu IntRegs:$src1, IntRegs:$src2), + (C2_tfrpr (C4_cmplteu IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_cmplteui IntRegs:$src1, u32_0ImmPred_timm:$src2), + (C2_tfrpr (C4_cmplteui IntRegs:$src1, u32_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_cmpneq IntRegs:$src1, IntRegs:$src2), + (C2_tfrpr (C4_cmpneq IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_cmpneqi IntRegs:$src1, s32_0ImmPred_timm:$src2), + (C2_tfrpr (C4_cmpneqi IntRegs:$src1, s32_0ImmPred_timm:$src2))>, Requires<[HasV5]>; def: Pat<(int_hexagon_C4_fastcorner9 PredRegs:$src1, PredRegs:$src2), (C2_tfrpr (C4_fastcorner9 (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2)))>, Requires<[HasV5]>; def: Pat<(int_hexagon_C4_fastcorner9_not PredRegs:$src1, PredRegs:$src2), (C2_tfrpr (C4_fastcorner9_not (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2)))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_acc_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_acc_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_acc_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_acc_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_acc_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_acc_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_acc_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_acc_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_acc_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_acc_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_acc_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_acc_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_acc_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_acc_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_acc_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_acc_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_nac_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_nac_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_nac_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_nac_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_nac_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_nac_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_nac_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_nac_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_nac_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_nac_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_nac_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_nac_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_nac_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_nac_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_nac_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_nac_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_acc_sat_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_acc_sat_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_acc_sat_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_acc_sat_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_acc_sat_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_acc_sat_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_acc_sat_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_acc_sat_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_acc_sat_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_acc_sat_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_acc_sat_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_acc_sat_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_acc_sat_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_acc_sat_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_acc_sat_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_acc_sat_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_nac_sat_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_nac_sat_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_nac_sat_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_nac_sat_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_nac_sat_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_nac_sat_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_nac_sat_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_nac_sat_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_nac_sat_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_nac_sat_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_nac_sat_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_nac_sat_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_nac_sat_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_nac_sat_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_nac_sat_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpy_nac_sat_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_hh_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_hh_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_hl_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_hl_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_lh_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_lh_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_ll_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_ll_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_sat_hh_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_sat_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_sat_hh_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_sat_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_sat_hl_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_sat_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_sat_hl_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_sat_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_sat_lh_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_sat_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_sat_lh_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_sat_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_sat_ll_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_sat_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_sat_ll_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_sat_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_rnd_hh_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_rnd_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_rnd_hh_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_rnd_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_rnd_hl_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_rnd_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_rnd_hl_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_rnd_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_rnd_ll_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_rnd_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_rnd_ll_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_rnd_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_sat_rnd_hh_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_sat_rnd_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_sat_rnd_hh_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_sat_rnd_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_sat_rnd_hl_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_sat_rnd_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_sat_rnd_hl_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_sat_rnd_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_sat_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_sat_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_sat_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_sat_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_sat_rnd_ll_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_sat_rnd_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_sat_rnd_ll_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_sat_rnd_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_acc_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyd_acc_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_acc_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyd_acc_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_acc_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyd_acc_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_acc_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyd_acc_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_acc_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyd_acc_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_acc_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyd_acc_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_acc_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyd_acc_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_acc_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyd_acc_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_nac_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyd_nac_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_nac_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyd_nac_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_nac_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyd_nac_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_nac_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyd_nac_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_nac_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyd_nac_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_nac_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyd_nac_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_nac_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyd_nac_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_nac_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyd_nac_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_hh_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpyd_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_hh_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpyd_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_hl_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpyd_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_hl_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpyd_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_lh_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpyd_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_lh_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpyd_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_ll_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpyd_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_ll_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpyd_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_rnd_hh_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpyd_rnd_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_rnd_hh_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpyd_rnd_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_rnd_hl_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpyd_rnd_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_rnd_hl_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpyd_rnd_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpyd_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpyd_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_rnd_ll_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpyd_rnd_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyd_rnd_ll_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpyd_rnd_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_acc_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyu_acc_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_acc_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyu_acc_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_acc_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyu_acc_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_acc_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyu_acc_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_acc_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyu_acc_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_acc_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyu_acc_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_acc_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyu_acc_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_acc_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyu_acc_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_nac_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyu_nac_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_nac_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyu_nac_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_nac_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyu_nac_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_nac_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyu_nac_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_nac_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyu_nac_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_nac_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyu_nac_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_nac_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyu_nac_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_nac_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyu_nac_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_hh_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpyu_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_hh_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpyu_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_hl_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpyu_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_hl_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpyu_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_lh_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpyu_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_lh_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpyu_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_ll_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpyu_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_ll_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpyu_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_acc_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyud_acc_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_acc_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyud_acc_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_acc_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyud_acc_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_acc_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyud_acc_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_acc_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyud_acc_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_acc_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyud_acc_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_acc_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyud_acc_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_acc_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyud_acc_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_nac_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyud_nac_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_nac_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyud_nac_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_nac_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyud_nac_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_nac_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyud_nac_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_nac_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyud_nac_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_nac_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyud_nac_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_nac_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyud_nac_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_nac_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mpyud_nac_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_hh_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpyud_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_hh_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpyud_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_hl_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpyud_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_hl_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpyud_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_lh_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpyud_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_lh_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpyud_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_ll_s0 IntRegs:$src1, IntRegs:$src2), - (M2_mpyud_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyud_ll_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpyud_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpysmi IntRegs:$src1, m32_0ImmPred_timm:$src2), - (M2_mpysmi IntRegs:$src1, m32_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_macsip IntRegs:$src1, IntRegs:$src2, u32_0ImmPred_timm:$src3), - (M2_macsip IntRegs:$src1, IntRegs:$src2, u32_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_macsin IntRegs:$src1, IntRegs:$src2, u32_0ImmPred_timm:$src3), - (M2_macsin IntRegs:$src1, IntRegs:$src2, u32_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_dpmpyss_s0 IntRegs:$src1, IntRegs:$src2), - (M2_dpmpyss_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_dpmpyss_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_dpmpyss_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_dpmpyss_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_dpmpyss_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_dpmpyuu_s0 IntRegs:$src1, IntRegs:$src2), - (M2_dpmpyuu_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_up IntRegs:$src1, IntRegs:$src2), - (M2_mpy_up IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_up_s1 IntRegs:$src1, IntRegs:$src2), - (M2_mpy_up_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpy_up_s1_sat IntRegs:$src1, IntRegs:$src2), - (M2_mpy_up_s1_sat IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyu_up IntRegs:$src1, IntRegs:$src2), - (M2_mpyu_up IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpysu_up IntRegs:$src1, IntRegs:$src2), - (M2_mpysu_up IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_dpmpyss_rnd_s0 IntRegs:$src1, IntRegs:$src2), - (M2_dpmpyss_rnd_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_mac_up_s1_sat IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M4_mac_up_s1_sat IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_nac_up_s1_sat IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M4_nac_up_s1_sat IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyi IntRegs:$src1, IntRegs:$src2), - (M2_mpyi IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mpyui IntRegs:$src1, IntRegs:$src2), - (M2_mpyui IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_maci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_maci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_nbitsclr IntRegs:$src1, IntRegs:$src2), + (C2_tfrpr (C4_nbitsclr IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_nbitsclri IntRegs:$src1, u6_0ImmPred_timm:$src2), + (C2_tfrpr (C4_nbitsclri IntRegs:$src1, u6_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_nbitsset IntRegs:$src1, IntRegs:$src2), + (C2_tfrpr (C4_nbitsset IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_or_and PredRegs:$src1, PredRegs:$src2, PredRegs:$src3), + (C2_tfrpr (C4_or_and (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2), (C2_tfrrp PredRegs:$src3)))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_or_andn PredRegs:$src1, PredRegs:$src2, PredRegs:$src3), + (C2_tfrpr (C4_or_andn (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2), (C2_tfrrp PredRegs:$src3)))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_or_or PredRegs:$src1, PredRegs:$src2, PredRegs:$src3), + (C2_tfrpr (C4_or_or (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2), (C2_tfrrp PredRegs:$src3)))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_C4_or_orn PredRegs:$src1, PredRegs:$src2, PredRegs:$src3), + (C2_tfrpr (C4_or_orn (C2_tfrrp PredRegs:$src1), (C2_tfrrp PredRegs:$src2), (C2_tfrrp PredRegs:$src3)))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_d2df DoubleRegs:$src1), + (F2_conv_d2df DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_d2sf DoubleRegs:$src1), + (F2_conv_d2sf DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_df2d DoubleRegs:$src1), + (F2_conv_df2d DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_df2d_chop DoubleRegs:$src1), + (F2_conv_df2d_chop DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_df2sf DoubleRegs:$src1), + (F2_conv_df2sf DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_df2ud DoubleRegs:$src1), + (F2_conv_df2ud DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_df2ud_chop DoubleRegs:$src1), + (F2_conv_df2ud_chop DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_df2uw DoubleRegs:$src1), + (F2_conv_df2uw DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_df2uw_chop DoubleRegs:$src1), + (F2_conv_df2uw_chop DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_df2w DoubleRegs:$src1), + (F2_conv_df2w DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_df2w_chop DoubleRegs:$src1), + (F2_conv_df2w_chop DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_sf2d IntRegs:$src1), + (F2_conv_sf2d IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_sf2d_chop IntRegs:$src1), + (F2_conv_sf2d_chop IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_sf2df IntRegs:$src1), + (F2_conv_sf2df IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_sf2ud IntRegs:$src1), + (F2_conv_sf2ud IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_sf2ud_chop IntRegs:$src1), + (F2_conv_sf2ud_chop IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_sf2uw IntRegs:$src1), + (F2_conv_sf2uw IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_sf2uw_chop IntRegs:$src1), + (F2_conv_sf2uw_chop IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_sf2w IntRegs:$src1), + (F2_conv_sf2w IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_sf2w_chop IntRegs:$src1), + (F2_conv_sf2w_chop IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_ud2df DoubleRegs:$src1), + (F2_conv_ud2df DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_ud2sf DoubleRegs:$src1), + (F2_conv_ud2sf DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_uw2df IntRegs:$src1), + (F2_conv_uw2df IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_uw2sf IntRegs:$src1), + (F2_conv_uw2sf IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_w2df IntRegs:$src1), + (F2_conv_w2df IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_conv_w2sf IntRegs:$src1), + (F2_conv_w2sf IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_dfclass DoubleRegs:$src1, u5_0ImmPred_timm:$src2), + (C2_tfrpr (F2_dfclass DoubleRegs:$src1, u5_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_dfcmpeq DoubleRegs:$src1, DoubleRegs:$src2), + (C2_tfrpr (F2_dfcmpeq DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_dfcmpge DoubleRegs:$src1, DoubleRegs:$src2), + (C2_tfrpr (F2_dfcmpge DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_dfcmpgt DoubleRegs:$src1, DoubleRegs:$src2), + (C2_tfrpr (F2_dfcmpgt DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_dfcmpuo DoubleRegs:$src1, DoubleRegs:$src2), + (C2_tfrpr (F2_dfcmpuo DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_dfimm_n u10_0ImmPred_timm:$src1), + (F2_dfimm_n u10_0ImmPred_timm:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_dfimm_p u10_0ImmPred_timm:$src1), + (F2_dfimm_p u10_0ImmPred_timm:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sfadd IntRegs:$src1, IntRegs:$src2), + (F2_sfadd IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sfclass IntRegs:$src1, u5_0ImmPred_timm:$src2), + (C2_tfrpr (F2_sfclass IntRegs:$src1, u5_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sfcmpeq IntRegs:$src1, IntRegs:$src2), + (C2_tfrpr (F2_sfcmpeq IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sfcmpge IntRegs:$src1, IntRegs:$src2), + (C2_tfrpr (F2_sfcmpge IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sfcmpgt IntRegs:$src1, IntRegs:$src2), + (C2_tfrpr (F2_sfcmpgt IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sfcmpuo IntRegs:$src1, IntRegs:$src2), + (C2_tfrpr (F2_sfcmpuo IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sffixupd IntRegs:$src1, IntRegs:$src2), + (F2_sffixupd IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sffixupn IntRegs:$src1, IntRegs:$src2), + (F2_sffixupn IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sffixupr IntRegs:$src1), + (F2_sffixupr IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sffma IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (F2_sffma IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sffma_lib IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (F2_sffma_lib IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sffma_sc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3, PredRegs:$src4), + (F2_sffma_sc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3, (C2_tfrrp PredRegs:$src4))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sffms IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (F2_sffms IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sffms_lib IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (F2_sffms_lib IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sfimm_n u10_0ImmPred_timm:$src1), + (F2_sfimm_n u10_0ImmPred_timm:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sfimm_p u10_0ImmPred_timm:$src1), + (F2_sfimm_p u10_0ImmPred_timm:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sfmax IntRegs:$src1, IntRegs:$src2), + (F2_sfmax IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sfmin IntRegs:$src1, IntRegs:$src2), + (F2_sfmin IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sfmpy IntRegs:$src1, IntRegs:$src2), + (F2_sfmpy IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_F2_sfsub IntRegs:$src1, IntRegs:$src2), + (F2_sfsub IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M2_acci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), (M2_acci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M2_accii IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3), (M2_accii IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_nacci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_nacci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_naccii IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3), - (M2_naccii IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_subacc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_subacc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_mpyrr_addr IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M4_mpyrr_addr IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[UseCompound, HasV5]>; -def: Pat<(int_hexagon_M4_mpyri_addr_u2 IntRegs:$src1, u6_2ImmPred_timm:$src2, IntRegs:$src3), - (M4_mpyri_addr_u2 IntRegs:$src1, u6_2ImmPred_timm:$src2, IntRegs:$src3)>, Requires<[UseCompound, HasV5]>; -def: Pat<(int_hexagon_M4_mpyri_addr IntRegs:$src1, IntRegs:$src2, u32_0ImmPred_timm:$src3), - (M4_mpyri_addr IntRegs:$src1, IntRegs:$src2, u32_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>; -def: Pat<(int_hexagon_M4_mpyri_addi u32_0ImmPred_timm:$src1, IntRegs:$src2, u6_0ImmPred_timm:$src3), - (M4_mpyri_addi u32_0ImmPred_timm:$src1, IntRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>; -def: Pat<(int_hexagon_M4_mpyrr_addi u32_0ImmPred_timm:$src1, IntRegs:$src2, IntRegs:$src3), - (M4_mpyrr_addi u32_0ImmPred_timm:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[UseCompound, HasV5]>; -def: Pat<(int_hexagon_M2_vmpy2s_s0 IntRegs:$src1, IntRegs:$src2), - (M2_vmpy2s_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vmpy2s_s1 IntRegs:$src1, IntRegs:$src2), - (M2_vmpy2s_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vmac2s_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_vmac2s_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vmac2s_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_vmac2s_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vmpy2su_s0 IntRegs:$src1, IntRegs:$src2), - (M2_vmpy2su_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vmpy2su_s1 IntRegs:$src1, IntRegs:$src2), - (M2_vmpy2su_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vmac2su_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_vmac2su_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vmac2su_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_vmac2su_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vmpy2s_s0pack IntRegs:$src1, IntRegs:$src2), - (M2_vmpy2s_s0pack IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vmpy2s_s1pack IntRegs:$src1, IntRegs:$src2), - (M2_vmpy2s_s1pack IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vmac2 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_vmac2 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vmpy2es_s0 DoubleRegs:$src1, DoubleRegs:$src2), - (M2_vmpy2es_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vmpy2es_s1 DoubleRegs:$src1, DoubleRegs:$src2), - (M2_vmpy2es_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vmac2es_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_vmac2es_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vmac2es_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_vmac2es_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vmac2es DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_vmac2es DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vrmac_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_vrmac_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vrmpy_s0 DoubleRegs:$src1, DoubleRegs:$src2), - (M2_vrmpy_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vdmpyrs_s0 DoubleRegs:$src1, DoubleRegs:$src2), - (M2_vdmpyrs_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vdmpyrs_s1 DoubleRegs:$src1, DoubleRegs:$src2), - (M2_vdmpyrs_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M5_vrmpybuu DoubleRegs:$src1, DoubleRegs:$src2), - (M5_vrmpybuu DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M5_vrmacbuu DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M5_vrmacbuu DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M5_vrmpybsu DoubleRegs:$src1, DoubleRegs:$src2), - (M5_vrmpybsu DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M5_vrmacbsu DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M5_vrmacbsu DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M5_vmpybuu IntRegs:$src1, IntRegs:$src2), - (M5_vmpybuu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M5_vmpybsu IntRegs:$src1, IntRegs:$src2), - (M5_vmpybsu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M5_vmacbuu DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M5_vmacbuu DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M5_vmacbsu DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M5_vmacbsu DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M5_vdmpybsu DoubleRegs:$src1, DoubleRegs:$src2), - (M5_vdmpybsu DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M5_vdmacbsu DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M5_vdmacbsu DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vdmacs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_vdmacs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vdmacs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_vdmacs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vdmpys_s0 DoubleRegs:$src1, DoubleRegs:$src2), - (M2_vdmpys_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vdmpys_s1 DoubleRegs:$src1, DoubleRegs:$src2), - (M2_vdmpys_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_cmpyrs_s0 IntRegs:$src1, IntRegs:$src2), - (M2_cmpyrs_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_cmpyrs_s1 IntRegs:$src1, IntRegs:$src2), - (M2_cmpyrs_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_cmpyrsc_s0 IntRegs:$src1, IntRegs:$src2), - (M2_cmpyrsc_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_cmpyrsc_s1 IntRegs:$src1, IntRegs:$src2), - (M2_cmpyrsc_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cmaci_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_cmaci_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cmacr_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_cmacr_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M2_cmacs_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), (M2_cmacs_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M2_cmacs_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), @@ -615,6 +643,18 @@ def: Pat<(int_hexagon_M2_cmacsc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src (M2_cmacsc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M2_cmacsc_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), (M2_cmacsc_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cmpyi_s0 IntRegs:$src1, IntRegs:$src2), + (M2_cmpyi_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cmpyr_s0 IntRegs:$src1, IntRegs:$src2), + (M2_cmpyr_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cmpyrs_s0 IntRegs:$src1, IntRegs:$src2), + (M2_cmpyrs_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cmpyrs_s1 IntRegs:$src1, IntRegs:$src2), + (M2_cmpyrs_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cmpyrsc_s0 IntRegs:$src1, IntRegs:$src2), + (M2_cmpyrsc_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_cmpyrsc_s1 IntRegs:$src1, IntRegs:$src2), + (M2_cmpyrsc_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M2_cmpys_s0 IntRegs:$src1, IntRegs:$src2), (M2_cmpys_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M2_cmpys_s1 IntRegs:$src1, IntRegs:$src2), @@ -631,132 +671,416 @@ def: Pat<(int_hexagon_M2_cnacsc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src (M2_cnacsc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M2_cnacsc_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), (M2_cnacsc_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vrcmpys_s1 DoubleRegs:$src1, IntRegs:$src2), - (M2_vrcmpys_s1 DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vrcmpys_acc_s1 DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (M2_vrcmpys_acc_s1 DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vrcmpys_s1rp DoubleRegs:$src1, IntRegs:$src2), - (M2_vrcmpys_s1rp DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmacls_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_mmacls_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmacls_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_mmacls_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmachs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_mmachs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmachs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_mmachs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmpyl_s0 DoubleRegs:$src1, DoubleRegs:$src2), - (M2_mmpyl_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmpyl_s1 DoubleRegs:$src1, DoubleRegs:$src2), - (M2_mmpyl_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmpyh_s0 DoubleRegs:$src1, DoubleRegs:$src2), - (M2_mmpyh_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmpyh_s1 DoubleRegs:$src1, DoubleRegs:$src2), - (M2_mmpyh_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmacls_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_mmacls_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmacls_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_mmacls_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_dpmpyss_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_dpmpyss_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_dpmpyss_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_dpmpyss_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_dpmpyss_rnd_s0 IntRegs:$src1, IntRegs:$src2), + (M2_dpmpyss_rnd_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_dpmpyss_s0 IntRegs:$src1, IntRegs:$src2), + (M2_dpmpyss_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_dpmpyuu_acc_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_dpmpyuu_nac_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_dpmpyuu_s0 IntRegs:$src1, IntRegs:$src2), + (M2_dpmpyuu_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_hmmpyh_rs1 IntRegs:$src1, IntRegs:$src2), + (M2_hmmpyh_rs1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_hmmpyh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_hmmpyh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_hmmpyl_rs1 IntRegs:$src1, IntRegs:$src2), + (M2_hmmpyl_rs1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_hmmpyl_s1 IntRegs:$src1, IntRegs:$src2), + (M2_hmmpyl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_maci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_maci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_macsin IntRegs:$src1, IntRegs:$src2, u32_0ImmPred_timm:$src3), + (M2_macsin IntRegs:$src1, IntRegs:$src2, u32_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_macsip IntRegs:$src1, IntRegs:$src2, u32_0ImmPred_timm:$src3), + (M2_macsip IntRegs:$src1, IntRegs:$src2, u32_0ImmPred_timm:$src3)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M2_mmachs_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), (M2_mmachs_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M2_mmachs_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), (M2_mmachs_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmpyl_rs0 DoubleRegs:$src1, DoubleRegs:$src2), - (M2_mmpyl_rs0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmpyl_rs1 DoubleRegs:$src1, DoubleRegs:$src2), - (M2_mmpyl_rs1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmpyh_rs0 DoubleRegs:$src1, DoubleRegs:$src2), - (M2_mmpyh_rs0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmpyh_rs1 DoubleRegs:$src1, DoubleRegs:$src2), - (M2_mmpyh_rs1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_vrmpyeh_s0 DoubleRegs:$src1, DoubleRegs:$src2), - (M4_vrmpyeh_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_vrmpyeh_s1 DoubleRegs:$src1, DoubleRegs:$src2), - (M4_vrmpyeh_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_vrmpyeh_acc_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M4_vrmpyeh_acc_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_vrmpyeh_acc_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M4_vrmpyeh_acc_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_vrmpyoh_s0 DoubleRegs:$src1, DoubleRegs:$src2), - (M4_vrmpyoh_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_vrmpyoh_s1 DoubleRegs:$src1, DoubleRegs:$src2), - (M4_vrmpyoh_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_vrmpyoh_acc_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M4_vrmpyoh_acc_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_vrmpyoh_acc_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M4_vrmpyoh_acc_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_hmmpyl_rs1 IntRegs:$src1, IntRegs:$src2), - (M2_hmmpyl_rs1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_hmmpyh_rs1 IntRegs:$src1, IntRegs:$src2), - (M2_hmmpyh_rs1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_hmmpyl_s1 IntRegs:$src1, IntRegs:$src2), - (M2_hmmpyl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_hmmpyh_s1 IntRegs:$src1, IntRegs:$src2), - (M2_hmmpyh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmaculs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_mmaculs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmaculs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_mmaculs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmacuhs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_mmacuhs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmacuhs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_mmacuhs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmpyul_s0 DoubleRegs:$src1, DoubleRegs:$src2), - (M2_mmpyul_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmpyul_s1 DoubleRegs:$src1, DoubleRegs:$src2), - (M2_mmpyul_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmpyuh_s0 DoubleRegs:$src1, DoubleRegs:$src2), - (M2_mmpyuh_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmpyuh_s1 DoubleRegs:$src1, DoubleRegs:$src2), - (M2_mmpyuh_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmaculs_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_mmaculs_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmaculs_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_mmaculs_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmachs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_mmachs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmachs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_mmachs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmacls_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_mmacls_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmacls_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_mmacls_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmacls_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_mmacls_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmacls_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_mmacls_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M2_mmacuhs_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), (M2_mmacuhs_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M2_mmacuhs_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), (M2_mmacuhs_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmpyul_rs0 DoubleRegs:$src1, DoubleRegs:$src2), - (M2_mmpyul_rs0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_mmpyul_rs1 DoubleRegs:$src1, DoubleRegs:$src2), - (M2_mmpyul_rs1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmacuhs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_mmacuhs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmacuhs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_mmacuhs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmaculs_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_mmaculs_rs0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmaculs_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_mmaculs_rs1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmaculs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_mmaculs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmaculs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_mmaculs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmpyh_rs0 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_mmpyh_rs0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmpyh_rs1 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_mmpyh_rs1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmpyh_s0 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_mmpyh_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmpyh_s1 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_mmpyh_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmpyl_rs0 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_mmpyl_rs0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmpyl_rs1 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_mmpyl_rs1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmpyl_s0 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_mmpyl_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmpyl_s1 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_mmpyl_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M2_mmpyuh_rs0 DoubleRegs:$src1, DoubleRegs:$src2), (M2_mmpyuh_rs0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M2_mmpyuh_rs1 DoubleRegs:$src1, DoubleRegs:$src2), (M2_mmpyuh_rs1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vrcmaci_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_vrcmaci_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vrcmacr_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_vrcmacr_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vrcmaci_s0c DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_vrcmaci_s0c DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vrcmacr_s0c DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_vrcmacr_s0c DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_cmaci_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_cmaci_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_cmacr_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_cmacr_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vrcmpyi_s0 DoubleRegs:$src1, DoubleRegs:$src2), - (M2_vrcmpyi_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vrcmpyr_s0 DoubleRegs:$src1, DoubleRegs:$src2), - (M2_vrcmpyr_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vrcmpyi_s0c DoubleRegs:$src1, DoubleRegs:$src2), - (M2_vrcmpyi_s0c DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vrcmpyr_s0c DoubleRegs:$src1, DoubleRegs:$src2), - (M2_vrcmpyr_s0c DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_cmpyi_s0 IntRegs:$src1, IntRegs:$src2), - (M2_cmpyi_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_cmpyr_s0 IntRegs:$src1, IntRegs:$src2), - (M2_cmpyr_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_cmpyi_wh DoubleRegs:$src1, IntRegs:$src2), - (M4_cmpyi_wh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_cmpyr_wh DoubleRegs:$src1, IntRegs:$src2), - (M4_cmpyr_wh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_cmpyi_whc DoubleRegs:$src1, IntRegs:$src2), - (M4_cmpyi_whc DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_cmpyr_whc DoubleRegs:$src1, IntRegs:$src2), - (M4_cmpyr_whc DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmpyuh_s0 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_mmpyuh_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmpyuh_s1 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_mmpyuh_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmpyul_rs0 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_mmpyul_rs0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmpyul_rs1 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_mmpyul_rs1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmpyul_s0 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_mmpyul_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mmpyul_s1 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_mmpyul_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_sat_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_sat_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_sat_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_sat_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_sat_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_sat_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_sat_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_sat_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_sat_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_sat_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_sat_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_sat_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_sat_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_sat_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_acc_sat_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_acc_sat_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_hh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_hh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_hl_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_hl_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_lh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_lh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_ll_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_ll_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_sat_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_sat_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_sat_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_sat_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_sat_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_sat_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_sat_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_sat_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_sat_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_sat_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_sat_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_sat_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_sat_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_sat_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_nac_sat_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpy_nac_sat_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_rnd_hh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_rnd_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_rnd_hh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_rnd_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_rnd_hl_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_rnd_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_rnd_hl_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_rnd_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_rnd_ll_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_rnd_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_rnd_ll_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_rnd_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_sat_hh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_sat_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_sat_hh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_sat_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_sat_hl_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_sat_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_sat_hl_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_sat_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_sat_lh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_sat_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_sat_lh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_sat_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_sat_ll_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_sat_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_sat_ll_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_sat_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_sat_rnd_hh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_sat_rnd_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_sat_rnd_hh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_sat_rnd_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_sat_rnd_hl_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_sat_rnd_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_sat_rnd_hl_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_sat_rnd_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_sat_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_sat_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_sat_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_sat_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_sat_rnd_ll_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_sat_rnd_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_sat_rnd_ll_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_sat_rnd_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_up IntRegs:$src1, IntRegs:$src2), + (M2_mpy_up IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_up_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpy_up_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpy_up_s1_sat IntRegs:$src1, IntRegs:$src2), + (M2_mpy_up_s1_sat IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_acc_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_acc_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_acc_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_acc_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_acc_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_acc_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_acc_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_acc_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_acc_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_acc_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_acc_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_acc_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_acc_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_acc_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_acc_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_acc_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_hh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_hh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_hl_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_hl_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_lh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_lh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_ll_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_ll_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_nac_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_nac_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_nac_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_nac_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_nac_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_nac_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_nac_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_nac_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_nac_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_nac_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_nac_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_nac_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_nac_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_nac_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_nac_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyd_nac_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_rnd_hh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_rnd_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_rnd_hh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_rnd_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_rnd_hl_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_rnd_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_rnd_hl_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_rnd_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_rnd_ll_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_rnd_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyd_rnd_ll_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyd_rnd_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyi IntRegs:$src1, IntRegs:$src2), + (M2_mpyi IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpysmi IntRegs:$src1, m32_0ImmPred_timm:$src2), + (M2_mpysmi IntRegs:$src1, m32_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpysu_up IntRegs:$src1, IntRegs:$src2), + (M2_mpysu_up IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_acc_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_acc_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_acc_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_acc_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_acc_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_acc_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_acc_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_acc_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_acc_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_acc_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_acc_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_acc_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_acc_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_acc_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_acc_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_acc_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_hh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyu_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_hh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyu_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_hl_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyu_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_hl_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyu_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_lh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyu_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_lh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyu_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_ll_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyu_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_ll_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyu_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_nac_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_nac_hh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_nac_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_nac_hh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_nac_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_nac_hl_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_nac_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_nac_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_nac_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_nac_lh_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_nac_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_nac_lh_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_nac_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_nac_ll_s0 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_nac_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyu_nac_ll_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyu_up IntRegs:$src1, IntRegs:$src2), + (M2_mpyu_up IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_acc_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_acc_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_acc_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_acc_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_acc_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_acc_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_acc_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_acc_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_acc_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_acc_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_acc_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_acc_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_acc_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_acc_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_acc_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_acc_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_hh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyud_hh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_hh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyud_hh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_hl_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyud_hl_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_hl_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyud_hl_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_lh_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyud_lh_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_lh_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyud_lh_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_ll_s0 IntRegs:$src1, IntRegs:$src2), + (M2_mpyud_ll_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_ll_s1 IntRegs:$src1, IntRegs:$src2), + (M2_mpyud_ll_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_nac_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_nac_hh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_nac_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_nac_hh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_nac_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_nac_hl_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_nac_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_nac_hl_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_nac_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_nac_lh_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_nac_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_nac_lh_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_nac_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_nac_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyud_nac_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mpyud_nac_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_mpyui IntRegs:$src1, IntRegs:$src2), + (M2_mpyui IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_nacci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_nacci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_naccii IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3), + (M2_naccii IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_subacc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_subacc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vabsdiffh DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vabsdiffh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vabsdiffw DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vabsdiffw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vcmac_s0_sat_i DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_vcmac_s0_sat_i DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vcmac_s0_sat_r DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_vcmac_s0_sat_r DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M2_vcmpy_s0_sat_i DoubleRegs:$src1, DoubleRegs:$src2), (M2_vcmpy_s0_sat_i DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M2_vcmpy_s0_sat_r DoubleRegs:$src1, DoubleRegs:$src2), @@ -765,182 +1089,82 @@ def: Pat<(int_hexagon_M2_vcmpy_s1_sat_i DoubleRegs:$src1, DoubleRegs:$src2), (M2_vcmpy_s1_sat_i DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M2_vcmpy_s1_sat_r DoubleRegs:$src1, DoubleRegs:$src2), (M2_vcmpy_s1_sat_r DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vcmac_s0_sat_i DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_vcmac_s0_sat_i DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vcmac_s0_sat_r DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M2_vcmac_s0_sat_r DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vcrotate DoubleRegs:$src1, IntRegs:$src2), - (S2_vcrotate DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_vrcrotate_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3, u2_0ImmPred_timm:$src4), - (S4_vrcrotate_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3, u2_0ImmPred_timm:$src4)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2, u2_0ImmPred_timm:$src3), - (S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2, u2_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vcnegh DoubleRegs:$src1, IntRegs:$src2), - (S2_vcnegh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vrcnegh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (S2_vrcnegh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_pmpyw IntRegs:$src1, IntRegs:$src2), - (M4_pmpyw IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_vpmpyh IntRegs:$src1, IntRegs:$src2), - (M4_vpmpyh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_pmpyw_acc DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M4_pmpyw_acc DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_vpmpyh_acc DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M4_vpmpyh_acc DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_add IntRegs:$src1, IntRegs:$src2), - (A2_add IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_sub IntRegs:$src1, IntRegs:$src2), - (A2_sub IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_addsat IntRegs:$src1, IntRegs:$src2), - (A2_addsat IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_subsat IntRegs:$src1, IntRegs:$src2), - (A2_subsat IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_addi IntRegs:$src1, s32_0ImmPred_timm:$src2), - (A2_addi IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_addh_l16_ll IntRegs:$src1, IntRegs:$src2), - (A2_addh_l16_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_addh_l16_hl IntRegs:$src1, IntRegs:$src2), - (A2_addh_l16_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_addh_l16_sat_ll IntRegs:$src1, IntRegs:$src2), - (A2_addh_l16_sat_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_addh_l16_sat_hl IntRegs:$src1, IntRegs:$src2), - (A2_addh_l16_sat_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_subh_l16_ll IntRegs:$src1, IntRegs:$src2), - (A2_subh_l16_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_subh_l16_hl IntRegs:$src1, IntRegs:$src2), - (A2_subh_l16_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_subh_l16_sat_ll IntRegs:$src1, IntRegs:$src2), - (A2_subh_l16_sat_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_subh_l16_sat_hl IntRegs:$src1, IntRegs:$src2), - (A2_subh_l16_sat_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_addh_h16_ll IntRegs:$src1, IntRegs:$src2), - (A2_addh_h16_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_addh_h16_lh IntRegs:$src1, IntRegs:$src2), - (A2_addh_h16_lh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_addh_h16_hl IntRegs:$src1, IntRegs:$src2), - (A2_addh_h16_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_addh_h16_hh IntRegs:$src1, IntRegs:$src2), - (A2_addh_h16_hh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_addh_h16_sat_ll IntRegs:$src1, IntRegs:$src2), - (A2_addh_h16_sat_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_addh_h16_sat_lh IntRegs:$src1, IntRegs:$src2), - (A2_addh_h16_sat_lh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_addh_h16_sat_hl IntRegs:$src1, IntRegs:$src2), - (A2_addh_h16_sat_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_addh_h16_sat_hh IntRegs:$src1, IntRegs:$src2), - (A2_addh_h16_sat_hh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_subh_h16_ll IntRegs:$src1, IntRegs:$src2), - (A2_subh_h16_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_subh_h16_lh IntRegs:$src1, IntRegs:$src2), - (A2_subh_h16_lh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_subh_h16_hl IntRegs:$src1, IntRegs:$src2), - (A2_subh_h16_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_subh_h16_hh IntRegs:$src1, IntRegs:$src2), - (A2_subh_h16_hh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_subh_h16_sat_ll IntRegs:$src1, IntRegs:$src2), - (A2_subh_h16_sat_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_subh_h16_sat_lh IntRegs:$src1, IntRegs:$src2), - (A2_subh_h16_sat_lh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_subh_h16_sat_hl IntRegs:$src1, IntRegs:$src2), - (A2_subh_h16_sat_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_subh_h16_sat_hh IntRegs:$src1, IntRegs:$src2), - (A2_subh_h16_sat_hh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_aslh IntRegs:$src1), - (A2_aslh IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_asrh IntRegs:$src1), - (A2_asrh IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_addp DoubleRegs:$src1, DoubleRegs:$src2), - (A2_addp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_addpsat DoubleRegs:$src1, DoubleRegs:$src2), - (A2_addpsat DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_addsp IntRegs:$src1, DoubleRegs:$src2), - (A2_addsp IntRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_subp DoubleRegs:$src1, DoubleRegs:$src2), - (A2_subp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_negsat IntRegs:$src1), - (A2_negsat IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_abs IntRegs:$src1), - (A2_abs IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_abssat IntRegs:$src1), - (A2_abssat IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vconj DoubleRegs:$src1), - (A2_vconj DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_negp DoubleRegs:$src1), - (A2_negp DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_absp DoubleRegs:$src1), - (A2_absp DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_max IntRegs:$src1, IntRegs:$src2), - (A2_max IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_maxu IntRegs:$src1, IntRegs:$src2), - (A2_maxu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_min IntRegs:$src1, IntRegs:$src2), - (A2_min IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_minu IntRegs:$src1, IntRegs:$src2), - (A2_minu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_maxp DoubleRegs:$src1, DoubleRegs:$src2), - (A2_maxp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_maxup DoubleRegs:$src1, DoubleRegs:$src2), - (A2_maxup DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_minp DoubleRegs:$src1, DoubleRegs:$src2), - (A2_minp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_minup DoubleRegs:$src1, DoubleRegs:$src2), - (A2_minup DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_tfr IntRegs:$src1), - (A2_tfr IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_tfrsi s32_0ImmPred_timm:$src1), - (A2_tfrsi s32_0ImmPred_timm:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_tfrp DoubleRegs:$src1), - (A2_tfrp DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_zxtb IntRegs:$src1), - (A2_zxtb IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_sxtb IntRegs:$src1), - (A2_sxtb IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_zxth IntRegs:$src1), - (A2_zxth IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_sxth IntRegs:$src1), - (A2_sxth IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_combinew IntRegs:$src1, IntRegs:$src2), - (A2_combinew IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_combineri IntRegs:$src1, s32_0ImmPred_timm:$src2), - (A4_combineri IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_combineir s32_0ImmPred_timm:$src1, IntRegs:$src2), - (A4_combineir s32_0ImmPred_timm:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_combineii s32_0ImmPred_timm:$src1, s8_0ImmPred_timm:$src2), - (A2_combineii s32_0ImmPred_timm:$src1, s8_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_combine_hh IntRegs:$src1, IntRegs:$src2), - (A2_combine_hh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_combine_hl IntRegs:$src1, IntRegs:$src2), - (A2_combine_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_combine_lh IntRegs:$src1, IntRegs:$src2), - (A2_combine_lh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_combine_ll IntRegs:$src1, IntRegs:$src2), - (A2_combine_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_tfril IntRegs:$src1, u16_0ImmPred_timm:$src2), - (A2_tfril IntRegs:$src1, u16_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_tfrih IntRegs:$src1, u16_0ImmPred_timm:$src2), - (A2_tfrih IntRegs:$src1, u16_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_and IntRegs:$src1, IntRegs:$src2), - (A2_and IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_or IntRegs:$src1, IntRegs:$src2), - (A2_or IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_xor IntRegs:$src1, IntRegs:$src2), - (A2_xor IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vdmacs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_vdmacs_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vdmacs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_vdmacs_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vdmpyrs_s0 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vdmpyrs_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vdmpyrs_s1 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vdmpyrs_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vdmpys_s0 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vdmpys_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vdmpys_s1 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vdmpys_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmac2 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_vmac2 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmac2es DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_vmac2es DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmac2es_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_vmac2es_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmac2es_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_vmac2es_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmac2s_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_vmac2s_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmac2s_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_vmac2s_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmac2su_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_vmac2su_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmac2su_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_vmac2su_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmpy2es_s0 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vmpy2es_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmpy2es_s1 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vmpy2es_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmpy2s_s0 IntRegs:$src1, IntRegs:$src2), + (M2_vmpy2s_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmpy2s_s0pack IntRegs:$src1, IntRegs:$src2), + (M2_vmpy2s_s0pack IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmpy2s_s1 IntRegs:$src1, IntRegs:$src2), + (M2_vmpy2s_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmpy2s_s1pack IntRegs:$src1, IntRegs:$src2), + (M2_vmpy2s_s1pack IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmpy2su_s0 IntRegs:$src1, IntRegs:$src2), + (M2_vmpy2su_s0 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vmpy2su_s1 IntRegs:$src1, IntRegs:$src2), + (M2_vmpy2su_s1 IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vraddh DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vraddh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vradduh DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vradduh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vrcmaci_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_vrcmaci_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vrcmaci_s0c DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_vrcmaci_s0c DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vrcmacr_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_vrcmacr_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vrcmacr_s0c DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_vrcmacr_s0c DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vrcmpyi_s0 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vrcmpyi_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vrcmpyi_s0c DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vrcmpyi_s0c DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vrcmpyr_s0 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vrcmpyr_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vrcmpyr_s0c DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vrcmpyr_s0c DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vrcmpys_acc_s1 DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (M2_vrcmpys_acc_s1 DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vrcmpys_s1 DoubleRegs:$src1, IntRegs:$src2), + (M2_vrcmpys_s1 DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vrcmpys_s1rp DoubleRegs:$src1, IntRegs:$src2), + (M2_vrcmpys_s1rp DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vrmac_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M2_vrmac_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M2_vrmpy_s0 DoubleRegs:$src1, DoubleRegs:$src2), + (M2_vrmpy_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M2_xor_xacc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), (M2_xor_xacc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_xor_xacc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M4_xor_xacc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_andn IntRegs:$src1, IntRegs:$src2), - (A4_andn IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_orn IntRegs:$src1, IntRegs:$src2), - (A4_orn IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_andnp DoubleRegs:$src1, DoubleRegs:$src2), - (A4_andnp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_ornp DoubleRegs:$src1, DoubleRegs:$src2), - (A4_ornp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_addaddi IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3), - (S4_addaddi IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>; -def: Pat<(int_hexagon_S4_subaddi IntRegs:$src1, s32_0ImmPred_timm:$src2, IntRegs:$src3), - (S4_subaddi IntRegs:$src1, s32_0ImmPred_timm:$src2, IntRegs:$src3)>, Requires<[UseCompound, HasV5]>; def: Pat<(int_hexagon_M4_and_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), (M4_and_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M4_and_andn IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), @@ -949,6 +1173,28 @@ def: Pat<(int_hexagon_M4_and_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), (M4_and_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M4_and_xor IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), (M4_and_xor IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_cmpyi_wh DoubleRegs:$src1, IntRegs:$src2), + (M4_cmpyi_wh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_cmpyi_whc DoubleRegs:$src1, IntRegs:$src2), + (M4_cmpyi_whc DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_cmpyr_wh DoubleRegs:$src1, IntRegs:$src2), + (M4_cmpyr_wh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_cmpyr_whc DoubleRegs:$src1, IntRegs:$src2), + (M4_cmpyr_whc DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_mac_up_s1_sat IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M4_mac_up_s1_sat IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_mpyri_addi u32_0ImmPred_timm:$src1, IntRegs:$src2, u6_0ImmPred_timm:$src3), + (M4_mpyri_addi u32_0ImmPred_timm:$src1, IntRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>; +def: Pat<(int_hexagon_M4_mpyri_addr IntRegs:$src1, IntRegs:$src2, u32_0ImmPred_timm:$src3), + (M4_mpyri_addr IntRegs:$src1, IntRegs:$src2, u32_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>; +def: Pat<(int_hexagon_M4_mpyri_addr_u2 IntRegs:$src1, u6_2ImmPred_timm:$src2, IntRegs:$src3), + (M4_mpyri_addr_u2 IntRegs:$src1, u6_2ImmPred_timm:$src2, IntRegs:$src3)>, Requires<[UseCompound, HasV5]>; +def: Pat<(int_hexagon_M4_mpyrr_addi u32_0ImmPred_timm:$src1, IntRegs:$src2, IntRegs:$src3), + (M4_mpyrr_addi u32_0ImmPred_timm:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[UseCompound, HasV5]>; +def: Pat<(int_hexagon_M4_mpyrr_addr IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M4_mpyrr_addr IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[UseCompound, HasV5]>; +def: Pat<(int_hexagon_M4_nac_up_s1_sat IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M4_nac_up_s1_sat IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M4_or_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), (M4_or_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M4_or_andn IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), @@ -957,714 +1203,470 @@ def: Pat<(int_hexagon_M4_or_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), (M4_or_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M4_or_xor IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), (M4_or_xor IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_or_andix IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3), - (S4_or_andix IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>; -def: Pat<(int_hexagon_S4_or_andi IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3), - (S4_or_andi IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_or_ori IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3), - (S4_or_ori IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_pmpyw IntRegs:$src1, IntRegs:$src2), + (M4_pmpyw IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_pmpyw_acc DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M4_pmpyw_acc DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_vpmpyh IntRegs:$src1, IntRegs:$src2), + (M4_vpmpyh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_vpmpyh_acc DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M4_vpmpyh_acc DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_vrmpyeh_acc_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M4_vrmpyeh_acc_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_vrmpyeh_acc_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M4_vrmpyeh_acc_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_vrmpyeh_s0 DoubleRegs:$src1, DoubleRegs:$src2), + (M4_vrmpyeh_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_vrmpyeh_s1 DoubleRegs:$src1, DoubleRegs:$src2), + (M4_vrmpyeh_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_vrmpyoh_acc_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M4_vrmpyoh_acc_s0 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_vrmpyoh_acc_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M4_vrmpyoh_acc_s1 DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_vrmpyoh_s0 DoubleRegs:$src1, DoubleRegs:$src2), + (M4_vrmpyoh_s0 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_vrmpyoh_s1 DoubleRegs:$src1, DoubleRegs:$src2), + (M4_vrmpyoh_s1 DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M4_xor_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), (M4_xor_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M4_xor_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M4_xor_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; def: Pat<(int_hexagon_M4_xor_andn IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), (M4_xor_andn IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_subri s32_0ImmPred_timm:$src1, IntRegs:$src2), - (A2_subri s32_0ImmPred_timm:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_andir IntRegs:$src1, s32_0ImmPred_timm:$src2), - (A2_andir IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_orir IntRegs:$src1, s32_0ImmPred_timm:$src2), - (A2_orir IntRegs:$src1, s32_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_andp DoubleRegs:$src1, DoubleRegs:$src2), - (A2_andp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_orp DoubleRegs:$src1, DoubleRegs:$src2), - (A2_orp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_xorp DoubleRegs:$src1, DoubleRegs:$src2), - (A2_xorp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_notp DoubleRegs:$src1), - (A2_notp DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_sxtw IntRegs:$src1), - (A2_sxtw IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_sat DoubleRegs:$src1), - (A2_sat DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_roundsat DoubleRegs:$src1), - (A2_roundsat DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_sath IntRegs:$src1), - (A2_sath IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_satuh IntRegs:$src1), - (A2_satuh IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_satub IntRegs:$src1), - (A2_satub IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_satb IntRegs:$src1), - (A2_satb IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vaddub DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vaddub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vaddb_map DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vaddub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vaddubs DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vaddubs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vaddh DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vaddh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vaddhs DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vaddhs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vadduhs DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vadduhs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A5_vaddhubs DoubleRegs:$src1, DoubleRegs:$src2), - (A5_vaddhubs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vaddw DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vaddw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vaddws DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vaddws DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_vxaddsubw DoubleRegs:$src1, DoubleRegs:$src2), - (S4_vxaddsubw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_vxsubaddw DoubleRegs:$src1, DoubleRegs:$src2), - (S4_vxsubaddw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_vxaddsubh DoubleRegs:$src1, DoubleRegs:$src2), - (S4_vxaddsubh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_vxsubaddh DoubleRegs:$src1, DoubleRegs:$src2), - (S4_vxsubaddh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_vxaddsubhr DoubleRegs:$src1, DoubleRegs:$src2), - (S4_vxaddsubhr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_vxsubaddhr DoubleRegs:$src1, DoubleRegs:$src2), - (S4_vxsubaddhr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_svavgh IntRegs:$src1, IntRegs:$src2), - (A2_svavgh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_svavghs IntRegs:$src1, IntRegs:$src2), - (A2_svavghs IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_svnavgh IntRegs:$src1, IntRegs:$src2), - (A2_svnavgh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_svaddh IntRegs:$src1, IntRegs:$src2), - (A2_svaddh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_svaddhs IntRegs:$src1, IntRegs:$src2), - (A2_svaddhs IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_svadduhs IntRegs:$src1, IntRegs:$src2), - (A2_svadduhs IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_svsubh IntRegs:$src1, IntRegs:$src2), - (A2_svsubh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_svsubhs IntRegs:$src1, IntRegs:$src2), - (A2_svsubhs IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_svsubuhs IntRegs:$src1, IntRegs:$src2), - (A2_svsubuhs IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vraddub DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vraddub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vraddub_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (A2_vraddub_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vraddh DoubleRegs:$src1, DoubleRegs:$src2), - (M2_vraddh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vradduh DoubleRegs:$src1, DoubleRegs:$src2), - (M2_vradduh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vsubub DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vsubub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vsubb_map DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vsubub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vsububs DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vsububs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vsubh DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vsubh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vsubhs DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vsubhs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vsubuhs DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vsubuhs DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vsubw DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vsubw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vsubws DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vsubws DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vabsh DoubleRegs:$src1), - (A2_vabsh DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vabshsat DoubleRegs:$src1), - (A2_vabshsat DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vabsw DoubleRegs:$src1), - (A2_vabsw DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vabswsat DoubleRegs:$src1), - (A2_vabswsat DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vabsdiffw DoubleRegs:$src1, DoubleRegs:$src2), - (M2_vabsdiffw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_M2_vabsdiffh DoubleRegs:$src1, DoubleRegs:$src2), - (M2_vabsdiffh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vrsadub DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vrsadub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vrsadub_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (A2_vrsadub_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vavgub DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vavgub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vavguh DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vavguh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vavgh DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vavgh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vnavgh DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vnavgh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vavgw DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vavgw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vnavgw DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vnavgw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vavgwr DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vavgwr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vnavgwr DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vnavgwr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vavgwcr DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vavgwcr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vnavgwcr DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vnavgwcr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vavghcr DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vavghcr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vnavghcr DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vnavghcr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vavguw DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vavguw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vavguwr DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vavguwr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vavgubr DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vavgubr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vavguhr DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vavguhr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vavghr DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vavghr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vnavghr DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vnavghr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_round_ri IntRegs:$src1, u5_0ImmPred_timm:$src2), - (A4_round_ri IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_round_rr IntRegs:$src1, IntRegs:$src2), - (A4_round_rr IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_round_ri_sat IntRegs:$src1, u5_0ImmPred_timm:$src2), - (A4_round_ri_sat IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_round_rr_sat IntRegs:$src1, IntRegs:$src2), - (A4_round_rr_sat IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_cround_ri IntRegs:$src1, u5_0ImmPred_timm:$src2), - (A4_cround_ri IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_cround_rr IntRegs:$src1, IntRegs:$src2), - (A4_cround_rr IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_vrminh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (A4_vrminh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_vrmaxh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (A4_vrmaxh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_vrminuh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (A4_vrminuh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_vrmaxuh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (A4_vrmaxuh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_vrminw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (A4_vrminw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_vrmaxw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (A4_vrmaxw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_vrminuw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (A4_vrminuw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_vrmaxuw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (A4_vrmaxuw DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vminb DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vminb DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vmaxb DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vmaxb DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vminub DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vminub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vmaxub DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vmaxub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vminh DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vminh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vmaxh DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vmaxh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vminuh DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vminuh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vmaxuh DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vmaxuh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vminw DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vminw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vmaxw DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vmaxw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vminuw DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vminuw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_vmaxuw DoubleRegs:$src1, DoubleRegs:$src2), - (A2_vmaxuw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_modwrapu IntRegs:$src1, IntRegs:$src2), - (A4_modwrapu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_sfadd IntRegs:$src1, IntRegs:$src2), - (F2_sfadd IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_sfsub IntRegs:$src1, IntRegs:$src2), - (F2_sfsub IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_sfmpy IntRegs:$src1, IntRegs:$src2), - (F2_sfmpy IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_sffma IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (F2_sffma IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_sffma_sc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3, PredRegs:$src4), - (F2_sffma_sc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3, (C2_tfrrp PredRegs:$src4))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_sffms IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (F2_sffms IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_sffma_lib IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (F2_sffma_lib IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_sffms_lib IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (F2_sffms_lib IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_sfcmpeq IntRegs:$src1, IntRegs:$src2), - (C2_tfrpr (F2_sfcmpeq IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_sfcmpgt IntRegs:$src1, IntRegs:$src2), - (C2_tfrpr (F2_sfcmpgt IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_sfcmpge IntRegs:$src1, IntRegs:$src2), - (C2_tfrpr (F2_sfcmpge IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_sfcmpuo IntRegs:$src1, IntRegs:$src2), - (C2_tfrpr (F2_sfcmpuo IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_sfmax IntRegs:$src1, IntRegs:$src2), - (F2_sfmax IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_sfmin IntRegs:$src1, IntRegs:$src2), - (F2_sfmin IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_sfclass IntRegs:$src1, u5_0ImmPred_timm:$src2), - (C2_tfrpr (F2_sfclass IntRegs:$src1, u5_0ImmPred_timm:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_sfimm_p u10_0ImmPred_timm:$src1), - (F2_sfimm_p u10_0ImmPred_timm:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_sfimm_n u10_0ImmPred_timm:$src1), - (F2_sfimm_n u10_0ImmPred_timm:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_sffixupn IntRegs:$src1, IntRegs:$src2), - (F2_sffixupn IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_sffixupd IntRegs:$src1, IntRegs:$src2), - (F2_sffixupd IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_sffixupr IntRegs:$src1), - (F2_sffixupr IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_dfcmpeq DoubleRegs:$src1, DoubleRegs:$src2), - (C2_tfrpr (F2_dfcmpeq DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_dfcmpgt DoubleRegs:$src1, DoubleRegs:$src2), - (C2_tfrpr (F2_dfcmpgt DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_dfcmpge DoubleRegs:$src1, DoubleRegs:$src2), - (C2_tfrpr (F2_dfcmpge DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_dfcmpuo DoubleRegs:$src1, DoubleRegs:$src2), - (C2_tfrpr (F2_dfcmpuo DoubleRegs:$src1, DoubleRegs:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_dfclass DoubleRegs:$src1, u5_0ImmPred_timm:$src2), - (C2_tfrpr (F2_dfclass DoubleRegs:$src1, u5_0ImmPred_timm:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_dfimm_p u10_0ImmPred_timm:$src1), - (F2_dfimm_p u10_0ImmPred_timm:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_dfimm_n u10_0ImmPred_timm:$src1), - (F2_dfimm_n u10_0ImmPred_timm:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_sf2df IntRegs:$src1), - (F2_conv_sf2df IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_df2sf DoubleRegs:$src1), - (F2_conv_df2sf DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_uw2sf IntRegs:$src1), - (F2_conv_uw2sf IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_uw2df IntRegs:$src1), - (F2_conv_uw2df IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_w2sf IntRegs:$src1), - (F2_conv_w2sf IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_w2df IntRegs:$src1), - (F2_conv_w2df IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_ud2sf DoubleRegs:$src1), - (F2_conv_ud2sf DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_ud2df DoubleRegs:$src1), - (F2_conv_ud2df DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_d2sf DoubleRegs:$src1), - (F2_conv_d2sf DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_d2df DoubleRegs:$src1), - (F2_conv_d2df DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_sf2uw IntRegs:$src1), - (F2_conv_sf2uw IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_sf2w IntRegs:$src1), - (F2_conv_sf2w IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_sf2ud IntRegs:$src1), - (F2_conv_sf2ud IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_sf2d IntRegs:$src1), - (F2_conv_sf2d IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_df2uw DoubleRegs:$src1), - (F2_conv_df2uw DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_df2w DoubleRegs:$src1), - (F2_conv_df2w DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_df2ud DoubleRegs:$src1), - (F2_conv_df2ud DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_df2d DoubleRegs:$src1), - (F2_conv_df2d DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_sf2uw_chop IntRegs:$src1), - (F2_conv_sf2uw_chop IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_sf2w_chop IntRegs:$src1), - (F2_conv_sf2w_chop IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_sf2ud_chop IntRegs:$src1), - (F2_conv_sf2ud_chop IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_sf2d_chop IntRegs:$src1), - (F2_conv_sf2d_chop IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_df2uw_chop DoubleRegs:$src1), - (F2_conv_df2uw_chop DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_df2w_chop DoubleRegs:$src1), - (F2_conv_df2w_chop DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_df2ud_chop DoubleRegs:$src1), - (F2_conv_df2ud_chop DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_F2_conv_df2d_chop DoubleRegs:$src1), - (F2_conv_df2d_chop DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_r_r IntRegs:$src1, IntRegs:$src2), - (S2_asr_r_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_r_r IntRegs:$src1, IntRegs:$src2), - (S2_asl_r_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_r_r IntRegs:$src1, IntRegs:$src2), - (S2_lsr_r_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsl_r_r IntRegs:$src1, IntRegs:$src2), - (S2_lsl_r_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_r_p DoubleRegs:$src1, IntRegs:$src2), - (S2_asr_r_p DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_r_p DoubleRegs:$src1, IntRegs:$src2), - (S2_asl_r_p DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_r_p DoubleRegs:$src1, IntRegs:$src2), - (S2_lsr_r_p DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsl_r_p DoubleRegs:$src1, IntRegs:$src2), - (S2_lsl_r_p DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (S2_asr_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (S2_asl_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (S2_lsr_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsl_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (S2_lsl_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (S2_asr_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (S2_asl_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (S2_lsr_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsl_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (S2_lsl_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (S2_asr_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (S2_asl_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (S2_lsr_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsl_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (S2_lsl_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (S2_asr_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (S2_asl_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (S2_lsr_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsl_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (S2_lsl_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (S2_asr_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (S2_asl_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (S2_lsr_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsl_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (S2_lsl_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (S2_asr_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (S2_asl_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (S2_lsr_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsl_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (S2_lsl_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (S2_asr_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (S2_asl_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (S2_lsr_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsl_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (S2_lsl_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (S2_asr_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (S2_asl_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (S2_lsr_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsl_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (S2_lsl_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (S2_asr_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (S2_asl_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (S2_lsr_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsl_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - (S2_lsl_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_r_r_sat IntRegs:$src1, IntRegs:$src2), - (S2_asr_r_r_sat IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_r_r_sat IntRegs:$src1, IntRegs:$src2), - (S2_asl_r_r_sat IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2), - (S2_asr_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2), - (S2_lsr_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2), - (S2_asl_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_i_p DoubleRegs:$src1, u6_0ImmPred_timm:$src2), - (S2_asr_i_p DoubleRegs:$src1, u6_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_i_p DoubleRegs:$src1, u6_0ImmPred_timm:$src2), - (S2_lsr_i_p DoubleRegs:$src1, u6_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_i_p DoubleRegs:$src1, u6_0ImmPred_timm:$src2), - (S2_asl_i_p DoubleRegs:$src1, u6_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S2_asr_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S2_lsr_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S2_asl_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), - (S2_asr_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), - (S2_lsr_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), - (S2_asl_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S2_asr_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S2_lsr_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S2_asl_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), - (S2_asr_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), - (S2_lsr_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), - (S2_asl_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_i_r_xacc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S2_lsr_i_r_xacc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_i_r_xacc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S2_asl_i_r_xacc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_i_p_xacc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), - (S2_lsr_i_p_xacc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_i_p_xacc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), - (S2_asl_i_p_xacc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S2_asr_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S2_lsr_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S2_asl_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S2_asr_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S2_lsr_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S2_asl_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), - (S2_asr_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), - (S2_lsr_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), - (S2_asl_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), - (S2_asr_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), - (S2_lsr_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), - (S2_asl_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_i_r_sat IntRegs:$src1, u5_0ImmPred_timm:$src2), - (S2_asl_i_r_sat IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_i_r_rnd IntRegs:$src1, u5_0ImmPred_timm:$src2), - (S2_asr_i_r_rnd IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_i_p_rnd DoubleRegs:$src1, u6_0ImmPred_timm:$src2), - (S2_asr_i_p_rnd DoubleRegs:$src1, u6_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_lsli s6_0ImmPred_timm:$src1, IntRegs:$src2), - (S4_lsli s6_0ImmPred_timm:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_xor_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M4_xor_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M4_xor_xacc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M4_xor_xacc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M5_vdmacbsu DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M5_vdmacbsu DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M5_vdmpybsu DoubleRegs:$src1, DoubleRegs:$src2), + (M5_vdmpybsu DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M5_vmacbsu DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M5_vmacbsu DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M5_vmacbuu DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M5_vmacbuu DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M5_vmpybsu IntRegs:$src1, IntRegs:$src2), + (M5_vmpybsu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M5_vmpybuu IntRegs:$src1, IntRegs:$src2), + (M5_vmpybuu IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M5_vrmacbsu DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M5_vrmacbsu DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M5_vrmacbuu DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M5_vrmacbuu DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M5_vrmpybsu DoubleRegs:$src1, DoubleRegs:$src2), + (M5_vrmpybsu DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_M5_vrmpybuu DoubleRegs:$src1, DoubleRegs:$src2), + (M5_vrmpybuu DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_S2_addasl_rrri IntRegs:$src1, IntRegs:$src2, u3_0ImmPred_timm:$src3), (S2_addasl_rrri IntRegs:$src1, IntRegs:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_andi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S4_andi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>; -def: Pat<(int_hexagon_S4_ori_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S4_ori_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>; -def: Pat<(int_hexagon_S4_addi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S4_addi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>; -def: Pat<(int_hexagon_S4_subi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S4_subi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>; -def: Pat<(int_hexagon_S4_andi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S4_andi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>; -def: Pat<(int_hexagon_S4_ori_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S4_ori_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>; -def: Pat<(int_hexagon_S4_addi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S4_addi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>; -def: Pat<(int_hexagon_S4_subi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S4_subi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>; -def: Pat<(int_hexagon_S2_valignib DoubleRegs:$src1, DoubleRegs:$src2, u3_0ImmPred_timm:$src3), - (S2_valignib DoubleRegs:$src1, DoubleRegs:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_valignrb DoubleRegs:$src1, DoubleRegs:$src2, PredRegs:$src3), - (S2_valignrb DoubleRegs:$src1, DoubleRegs:$src2, (C2_tfrrp PredRegs:$src3))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vspliceib DoubleRegs:$src1, DoubleRegs:$src2, u3_0ImmPred_timm:$src3), - (S2_vspliceib DoubleRegs:$src1, DoubleRegs:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vsplicerb DoubleRegs:$src1, DoubleRegs:$src2, PredRegs:$src3), - (S2_vsplicerb DoubleRegs:$src1, DoubleRegs:$src2, (C2_tfrrp PredRegs:$src3))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vsplatrh IntRegs:$src1), - (S2_vsplatrh IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vsplatrb IntRegs:$src1), - (S2_vsplatrb IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_insert IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3, u5_0ImmPred_timm:$src4), - (S2_insert IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3, u5_0ImmPred_timm:$src4)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_bitspliti IntRegs:$src1, u5_0ImmPred_timm:$src2), - (A4_bitspliti IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A4_bitsplit IntRegs:$src1, IntRegs:$src2), - (A4_bitsplit IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_extract IntRegs:$src1, u5_0ImmPred_timm:$src2, u5_0ImmPred_timm:$src3), - (S4_extract IntRegs:$src1, u5_0ImmPred_timm:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_extractu IntRegs:$src1, u5_0ImmPred_timm:$src2, u5_0ImmPred_timm:$src3), - (S2_extractu IntRegs:$src1, u5_0ImmPred_timm:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_insertp DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3, u6_0ImmPred_timm:$src4), - (S2_insertp DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3, u6_0ImmPred_timm:$src4)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_extractp DoubleRegs:$src1, u6_0ImmPred_timm:$src2, u6_0ImmPred_timm:$src3), - (S4_extractp DoubleRegs:$src1, u6_0ImmPred_timm:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_extractup DoubleRegs:$src1, u6_0ImmPred_timm:$src2, u6_0ImmPred_timm:$src3), - (S2_extractup DoubleRegs:$src1, u6_0ImmPred_timm:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_insert_rp IntRegs:$src1, IntRegs:$src2, DoubleRegs:$src3), - (S2_insert_rp IntRegs:$src1, IntRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_extract_rp IntRegs:$src1, DoubleRegs:$src2), - (S4_extract_rp IntRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_extractu_rp IntRegs:$src1, DoubleRegs:$src2), - (S2_extractu_rp IntRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_insertp_rp DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (S2_insertp_rp DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_extractp_rp DoubleRegs:$src1, DoubleRegs:$src2), - (S4_extractp_rp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_extractup_rp DoubleRegs:$src1, DoubleRegs:$src2), - (S2_extractup_rp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_tstbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2), - (C2_tfrpr (S2_tstbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_ntstbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2), - (C2_tfrpr (S4_ntstbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_setbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2), - (S2_setbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_togglebit_i IntRegs:$src1, u5_0ImmPred_timm:$src2), - (S2_togglebit_i IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_clrbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2), - (S2_clrbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_tstbit_r IntRegs:$src1, IntRegs:$src2), - (C2_tfrpr (S2_tstbit_r IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_ntstbit_r IntRegs:$src1, IntRegs:$src2), - (C2_tfrpr (S4_ntstbit_r IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_setbit_r IntRegs:$src1, IntRegs:$src2), - (S2_setbit_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_togglebit_r IntRegs:$src1, IntRegs:$src2), - (S2_togglebit_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_clrbit_r IntRegs:$src1, IntRegs:$src2), - (S2_clrbit_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_i_vh DoubleRegs:$src1, u4_0ImmPred_timm:$src2), - (S2_asr_i_vh DoubleRegs:$src1, u4_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_i_vh DoubleRegs:$src1, u4_0ImmPred_timm:$src2), - (S2_lsr_i_vh DoubleRegs:$src1, u4_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_i_p DoubleRegs:$src1, u6_0ImmPred_timm:$src2), + (S2_asl_i_p DoubleRegs:$src1, u6_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), + (S2_asl_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), + (S2_asl_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), + (S2_asl_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), + (S2_asl_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_i_p_xacc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), + (S2_asl_i_p_xacc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2), + (S2_asl_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S2_asl_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S2_asl_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S2_asl_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S2_asl_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_i_r_sat IntRegs:$src1, u5_0ImmPred_timm:$src2), + (S2_asl_i_r_sat IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_i_r_xacc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S2_asl_i_r_xacc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; def: Pat<(int_hexagon_S2_asl_i_vh DoubleRegs:$src1, u4_0ImmPred_timm:$src2), (S2_asl_i_vh DoubleRegs:$src1, u4_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_r_vh DoubleRegs:$src1, IntRegs:$src2), - (S2_asr_r_vh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S5_asrhub_sat DoubleRegs:$src1, u4_0ImmPred_timm:$src2), - (S5_asrhub_sat DoubleRegs:$src1, u4_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asl_r_vh DoubleRegs:$src1, IntRegs:$src2), - (S2_asl_r_vh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_r_vh DoubleRegs:$src1, IntRegs:$src2), - (S2_lsr_r_vh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsl_r_vh DoubleRegs:$src1, IntRegs:$src2), - (S2_lsl_r_vh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_i_vw DoubleRegs:$src1, u5_0ImmPred_timm:$src2), - (S2_asr_i_vw DoubleRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_i_svw_trun DoubleRegs:$src1, u5_0ImmPred_timm:$src2), - (S2_asr_i_svw_trun DoubleRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_r_svw_trun DoubleRegs:$src1, IntRegs:$src2), - (S2_asr_r_svw_trun DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_i_vw DoubleRegs:$src1, u5_0ImmPred_timm:$src2), - (S2_lsr_i_vw DoubleRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_S2_asl_i_vw DoubleRegs:$src1, u5_0ImmPred_timm:$src2), (S2_asl_i_vw DoubleRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_asr_r_vw DoubleRegs:$src1, IntRegs:$src2), - (S2_asr_r_vw DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_r_p DoubleRegs:$src1, IntRegs:$src2), + (S2_asl_r_p DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_asl_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_asl_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_asl_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_asl_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_asl_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_r_r IntRegs:$src1, IntRegs:$src2), + (S2_asl_r_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_asl_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_asl_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_asl_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_asl_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_r_r_sat IntRegs:$src1, IntRegs:$src2), + (S2_asl_r_r_sat IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asl_r_vh DoubleRegs:$src1, IntRegs:$src2), + (S2_asl_r_vh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_S2_asl_r_vw DoubleRegs:$src1, IntRegs:$src2), (S2_asl_r_vw DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsr_r_vw DoubleRegs:$src1, IntRegs:$src2), - (S2_lsr_r_vw DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lsl_r_vw DoubleRegs:$src1, IntRegs:$src2), - (S2_lsl_r_vw DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vrndpackwh DoubleRegs:$src1), - (S2_vrndpackwh DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vrndpackwhs DoubleRegs:$src1), - (S2_vrndpackwhs DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vsxtbh IntRegs:$src1), - (S2_vsxtbh IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vzxtbh IntRegs:$src1), - (S2_vzxtbh IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vsathub DoubleRegs:$src1), - (S2_vsathub DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_svsathub IntRegs:$src1), - (S2_svsathub IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_svsathb IntRegs:$src1), - (S2_svsathb IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vsathb DoubleRegs:$src1), - (S2_vsathb DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vtrunohb DoubleRegs:$src1), - (S2_vtrunohb DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vtrunewh DoubleRegs:$src1, DoubleRegs:$src2), - (S2_vtrunewh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vtrunowh DoubleRegs:$src1, DoubleRegs:$src2), - (S2_vtrunowh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vtrunehb DoubleRegs:$src1), - (S2_vtrunehb DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vsxthw IntRegs:$src1), - (S2_vsxthw IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vzxthw IntRegs:$src1), - (S2_vzxthw IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vsatwh DoubleRegs:$src1), - (S2_vsatwh DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vsatwuh DoubleRegs:$src1), - (S2_vsatwuh DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_packhl IntRegs:$src1, IntRegs:$src2), - (S2_packhl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_A2_swiz IntRegs:$src1), - (A2_swiz IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vsathub_nopack DoubleRegs:$src1), - (S2_vsathub_nopack DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vsathb_nopack DoubleRegs:$src1), - (S2_vsathb_nopack DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vsatwh_nopack DoubleRegs:$src1), - (S2_vsatwh_nopack DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_vsatwuh_nopack DoubleRegs:$src1), - (S2_vsatwuh_nopack DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_shuffob DoubleRegs:$src1, DoubleRegs:$src2), - (S2_shuffob DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_shuffeb DoubleRegs:$src1, DoubleRegs:$src2), - (S2_shuffeb DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_shuffoh DoubleRegs:$src1, DoubleRegs:$src2), - (S2_shuffoh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_shuffeh DoubleRegs:$src1, DoubleRegs:$src2), - (S2_shuffeh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S5_popcountp DoubleRegs:$src1), - (S5_popcountp DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_parity IntRegs:$src1, IntRegs:$src2), - (S4_parity IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_parityp DoubleRegs:$src1, DoubleRegs:$src2), - (S2_parityp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_lfsp DoubleRegs:$src1, DoubleRegs:$src2), - (S2_lfsp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_clbnorm IntRegs:$src1), - (S2_clbnorm IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_clbaddi IntRegs:$src1, s6_0ImmPred_timm:$src2), - (S4_clbaddi IntRegs:$src1, s6_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_clbpnorm DoubleRegs:$src1), - (S4_clbpnorm DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S4_clbpaddi DoubleRegs:$src1, s6_0ImmPred_timm:$src2), - (S4_clbpaddi DoubleRegs:$src1, s6_0ImmPred_timm:$src2)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_clb IntRegs:$src1), - (S2_clb IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_cl0 IntRegs:$src1), - (S2_cl0 IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_cl1 IntRegs:$src1), - (S2_cl1 IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_clbp DoubleRegs:$src1), - (S2_clbp DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_cl0p DoubleRegs:$src1), - (S2_cl0p DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_cl1p DoubleRegs:$src1), - (S2_cl1p DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_i_p DoubleRegs:$src1, u6_0ImmPred_timm:$src2), + (S2_asr_i_p DoubleRegs:$src1, u6_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), + (S2_asr_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), + (S2_asr_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), + (S2_asr_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), + (S2_asr_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_i_p_rnd DoubleRegs:$src1, u6_0ImmPred_timm:$src2), + (S2_asr_i_p_rnd DoubleRegs:$src1, u6_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2), + (S2_asr_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S2_asr_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S2_asr_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S2_asr_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S2_asr_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_i_r_rnd IntRegs:$src1, u5_0ImmPred_timm:$src2), + (S2_asr_i_r_rnd IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_i_svw_trun DoubleRegs:$src1, u5_0ImmPred_timm:$src2), + (S2_asr_i_svw_trun DoubleRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_i_vh DoubleRegs:$src1, u4_0ImmPred_timm:$src2), + (S2_asr_i_vh DoubleRegs:$src1, u4_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_i_vw DoubleRegs:$src1, u5_0ImmPred_timm:$src2), + (S2_asr_i_vw DoubleRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_r_p DoubleRegs:$src1, IntRegs:$src2), + (S2_asr_r_p DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_asr_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_asr_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_asr_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_asr_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_asr_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_r_r IntRegs:$src1, IntRegs:$src2), + (S2_asr_r_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_asr_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_asr_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_asr_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_asr_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_r_r_sat IntRegs:$src1, IntRegs:$src2), + (S2_asr_r_r_sat IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_r_svw_trun DoubleRegs:$src1, IntRegs:$src2), + (S2_asr_r_svw_trun DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_r_vh DoubleRegs:$src1, IntRegs:$src2), + (S2_asr_r_vh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_asr_r_vw DoubleRegs:$src1, IntRegs:$src2), + (S2_asr_r_vw DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_S2_brev IntRegs:$src1), (S2_brev IntRegs:$src1)>, Requires<[HasV5]>; def: Pat<(int_hexagon_S2_brevp DoubleRegs:$src1), (S2_brevp DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_cl0 IntRegs:$src1), + (S2_cl0 IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_cl0p DoubleRegs:$src1), + (S2_cl0p DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_cl1 IntRegs:$src1), + (S2_cl1 IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_cl1p DoubleRegs:$src1), + (S2_cl1p DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_clb IntRegs:$src1), + (S2_clb IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_clbnorm IntRegs:$src1), + (S2_clbnorm IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_clbp DoubleRegs:$src1), + (S2_clbp DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_clrbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2), + (S2_clrbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_clrbit_r IntRegs:$src1, IntRegs:$src2), + (S2_clrbit_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_S2_ct0 IntRegs:$src1), (S2_ct0 IntRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_ct1 IntRegs:$src1), - (S2_ct1 IntRegs:$src1)>, Requires<[HasV5]>; def: Pat<(int_hexagon_S2_ct0p DoubleRegs:$src1), (S2_ct0p DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_ct1 IntRegs:$src1), + (S2_ct1 IntRegs:$src1)>, Requires<[HasV5]>; def: Pat<(int_hexagon_S2_ct1p DoubleRegs:$src1), (S2_ct1p DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_S2_interleave DoubleRegs:$src1), - (S2_interleave DoubleRegs:$src1)>, Requires<[HasV5]>; def: Pat<(int_hexagon_S2_deinterleave DoubleRegs:$src1), (S2_deinterleave DoubleRegs:$src1)>, Requires<[HasV5]>; -def: Pat<(int_hexagon_Y2_dczeroa IntRegs:$src1), - (Y2_dczeroa IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_extractu IntRegs:$src1, u5_0ImmPred_timm:$src2, u5_0ImmPred_timm:$src3), + (S2_extractu IntRegs:$src1, u5_0ImmPred_timm:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_extractu_rp IntRegs:$src1, DoubleRegs:$src2), + (S2_extractu_rp IntRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_extractup DoubleRegs:$src1, u6_0ImmPred_timm:$src2, u6_0ImmPred_timm:$src3), + (S2_extractup DoubleRegs:$src1, u6_0ImmPred_timm:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_extractup_rp DoubleRegs:$src1, DoubleRegs:$src2), + (S2_extractup_rp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_insert IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3, u5_0ImmPred_timm:$src4), + (S2_insert IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3, u5_0ImmPred_timm:$src4)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_insert_rp IntRegs:$src1, IntRegs:$src2, DoubleRegs:$src3), + (S2_insert_rp IntRegs:$src1, IntRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_insertp DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3, u6_0ImmPred_timm:$src4), + (S2_insertp DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3, u6_0ImmPred_timm:$src4)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_insertp_rp DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (S2_insertp_rp DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_interleave DoubleRegs:$src1), + (S2_interleave DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lfsp DoubleRegs:$src1, DoubleRegs:$src2), + (S2_lfsp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsl_r_p DoubleRegs:$src1, IntRegs:$src2), + (S2_lsl_r_p DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsl_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_lsl_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsl_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_lsl_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsl_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_lsl_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsl_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_lsl_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsl_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_lsl_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsl_r_r IntRegs:$src1, IntRegs:$src2), + (S2_lsl_r_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsl_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_lsl_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsl_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_lsl_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsl_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_lsl_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsl_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_lsl_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsl_r_vh DoubleRegs:$src1, IntRegs:$src2), + (S2_lsl_r_vh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsl_r_vw DoubleRegs:$src1, IntRegs:$src2), + (S2_lsl_r_vw DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_i_p DoubleRegs:$src1, u6_0ImmPred_timm:$src2), + (S2_lsr_i_p DoubleRegs:$src1, u6_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), + (S2_lsr_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), + (S2_lsr_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), + (S2_lsr_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), + (S2_lsr_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_i_p_xacc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), + (S2_lsr_i_p_xacc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2), + (S2_lsr_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S2_lsr_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S2_lsr_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S2_lsr_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S2_lsr_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_i_r_xacc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S2_lsr_i_r_xacc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_i_vh DoubleRegs:$src1, u4_0ImmPred_timm:$src2), + (S2_lsr_i_vh DoubleRegs:$src1, u4_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_i_vw DoubleRegs:$src1, u5_0ImmPred_timm:$src2), + (S2_lsr_i_vw DoubleRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_r_p DoubleRegs:$src1, IntRegs:$src2), + (S2_lsr_r_p DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_lsr_r_p_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_lsr_r_p_and DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_lsr_r_p_nac DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_lsr_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_lsr_r_p_xor DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_r_r IntRegs:$src1, IntRegs:$src2), + (S2_lsr_r_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_lsr_r_r_acc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_lsr_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_lsr_r_r_nac IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (S2_lsr_r_r_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_r_vh DoubleRegs:$src1, IntRegs:$src2), + (S2_lsr_r_vh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_lsr_r_vw DoubleRegs:$src1, IntRegs:$src2), + (S2_lsr_r_vw DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_packhl IntRegs:$src1, IntRegs:$src2), + (S2_packhl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_parityp DoubleRegs:$src1, DoubleRegs:$src2), + (S2_parityp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_setbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2), + (S2_setbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_setbit_r IntRegs:$src1, IntRegs:$src2), + (S2_setbit_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_shuffeb DoubleRegs:$src1, DoubleRegs:$src2), + (S2_shuffeb DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_shuffeh DoubleRegs:$src1, DoubleRegs:$src2), + (S2_shuffeh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_shuffob DoubleRegs:$src1, DoubleRegs:$src2), + (S2_shuffob DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_shuffoh DoubleRegs:$src1, DoubleRegs:$src2), + (S2_shuffoh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_svsathb IntRegs:$src1), + (S2_svsathb IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_svsathub IntRegs:$src1), + (S2_svsathub IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_togglebit_i IntRegs:$src1, u5_0ImmPred_timm:$src2), + (S2_togglebit_i IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_togglebit_r IntRegs:$src1, IntRegs:$src2), + (S2_togglebit_r IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_tstbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2), + (C2_tfrpr (S2_tstbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_tstbit_r IntRegs:$src1, IntRegs:$src2), + (C2_tfrpr (S2_tstbit_r IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_valignib DoubleRegs:$src1, DoubleRegs:$src2, u3_0ImmPred_timm:$src3), + (S2_valignib DoubleRegs:$src1, DoubleRegs:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_valignrb DoubleRegs:$src1, DoubleRegs:$src2, PredRegs:$src3), + (S2_valignrb DoubleRegs:$src1, DoubleRegs:$src2, (C2_tfrrp PredRegs:$src3))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vcnegh DoubleRegs:$src1, IntRegs:$src2), + (S2_vcnegh DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vcrotate DoubleRegs:$src1, IntRegs:$src2), + (S2_vcrotate DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vrcnegh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), + (S2_vrcnegh DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vrndpackwh DoubleRegs:$src1), + (S2_vrndpackwh DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vrndpackwhs DoubleRegs:$src1), + (S2_vrndpackwhs DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vsathb DoubleRegs:$src1), + (S2_vsathb DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vsathb_nopack DoubleRegs:$src1), + (S2_vsathb_nopack DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vsathub DoubleRegs:$src1), + (S2_vsathub DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vsathub_nopack DoubleRegs:$src1), + (S2_vsathub_nopack DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vsatwh DoubleRegs:$src1), + (S2_vsatwh DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vsatwh_nopack DoubleRegs:$src1), + (S2_vsatwh_nopack DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vsatwuh DoubleRegs:$src1), + (S2_vsatwuh DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vsatwuh_nopack DoubleRegs:$src1), + (S2_vsatwuh_nopack DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vsplatrb IntRegs:$src1), + (S2_vsplatrb IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vsplatrh IntRegs:$src1), + (S2_vsplatrh IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vspliceib DoubleRegs:$src1, DoubleRegs:$src2, u3_0ImmPred_timm:$src3), + (S2_vspliceib DoubleRegs:$src1, DoubleRegs:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vsplicerb DoubleRegs:$src1, DoubleRegs:$src2, PredRegs:$src3), + (S2_vsplicerb DoubleRegs:$src1, DoubleRegs:$src2, (C2_tfrrp PredRegs:$src3))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vsxtbh IntRegs:$src1), + (S2_vsxtbh IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vsxthw IntRegs:$src1), + (S2_vsxthw IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vtrunehb DoubleRegs:$src1), + (S2_vtrunehb DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vtrunewh DoubleRegs:$src1, DoubleRegs:$src2), + (S2_vtrunewh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vtrunohb DoubleRegs:$src1), + (S2_vtrunohb DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vtrunowh DoubleRegs:$src1, DoubleRegs:$src2), + (S2_vtrunowh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vzxtbh IntRegs:$src1), + (S2_vzxtbh IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S2_vzxthw IntRegs:$src1), + (S2_vzxthw IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_addaddi IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3), + (S4_addaddi IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>; +def: Pat<(int_hexagon_S4_addi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S4_addi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>; +def: Pat<(int_hexagon_S4_addi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S4_addi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>; +def: Pat<(int_hexagon_S4_andi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S4_andi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>; +def: Pat<(int_hexagon_S4_andi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S4_andi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>; +def: Pat<(int_hexagon_S4_clbaddi IntRegs:$src1, s6_0ImmPred_timm:$src2), + (S4_clbaddi IntRegs:$src1, s6_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_clbpaddi DoubleRegs:$src1, s6_0ImmPred_timm:$src2), + (S4_clbpaddi DoubleRegs:$src1, s6_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_clbpnorm DoubleRegs:$src1), + (S4_clbpnorm DoubleRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_extract IntRegs:$src1, u5_0ImmPred_timm:$src2, u5_0ImmPred_timm:$src3), + (S4_extract IntRegs:$src1, u5_0ImmPred_timm:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_extract_rp IntRegs:$src1, DoubleRegs:$src2), + (S4_extract_rp IntRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_extractp DoubleRegs:$src1, u6_0ImmPred_timm:$src2, u6_0ImmPred_timm:$src3), + (S4_extractp DoubleRegs:$src1, u6_0ImmPred_timm:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_extractp_rp DoubleRegs:$src1, DoubleRegs:$src2), + (S4_extractp_rp DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_lsli s6_0ImmPred_timm:$src1, IntRegs:$src2), + (S4_lsli s6_0ImmPred_timm:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_ntstbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2), + (C2_tfrpr (S4_ntstbit_i IntRegs:$src1, u5_0ImmPred_timm:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_ntstbit_r IntRegs:$src1, IntRegs:$src2), + (C2_tfrpr (S4_ntstbit_r IntRegs:$src1, IntRegs:$src2))>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_or_andi IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3), + (S4_or_andi IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_or_andix IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3), + (S4_or_andix IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>; +def: Pat<(int_hexagon_S4_or_ori IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3), + (S4_or_ori IntRegs:$src1, IntRegs:$src2, s32_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_ori_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S4_ori_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>; +def: Pat<(int_hexagon_S4_ori_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S4_ori_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>; +def: Pat<(int_hexagon_S4_parity IntRegs:$src1, IntRegs:$src2), + (S4_parity IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_subaddi IntRegs:$src1, s32_0ImmPred_timm:$src2, IntRegs:$src3), + (S4_subaddi IntRegs:$src1, s32_0ImmPred_timm:$src2, IntRegs:$src3)>, Requires<[UseCompound, HasV5]>; +def: Pat<(int_hexagon_S4_subi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S4_subi_asl_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>; +def: Pat<(int_hexagon_S4_subi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S4_subi_lsr_ri u32_0ImmPred_timm:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[UseCompound, HasV5]>; +def: Pat<(int_hexagon_S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2, u2_0ImmPred_timm:$src3), + (S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2, u2_0ImmPred_timm:$src3)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_vrcrotate_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3, u2_0ImmPred_timm:$src4), + (S4_vrcrotate_acc DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3, u2_0ImmPred_timm:$src4)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_vxaddsubh DoubleRegs:$src1, DoubleRegs:$src2), + (S4_vxaddsubh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_vxaddsubhr DoubleRegs:$src1, DoubleRegs:$src2), + (S4_vxaddsubhr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_vxaddsubw DoubleRegs:$src1, DoubleRegs:$src2), + (S4_vxaddsubw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_vxsubaddh DoubleRegs:$src1, DoubleRegs:$src2), + (S4_vxsubaddh DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_vxsubaddhr DoubleRegs:$src1, DoubleRegs:$src2), + (S4_vxsubaddhr DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S4_vxsubaddw DoubleRegs:$src1, DoubleRegs:$src2), + (S4_vxsubaddw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S5_asrhub_sat DoubleRegs:$src1, u4_0ImmPred_timm:$src2), + (S5_asrhub_sat DoubleRegs:$src1, u4_0ImmPred_timm:$src2)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_S5_popcountp DoubleRegs:$src1), + (S5_popcountp DoubleRegs:$src1)>, Requires<[HasV5]>; def: Pat<(int_hexagon_Y2_dccleana IntRegs:$src1), (Y2_dccleana IntRegs:$src1)>, Requires<[HasV5]>; def: Pat<(int_hexagon_Y2_dccleaninva IntRegs:$src1), (Y2_dccleaninva IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_Y2_dcfetch IntRegs:$src1), + (Y2_dcfetch IntRegs:$src1)>, Requires<[HasV5]>; def: Pat<(int_hexagon_Y2_dcinva IntRegs:$src1), (Y2_dcinva IntRegs:$src1)>, Requires<[HasV5]>; +def: Pat<(int_hexagon_Y2_dczeroa IntRegs:$src1), + (Y2_dczeroa IntRegs:$src1)>, Requires<[HasV5]>; def: Pat<(int_hexagon_Y4_l2fetch IntRegs:$src1, IntRegs:$src2), (Y4_l2fetch IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>; def: Pat<(int_hexagon_Y5_l2fetch IntRegs:$src1, DoubleRegs:$src2), @@ -1672,30 +1674,30 @@ def: Pat<(int_hexagon_Y5_l2fetch IntRegs:$src1, DoubleRegs:$src2), // V60 Scalar Instructions. -def: Pat<(int_hexagon_S6_rol_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2), - (S6_rol_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV60]>; def: Pat<(int_hexagon_S6_rol_i_p DoubleRegs:$src1, u6_0ImmPred_timm:$src2), (S6_rol_i_p DoubleRegs:$src1, u6_0ImmPred_timm:$src2)>, Requires<[HasV60]>; -def: Pat<(int_hexagon_S6_rol_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S6_rol_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV60]>; def: Pat<(int_hexagon_S6_rol_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), (S6_rol_i_p_acc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV60]>; -def: Pat<(int_hexagon_S6_rol_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S6_rol_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV60]>; -def: Pat<(int_hexagon_S6_rol_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), - (S6_rol_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV60]>; -def: Pat<(int_hexagon_S6_rol_i_r_xacc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S6_rol_i_r_xacc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV60]>; -def: Pat<(int_hexagon_S6_rol_i_p_xacc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), - (S6_rol_i_p_xacc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV60]>; -def: Pat<(int_hexagon_S6_rol_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S6_rol_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV60]>; -def: Pat<(int_hexagon_S6_rol_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), - (S6_rol_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV60]>; def: Pat<(int_hexagon_S6_rol_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), (S6_rol_i_p_and DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV60]>; +def: Pat<(int_hexagon_S6_rol_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), + (S6_rol_i_p_nac DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV60]>; def: Pat<(int_hexagon_S6_rol_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), (S6_rol_i_p_or DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV60]>; +def: Pat<(int_hexagon_S6_rol_i_p_xacc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3), + (S6_rol_i_p_xacc DoubleRegs:$src1, DoubleRegs:$src2, u6_0ImmPred_timm:$src3)>, Requires<[HasV60]>; +def: Pat<(int_hexagon_S6_rol_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2), + (S6_rol_i_r IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV60]>; +def: Pat<(int_hexagon_S6_rol_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S6_rol_i_r_acc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV60]>; +def: Pat<(int_hexagon_S6_rol_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S6_rol_i_r_and IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV60]>; +def: Pat<(int_hexagon_S6_rol_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S6_rol_i_r_nac IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV60]>; +def: Pat<(int_hexagon_S6_rol_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S6_rol_i_r_or IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV60]>; +def: Pat<(int_hexagon_S6_rol_i_r_xacc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3), + (S6_rol_i_r_xacc IntRegs:$src1, IntRegs:$src2, u5_0ImmPred_timm:$src3)>, Requires<[HasV60]>; // V62 Scalar Instructions. @@ -1717,59 +1719,23 @@ def: Pat<(int_hexagon_A6_vcmpbeq_notany DoubleRegs:$src1, DoubleRegs:$src2), // V66 Scalar Instructions. -def: Pat<(int_hexagon_M2_mnaci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - (M2_mnaci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV66]>; def: Pat<(int_hexagon_F2_dfadd DoubleRegs:$src1, DoubleRegs:$src2), (F2_dfadd DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV66]>; def: Pat<(int_hexagon_F2_dfsub DoubleRegs:$src1, DoubleRegs:$src2), (F2_dfsub DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV66]>; +def: Pat<(int_hexagon_M2_mnaci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), + (M2_mnaci IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>, Requires<[HasV66]>; def: Pat<(int_hexagon_S2_mask u5_0ImmPred_timm:$src1, u5_0ImmPred_timm:$src2), (S2_mask u5_0ImmPred_timm:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV66]>; // V67 Scalar Instructions. -def: Pat<(int_hexagon_M7_dcmpyrw DoubleRegs:$src1, DoubleRegs:$src2), - (M7_dcmpyrw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; -def: Pat<(int_hexagon_M7_dcmpyrw_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M7_dcmpyrw_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV67]>; -def: Pat<(int_hexagon_M7_dcmpyrwc DoubleRegs:$src1, DoubleRegs:$src2), - (M7_dcmpyrwc DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; -def: Pat<(int_hexagon_M7_dcmpyrwc_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M7_dcmpyrwc_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV67]>; -def: Pat<(int_hexagon_M7_dcmpyiw DoubleRegs:$src1, DoubleRegs:$src2), - (M7_dcmpyiw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; -def: Pat<(int_hexagon_M7_dcmpyiw_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M7_dcmpyiw_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV67]>; -def: Pat<(int_hexagon_M7_dcmpyiwc DoubleRegs:$src1, DoubleRegs:$src2), - (M7_dcmpyiwc DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; -def: Pat<(int_hexagon_M7_dcmpyiwc_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M7_dcmpyiwc_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV67]>; -def: Pat<(int_hexagon_M7_vdmpy DoubleRegs:$src1, DoubleRegs:$src2), - (M7_dcmpyrwc DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; -def: Pat<(int_hexagon_M7_vdmpy_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (M7_dcmpyrwc_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV67]>; -def: Pat<(int_hexagon_M7_wcmpyrw DoubleRegs:$src1, DoubleRegs:$src2), - (M7_wcmpyrw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; -def: Pat<(int_hexagon_M7_wcmpyrwc DoubleRegs:$src1, DoubleRegs:$src2), - (M7_wcmpyrwc DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; -def: Pat<(int_hexagon_M7_wcmpyiw DoubleRegs:$src1, DoubleRegs:$src2), - (M7_wcmpyiw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; -def: Pat<(int_hexagon_M7_wcmpyiwc DoubleRegs:$src1, DoubleRegs:$src2), - (M7_wcmpyiwc DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; -def: Pat<(int_hexagon_M7_wcmpyrw_rnd DoubleRegs:$src1, DoubleRegs:$src2), - (M7_wcmpyrw_rnd DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; -def: Pat<(int_hexagon_M7_wcmpyrwc_rnd DoubleRegs:$src1, DoubleRegs:$src2), - (M7_wcmpyrwc_rnd DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; -def: Pat<(int_hexagon_M7_wcmpyiw_rnd DoubleRegs:$src1, DoubleRegs:$src2), - (M7_wcmpyiw_rnd DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; -def: Pat<(int_hexagon_M7_wcmpyiwc_rnd DoubleRegs:$src1, DoubleRegs:$src2), - (M7_wcmpyiwc_rnd DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_A7_clip IntRegs:$src1, u5_0ImmPred_timm:$src2), + (A7_clip IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV67]>; def: Pat<(int_hexagon_A7_croundd_ri DoubleRegs:$src1, u6_0ImmPred_timm:$src2), (A7_croundd_ri DoubleRegs:$src1, u6_0ImmPred_timm:$src2)>, Requires<[HasV67]>; def: Pat<(int_hexagon_A7_croundd_rr DoubleRegs:$src1, IntRegs:$src2), (A7_croundd_rr DoubleRegs:$src1, IntRegs:$src2)>, Requires<[HasV67]>; -def: Pat<(int_hexagon_A7_clip IntRegs:$src1, u5_0ImmPred_timm:$src2), - (A7_clip IntRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV67]>; def: Pat<(int_hexagon_A7_vclip DoubleRegs:$src1, u5_0ImmPred_timm:$src2), (A7_vclip DoubleRegs:$src1, u5_0ImmPred_timm:$src2)>, Requires<[HasV67]>; def: Pat<(int_hexagon_F2_dfmax DoubleRegs:$src1, DoubleRegs:$src2), @@ -1778,123 +1744,422 @@ def: Pat<(int_hexagon_F2_dfmin DoubleRegs:$src1, DoubleRegs:$src2), (F2_dfmin DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; def: Pat<(int_hexagon_F2_dfmpyfix DoubleRegs:$src1, DoubleRegs:$src2), (F2_dfmpyfix DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; -def: Pat<(int_hexagon_F2_dfmpyll DoubleRegs:$src1, DoubleRegs:$src2), - (F2_dfmpyll DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; -def: Pat<(int_hexagon_F2_dfmpylh DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), - (F2_dfmpylh DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV67]>; def: Pat<(int_hexagon_F2_dfmpyhh DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), (F2_dfmpyhh DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_F2_dfmpylh DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (F2_dfmpylh DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_F2_dfmpyll DoubleRegs:$src1, DoubleRegs:$src2), + (F2_dfmpyll DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_M7_dcmpyiw DoubleRegs:$src1, DoubleRegs:$src2), + (M7_dcmpyiw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_M7_dcmpyiw_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M7_dcmpyiw_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_M7_dcmpyiwc DoubleRegs:$src1, DoubleRegs:$src2), + (M7_dcmpyiwc DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_M7_dcmpyiwc_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M7_dcmpyiwc_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_M7_dcmpyrw DoubleRegs:$src1, DoubleRegs:$src2), + (M7_dcmpyrw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_M7_dcmpyrw_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M7_dcmpyrw_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_M7_dcmpyrwc DoubleRegs:$src1, DoubleRegs:$src2), + (M7_dcmpyrwc DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_M7_dcmpyrwc_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M7_dcmpyrwc_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_M7_vdmpy DoubleRegs:$src1, DoubleRegs:$src2), + (M7_dcmpyrwc DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_M7_vdmpy_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), + (M7_dcmpyrwc_acc DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_M7_wcmpyiw DoubleRegs:$src1, DoubleRegs:$src2), + (M7_wcmpyiw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_M7_wcmpyiw_rnd DoubleRegs:$src1, DoubleRegs:$src2), + (M7_wcmpyiw_rnd DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_M7_wcmpyiwc DoubleRegs:$src1, DoubleRegs:$src2), + (M7_wcmpyiwc DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_M7_wcmpyiwc_rnd DoubleRegs:$src1, DoubleRegs:$src2), + (M7_wcmpyiwc_rnd DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_M7_wcmpyrw DoubleRegs:$src1, DoubleRegs:$src2), + (M7_wcmpyrw DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_M7_wcmpyrw_rnd DoubleRegs:$src1, DoubleRegs:$src2), + (M7_wcmpyrw_rnd DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_M7_wcmpyrwc DoubleRegs:$src1, DoubleRegs:$src2), + (M7_wcmpyrwc DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; +def: Pat<(int_hexagon_M7_wcmpyrwc_rnd DoubleRegs:$src1, DoubleRegs:$src2), + (M7_wcmpyrwc_rnd DoubleRegs:$src1, DoubleRegs:$src2)>, Requires<[HasV67]>; + +// V68 Scalar Instructions. + +def: Pat<(int_hexagon_Y6_dmlink IntRegs:$src1, IntRegs:$src2), + (Y6_dmlink IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV68]>; +def: Pat<(int_hexagon_Y6_dmpause ), + (Y6_dmpause )>, Requires<[HasV68]>; +def: Pat<(int_hexagon_Y6_dmpoll ), + (Y6_dmpoll )>, Requires<[HasV68]>; +def: Pat<(int_hexagon_Y6_dmresume IntRegs:$src1), + (Y6_dmresume IntRegs:$src1)>, Requires<[HasV68]>; +def: Pat<(int_hexagon_Y6_dmstart IntRegs:$src1), + (Y6_dmstart IntRegs:$src1)>, Requires<[HasV68]>; +def: Pat<(int_hexagon_Y6_dmwait ), + (Y6_dmwait )>, Requires<[HasV68]>; // V60 HVX Instructions. -def: Pat<(int_hexagon_V6_vS32b_qpred_ai HvxQR:$src1, IntRegs:$src2, HvxVR:$src3), - (V6_vS32b_qpred_ai HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vS32b_qpred_ai_128B HvxQR:$src1, IntRegs:$src2, HvxVR:$src3), - (V6_vS32b_qpred_ai HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_extractw HvxVR:$src1, IntRegs:$src2), + (V6_extractw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_extractw_128B HvxVR:$src1, IntRegs:$src2), + (V6_extractw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_hi HvxWR:$src1), + (V6_hi HvxWR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_hi_128B HvxWR:$src1), + (V6_hi HvxWR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_lo HvxWR:$src1), + (V6_lo HvxWR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_lo_128B HvxWR:$src1), + (V6_lo HvxWR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_lvsplatw IntRegs:$src1), + (V6_lvsplatw IntRegs:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_lvsplatw_128B IntRegs:$src1), + (V6_lvsplatw IntRegs:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_pred_and HvxQR:$src1, HvxQR:$src2), + (V6_pred_and HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_pred_and_128B HvxQR:$src1, HvxQR:$src2), + (V6_pred_and HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_pred_and_n HvxQR:$src1, HvxQR:$src2), + (V6_pred_and_n HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_pred_and_n_128B HvxQR:$src1, HvxQR:$src2), + (V6_pred_and_n HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_pred_not HvxQR:$src1), + (V6_pred_not HvxQR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_pred_not_128B HvxQR:$src1), + (V6_pred_not HvxQR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_pred_or HvxQR:$src1, HvxQR:$src2), + (V6_pred_or HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_pred_or_128B HvxQR:$src1, HvxQR:$src2), + (V6_pred_or HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_pred_or_n HvxQR:$src1, HvxQR:$src2), + (V6_pred_or_n HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_pred_or_n_128B HvxQR:$src1, HvxQR:$src2), + (V6_pred_or_n HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_pred_scalar2 IntRegs:$src1), + (V6_pred_scalar2 IntRegs:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_pred_scalar2_128B IntRegs:$src1), + (V6_pred_scalar2 IntRegs:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_pred_xor HvxQR:$src1, HvxQR:$src2), + (V6_pred_xor HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_pred_xor_128B HvxQR:$src1, HvxQR:$src2), + (V6_pred_xor HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_vS32b_nqpred_ai HvxQR:$src1, IntRegs:$src2, HvxVR:$src3), (V6_vS32b_nqpred_ai HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vS32b_nqpred_ai_128B HvxQR:$src1, IntRegs:$src2, HvxVR:$src3), (V6_vS32b_nqpred_ai HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vS32b_nt_qpred_ai HvxQR:$src1, IntRegs:$src2, HvxVR:$src3), - (V6_vS32b_nt_qpred_ai HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vS32b_nt_qpred_ai_128B HvxQR:$src1, IntRegs:$src2, HvxVR:$src3), - (V6_vS32b_nt_qpred_ai HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_vS32b_nt_nqpred_ai HvxQR:$src1, IntRegs:$src2, HvxVR:$src3), (V6_vS32b_nt_nqpred_ai HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vS32b_nt_nqpred_ai_128B HvxQR:$src1, IntRegs:$src2, HvxVR:$src3), (V6_vS32b_nt_nqpred_ai HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vS32b_nt_qpred_ai HvxQR:$src1, IntRegs:$src2, HvxVR:$src3), + (V6_vS32b_nt_qpred_ai HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vS32b_nt_qpred_ai_128B HvxQR:$src1, IntRegs:$src2, HvxVR:$src3), + (V6_vS32b_nt_qpred_ai HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vS32b_qpred_ai HvxQR:$src1, IntRegs:$src2, HvxVR:$src3), + (V6_vS32b_qpred_ai HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vS32b_qpred_ai_128B HvxQR:$src1, IntRegs:$src2, HvxVR:$src3), + (V6_vS32b_qpred_ai HvxQR:$src1, IntRegs:$src2, 0, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vabsdiffh HvxVR:$src1, HvxVR:$src2), + (V6_vabsdiffh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vabsdiffh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vabsdiffh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vabsdiffub HvxVR:$src1, HvxVR:$src2), + (V6_vabsdiffub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vabsdiffub_128B HvxVR:$src1, HvxVR:$src2), + (V6_vabsdiffub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vabsdiffuh HvxVR:$src1, HvxVR:$src2), + (V6_vabsdiffuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vabsdiffuh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vabsdiffuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vabsdiffw HvxVR:$src1, HvxVR:$src2), + (V6_vabsdiffw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vabsdiffw_128B HvxVR:$src1, HvxVR:$src2), + (V6_vabsdiffw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vabsh HvxVR:$src1), + (V6_vabsh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vabsh_128B HvxVR:$src1), + (V6_vabsh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vabsh_sat HvxVR:$src1), + (V6_vabsh_sat HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vabsh_sat_128B HvxVR:$src1), + (V6_vabsh_sat HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vabsw HvxVR:$src1), + (V6_vabsw HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vabsw_128B HvxVR:$src1), + (V6_vabsw HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vabsw_sat HvxVR:$src1), + (V6_vabsw_sat HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vabsw_sat_128B HvxVR:$src1), + (V6_vabsw_sat HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddb HvxVR:$src1, HvxVR:$src2), + (V6_vaddb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddb_128B HvxVR:$src1, HvxVR:$src2), + (V6_vaddb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddb_dv HvxWR:$src1, HvxWR:$src2), + (V6_vaddb_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddb_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vaddb_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddbnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vaddbnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddbnq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vaddbnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vaddbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddbq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vaddbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddh HvxVR:$src1, HvxVR:$src2), + (V6_vaddh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vaddh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddh_dv HvxWR:$src1, HvxWR:$src2), + (V6_vaddh_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddh_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vaddh_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddhnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vaddhnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddhnq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vaddhnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddhq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vaddhq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddhq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vaddhq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddhsat HvxVR:$src1, HvxVR:$src2), + (V6_vaddhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddhsat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vaddhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddhsat_dv HvxWR:$src1, HvxWR:$src2), + (V6_vaddhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddhsat_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vaddhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddhw HvxVR:$src1, HvxVR:$src2), + (V6_vaddhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddhw_128B HvxVR:$src1, HvxVR:$src2), + (V6_vaddhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddubh HvxVR:$src1, HvxVR:$src2), + (V6_vaddubh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddubh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vaddubh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddubsat HvxVR:$src1, HvxVR:$src2), + (V6_vaddubsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddubsat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vaddubsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddubsat_dv HvxWR:$src1, HvxWR:$src2), + (V6_vaddubsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddubsat_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vaddubsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vadduhsat HvxVR:$src1, HvxVR:$src2), + (V6_vadduhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vadduhsat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vadduhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vadduhsat_dv HvxWR:$src1, HvxWR:$src2), + (V6_vadduhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vadduhsat_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vadduhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vadduhw HvxVR:$src1, HvxVR:$src2), + (V6_vadduhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vadduhw_128B HvxVR:$src1, HvxVR:$src2), + (V6_vadduhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddw HvxVR:$src1, HvxVR:$src2), + (V6_vaddw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddw_128B HvxVR:$src1, HvxVR:$src2), + (V6_vaddw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddw_dv HvxWR:$src1, HvxWR:$src2), + (V6_vaddw_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddw_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vaddw_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddwnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vaddwnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddwnq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vaddwnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vaddwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddwq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vaddwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddwsat HvxVR:$src1, HvxVR:$src2), + (V6_vaddwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddwsat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vaddwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddwsat_dv HvxWR:$src1, HvxWR:$src2), + (V6_vaddwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddwsat_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vaddwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_valignb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_valignb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_valignb_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_valignb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vlalignb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vlalignb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vlalignb_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vlalignb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_valignbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3), (V6_valignbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_valignbi_128B HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3), (V6_valignbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vlalignbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3), - (V6_vlalignbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vlalignbi_128B HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3), - (V6_vlalignbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vror HvxVR:$src1, IntRegs:$src2), - (V6_vror HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vror_128B HvxVR:$src1, IntRegs:$src2), - (V6_vror HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vunpackub HvxVR:$src1), - (V6_vunpackub HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vunpackub_128B HvxVR:$src1), - (V6_vunpackub HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vunpackb HvxVR:$src1), - (V6_vunpackb HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vunpackb_128B HvxVR:$src1), - (V6_vunpackb HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vunpackuh HvxVR:$src1), - (V6_vunpackuh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vunpackuh_128B HvxVR:$src1), - (V6_vunpackuh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vunpackh HvxVR:$src1), - (V6_vunpackh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vunpackh_128B HvxVR:$src1), - (V6_vunpackh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vunpackob HvxWR:$src1, HvxVR:$src2), - (V6_vunpackob HvxWR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vunpackob_128B HvxWR:$src1, HvxVR:$src2), - (V6_vunpackob HvxWR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vunpackoh HvxWR:$src1, HvxVR:$src2), - (V6_vunpackoh HvxWR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vunpackoh_128B HvxWR:$src1, HvxVR:$src2), - (V6_vunpackoh HvxWR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vpackeb HvxVR:$src1, HvxVR:$src2), - (V6_vpackeb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vpackeb_128B HvxVR:$src1, HvxVR:$src2), - (V6_vpackeb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vpackeh HvxVR:$src1, HvxVR:$src2), - (V6_vpackeh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vpackeh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vpackeh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vpackob HvxVR:$src1, HvxVR:$src2), - (V6_vpackob HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vpackob_128B HvxVR:$src1, HvxVR:$src2), - (V6_vpackob HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vpackoh HvxVR:$src1, HvxVR:$src2), - (V6_vpackoh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vpackoh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vpackoh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vpackhub_sat HvxVR:$src1, HvxVR:$src2), - (V6_vpackhub_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vpackhub_sat_128B HvxVR:$src1, HvxVR:$src2), - (V6_vpackhub_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vpackhb_sat HvxVR:$src1, HvxVR:$src2), - (V6_vpackhb_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vpackhb_sat_128B HvxVR:$src1, HvxVR:$src2), - (V6_vpackhb_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vpackwuh_sat HvxVR:$src1, HvxVR:$src2), - (V6_vpackwuh_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vpackwuh_sat_128B HvxVR:$src1, HvxVR:$src2), - (V6_vpackwuh_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vpackwh_sat HvxVR:$src1, HvxVR:$src2), - (V6_vpackwh_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vpackwh_sat_128B HvxVR:$src1, HvxVR:$src2), - (V6_vpackwh_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vzb HvxVR:$src1), - (V6_vzb HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vzb_128B HvxVR:$src1), - (V6_vzb HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsb HvxVR:$src1), - (V6_vsb HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsb_128B HvxVR:$src1), - (V6_vsb HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vzh HvxVR:$src1), - (V6_vzh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vzh_128B HvxVR:$src1), - (V6_vzh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsh HvxVR:$src1), - (V6_vsh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsh_128B HvxVR:$src1), - (V6_vsh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vand HvxVR:$src1, HvxVR:$src2), + (V6_vand HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vand_128B HvxVR:$src1, HvxVR:$src2), + (V6_vand HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vandqrt HvxQR:$src1, IntRegs:$src2), + (V6_vandqrt HvxQR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vandqrt_128B HvxQR:$src1, IntRegs:$src2), + (V6_vandqrt HvxQR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vandqrt_acc HvxVR:$src1, HvxQR:$src2, IntRegs:$src3), + (V6_vandqrt_acc HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vandqrt_acc_128B HvxVR:$src1, HvxQR:$src2, IntRegs:$src3), + (V6_vandqrt_acc HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vandvrt HvxVR:$src1, IntRegs:$src2), + (V6_vandvrt HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vandvrt_128B HvxVR:$src1, IntRegs:$src2), + (V6_vandvrt HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vandvrt_acc HvxQR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vandvrt_acc HvxQR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vandvrt_acc_128B HvxQR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vandvrt_acc HvxQR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaslh HvxVR:$src1, IntRegs:$src2), + (V6_vaslh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaslh_128B HvxVR:$src1, IntRegs:$src2), + (V6_vaslh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaslhv HvxVR:$src1, HvxVR:$src2), + (V6_vaslhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaslhv_128B HvxVR:$src1, HvxVR:$src2), + (V6_vaslhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaslw HvxVR:$src1, IntRegs:$src2), + (V6_vaslw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaslw_128B HvxVR:$src1, IntRegs:$src2), + (V6_vaslw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaslw_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vaslw_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaslw_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vaslw_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaslwv HvxVR:$src1, HvxVR:$src2), + (V6_vaslwv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaslwv_128B HvxVR:$src1, HvxVR:$src2), + (V6_vaslwv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasrh HvxVR:$src1, IntRegs:$src2), + (V6_vasrh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasrh_128B HvxVR:$src1, IntRegs:$src2), + (V6_vasrh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasrhbrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrhbrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasrhbrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrhbrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasrhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasrhubrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasrhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasrhubsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasrhv HvxVR:$src1, HvxVR:$src2), + (V6_vasrhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasrhv_128B HvxVR:$src1, HvxVR:$src2), + (V6_vasrhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasrw HvxVR:$src1, IntRegs:$src2), + (V6_vasrw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasrw_128B HvxVR:$src1, IntRegs:$src2), + (V6_vasrw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasrw_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vasrw_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasrw_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vasrw_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasrwh HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrwh HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasrwh_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrwh HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasrwhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrwhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasrwhrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrwhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasrwhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrwhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasrwhsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrwhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasrwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasrwuhsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasrwv HvxVR:$src1, HvxVR:$src2), + (V6_vasrwv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasrwv_128B HvxVR:$src1, HvxVR:$src2), + (V6_vasrwv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vassign HvxVR:$src1), + (V6_vassign HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vassign_128B HvxVR:$src1), + (V6_vassign HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vassignp HvxWR:$src1), + (V6_vassignp HvxWR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vassignp_128B HvxWR:$src1), + (V6_vassignp HvxWR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vavgh HvxVR:$src1, HvxVR:$src2), + (V6_vavgh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vavgh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vavgh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vavghrnd HvxVR:$src1, HvxVR:$src2), + (V6_vavghrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vavghrnd_128B HvxVR:$src1, HvxVR:$src2), + (V6_vavghrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vavgub HvxVR:$src1, HvxVR:$src2), + (V6_vavgub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vavgub_128B HvxVR:$src1, HvxVR:$src2), + (V6_vavgub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vavgubrnd HvxVR:$src1, HvxVR:$src2), + (V6_vavgubrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vavgubrnd_128B HvxVR:$src1, HvxVR:$src2), + (V6_vavgubrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vavguh HvxVR:$src1, HvxVR:$src2), + (V6_vavguh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vavguh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vavguh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vavguhrnd HvxVR:$src1, HvxVR:$src2), + (V6_vavguhrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vavguhrnd_128B HvxVR:$src1, HvxVR:$src2), + (V6_vavguhrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vavgw HvxVR:$src1, HvxVR:$src2), + (V6_vavgw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vavgw_128B HvxVR:$src1, HvxVR:$src2), + (V6_vavgw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vavgwrnd HvxVR:$src1, HvxVR:$src2), + (V6_vavgwrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vavgwrnd_128B HvxVR:$src1, HvxVR:$src2), + (V6_vavgwrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vcl0h HvxVR:$src1), + (V6_vcl0h HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vcl0h_128B HvxVR:$src1), + (V6_vcl0h HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vcl0w HvxVR:$src1), + (V6_vcl0w HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vcl0w_128B HvxVR:$src1), + (V6_vcl0w HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vcombine HvxVR:$src1, HvxVR:$src2), + (V6_vcombine HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vcombine_128B HvxVR:$src1, HvxVR:$src2), + (V6_vcombine HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vd0 ), + (V6_vd0 )>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vd0_128B ), + (V6_vd0 )>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdealb HvxVR:$src1), + (V6_vdealb HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdealb_128B HvxVR:$src1), + (V6_vdealb HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdealb4w HvxVR:$src1, HvxVR:$src2), + (V6_vdealb4w HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdealb4w_128B HvxVR:$src1, HvxVR:$src2), + (V6_vdealb4w HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdealh HvxVR:$src1), + (V6_vdealh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdealh_128B HvxVR:$src1), + (V6_vdealh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdealvdd HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vdealvdd HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdealvdd_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vdealvdd HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdelta HvxVR:$src1, HvxVR:$src2), + (V6_vdelta HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdelta_128B HvxVR:$src1, HvxVR:$src2), + (V6_vdelta HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_vdmpybus HvxVR:$src1, IntRegs:$src2), (V6_vdmpybus HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vdmpybus_128B HvxVR:$src1, IntRegs:$src2), @@ -1927,22 +2192,6 @@ def: Pat<(int_hexagon_V6_vdmpyhb_dv_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3) (V6_vdmpyhb_dv_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vdmpyhb_dv_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), (V6_vdmpyhb_dv_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vdmpyhvsat HvxVR:$src1, HvxVR:$src2), - (V6_vdmpyhvsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vdmpyhvsat_128B HvxVR:$src1, HvxVR:$src2), - (V6_vdmpyhvsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vdmpyhvsat_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vdmpyhvsat_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vdmpyhvsat_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vdmpyhvsat_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vdmpyhsat HvxVR:$src1, IntRegs:$src2), - (V6_vdmpyhsat HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vdmpyhsat_128B HvxVR:$src1, IntRegs:$src2), - (V6_vdmpyhsat HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vdmpyhsat_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vdmpyhsat_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vdmpyhsat_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vdmpyhsat_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_vdmpyhisat HvxWR:$src1, IntRegs:$src2), (V6_vdmpyhisat HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vdmpyhisat_128B HvxWR:$src1, IntRegs:$src2), @@ -1951,14 +2200,14 @@ def: Pat<(int_hexagon_V6_vdmpyhisat_acc HvxVR:$src1, HvxWR:$src2, IntRegs:$src3) (V6_vdmpyhisat_acc HvxVR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vdmpyhisat_acc_128B HvxVR:$src1, HvxWR:$src2, IntRegs:$src3), (V6_vdmpyhisat_acc HvxVR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vdmpyhsusat HvxVR:$src1, IntRegs:$src2), - (V6_vdmpyhsusat HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vdmpyhsusat_128B HvxVR:$src1, IntRegs:$src2), - (V6_vdmpyhsusat HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vdmpyhsusat_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vdmpyhsusat_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vdmpyhsusat_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vdmpyhsusat_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdmpyhsat HvxVR:$src1, IntRegs:$src2), + (V6_vdmpyhsat HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdmpyhsat_128B HvxVR:$src1, IntRegs:$src2), + (V6_vdmpyhsat HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdmpyhsat_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vdmpyhsat_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdmpyhsat_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vdmpyhsat_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_vdmpyhsuisat HvxWR:$src1, IntRegs:$src2), (V6_vdmpyhsuisat HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vdmpyhsuisat_128B HvxWR:$src1, IntRegs:$src2), @@ -1967,62 +2216,510 @@ def: Pat<(int_hexagon_V6_vdmpyhsuisat_acc HvxVR:$src1, HvxWR:$src2, IntRegs:$src (V6_vdmpyhsuisat_acc HvxVR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vdmpyhsuisat_acc_128B HvxVR:$src1, HvxWR:$src2, IntRegs:$src3), (V6_vdmpyhsuisat_acc HvxVR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vtmpyb HvxWR:$src1, IntRegs:$src2), - (V6_vtmpyb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vtmpyb_128B HvxWR:$src1, IntRegs:$src2), - (V6_vtmpyb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vtmpyb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), - (V6_vtmpyb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vtmpyb_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), - (V6_vtmpyb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vtmpybus HvxWR:$src1, IntRegs:$src2), - (V6_vtmpybus HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vtmpybus_128B HvxWR:$src1, IntRegs:$src2), - (V6_vtmpybus HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vtmpybus_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), - (V6_vtmpybus_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vtmpybus_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), - (V6_vtmpybus_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vtmpyhb HvxWR:$src1, IntRegs:$src2), - (V6_vtmpyhb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vtmpyhb_128B HvxWR:$src1, IntRegs:$src2), - (V6_vtmpyhb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vtmpyhb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), - (V6_vtmpyhb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vtmpyhb_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), - (V6_vtmpyhb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vrmpyub HvxVR:$src1, IntRegs:$src2), - (V6_vrmpyub HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vrmpyub_128B HvxVR:$src1, IntRegs:$src2), - (V6_vrmpyub HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vrmpyub_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vrmpyub_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vrmpyub_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vrmpyub_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vrmpyubv HvxVR:$src1, HvxVR:$src2), - (V6_vrmpyubv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vrmpyubv_128B HvxVR:$src1, HvxVR:$src2), - (V6_vrmpyubv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vrmpyubv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vrmpyubv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vrmpyubv_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vrmpyubv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vrmpybv HvxVR:$src1, HvxVR:$src2), - (V6_vrmpybv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vrmpybv_128B HvxVR:$src1, HvxVR:$src2), - (V6_vrmpybv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vrmpybv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vrmpybv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vrmpybv_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vrmpybv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vrmpyubi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3), - (V6_vrmpyubi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vrmpyubi_128B HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3), - (V6_vrmpyubi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vrmpyubi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4), - (V6_vrmpyubi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vrmpyubi_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4), - (V6_vrmpyubi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdmpyhsusat HvxVR:$src1, IntRegs:$src2), + (V6_vdmpyhsusat HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdmpyhsusat_128B HvxVR:$src1, IntRegs:$src2), + (V6_vdmpyhsusat HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdmpyhsusat_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vdmpyhsusat_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdmpyhsusat_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vdmpyhsusat_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdmpyhvsat HvxVR:$src1, HvxVR:$src2), + (V6_vdmpyhvsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdmpyhvsat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vdmpyhvsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdmpyhvsat_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vdmpyhvsat_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdmpyhvsat_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vdmpyhvsat_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdsaduh HvxWR:$src1, IntRegs:$src2), + (V6_vdsaduh HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdsaduh_128B HvxWR:$src1, IntRegs:$src2), + (V6_vdsaduh HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdsaduh_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vdsaduh_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdsaduh_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vdsaduh_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_veqb HvxVR:$src1, HvxVR:$src2), + (V6_veqb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_veqb_128B HvxVR:$src1, HvxVR:$src2), + (V6_veqb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_veqb_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqb_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_veqb_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqb_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_veqb_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqb_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_veqb_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqb_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_veqb_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqb_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_veqb_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqb_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_veqh HvxVR:$src1, HvxVR:$src2), + (V6_veqh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_veqh_128B HvxVR:$src1, HvxVR:$src2), + (V6_veqh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_veqh_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqh_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_veqh_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqh_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_veqh_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqh_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_veqh_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqh_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_veqh_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqh_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_veqh_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqh_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_veqw HvxVR:$src1, HvxVR:$src2), + (V6_veqw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_veqw_128B HvxVR:$src1, HvxVR:$src2), + (V6_veqw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_veqw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_veqw_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_veqw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_veqw_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_veqw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_veqw_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_veqw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtb HvxVR:$src1, HvxVR:$src2), + (V6_vgtb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtb_128B HvxVR:$src1, HvxVR:$src2), + (V6_vgtb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtb_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtb_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtb_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtb_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtb_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtb_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtb_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtb_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtb_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtb_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtb_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtb_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgth HvxVR:$src1, HvxVR:$src2), + (V6_vgth HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgth_128B HvxVR:$src1, HvxVR:$src2), + (V6_vgth HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgth_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgth_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgth_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgth_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgth_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgth_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgth_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgth_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgth_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgth_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgth_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgth_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtub HvxVR:$src1, HvxVR:$src2), + (V6_vgtub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtub_128B HvxVR:$src1, HvxVR:$src2), + (V6_vgtub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtub_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtub_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtub_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtub_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtub_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtub_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtub_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtub_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtub_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtub_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtub_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtub_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtuh HvxVR:$src1, HvxVR:$src2), + (V6_vgtuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtuh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vgtuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtuh_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtuh_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtuh_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtuh_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtuh_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtuh_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtuh_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtuh_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtuh_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtuh_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtuh_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtuh_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtuw HvxVR:$src1, HvxVR:$src2), + (V6_vgtuw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtuw_128B HvxVR:$src1, HvxVR:$src2), + (V6_vgtuw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtuw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtuw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtuw_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtuw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtuw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtuw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtuw_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtuw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtuw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtuw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtuw_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtuw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtw HvxVR:$src1, HvxVR:$src2), + (V6_vgtw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtw_128B HvxVR:$src1, HvxVR:$src2), + (V6_vgtw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtw_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtw_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vgtw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vgtw_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vgtw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vinsertwr HvxVR:$src1, IntRegs:$src2), + (V6_vinsertwr HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vinsertwr_128B HvxVR:$src1, IntRegs:$src2), + (V6_vinsertwr HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlalignb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vlalignb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlalignb_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vlalignb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlalignbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3), + (V6_vlalignbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlalignbi_128B HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3), + (V6_vlalignbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlsrh HvxVR:$src1, IntRegs:$src2), + (V6_vlsrh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlsrh_128B HvxVR:$src1, IntRegs:$src2), + (V6_vlsrh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlsrhv HvxVR:$src1, HvxVR:$src2), + (V6_vlsrhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlsrhv_128B HvxVR:$src1, HvxVR:$src2), + (V6_vlsrhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlsrw HvxVR:$src1, IntRegs:$src2), + (V6_vlsrw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlsrw_128B HvxVR:$src1, IntRegs:$src2), + (V6_vlsrw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlsrwv HvxVR:$src1, HvxVR:$src2), + (V6_vlsrwv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlsrwv_128B HvxVR:$src1, HvxVR:$src2), + (V6_vlsrwv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlutvvb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vlutvvb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlutvvb_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vlutvvb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlutvvb_oracc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4), + (V6_vlutvvb_oracc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlutvvb_oracc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4), + (V6_vlutvvb_oracc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlutvwh HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vlutvwh HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlutvwh_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vlutvwh HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlutvwh_oracc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4), + (V6_vlutvwh_oracc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlutvwh_oracc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4), + (V6_vlutvwh_oracc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmaxh HvxVR:$src1, HvxVR:$src2), + (V6_vmaxh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmaxh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmaxh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmaxub HvxVR:$src1, HvxVR:$src2), + (V6_vmaxub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmaxub_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmaxub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmaxuh HvxVR:$src1, HvxVR:$src2), + (V6_vmaxuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmaxuh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmaxuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmaxw HvxVR:$src1, HvxVR:$src2), + (V6_vmaxw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmaxw_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmaxw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vminh HvxVR:$src1, HvxVR:$src2), + (V6_vminh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vminh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vminh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vminub HvxVR:$src1, HvxVR:$src2), + (V6_vminub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vminub_128B HvxVR:$src1, HvxVR:$src2), + (V6_vminub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vminuh HvxVR:$src1, HvxVR:$src2), + (V6_vminuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vminuh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vminuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vminw HvxVR:$src1, HvxVR:$src2), + (V6_vminw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vminw_128B HvxVR:$src1, HvxVR:$src2), + (V6_vminw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpabus HvxWR:$src1, IntRegs:$src2), + (V6_vmpabus HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpabus_128B HvxWR:$src1, IntRegs:$src2), + (V6_vmpabus HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpabus_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vmpabus_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpabus_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vmpabus_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpabusv HvxWR:$src1, HvxWR:$src2), + (V6_vmpabusv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpabusv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vmpabusv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpabuuv HvxWR:$src1, HvxWR:$src2), + (V6_vmpabuuv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpabuuv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vmpabuuv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpahb HvxWR:$src1, IntRegs:$src2), + (V6_vmpahb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpahb_128B HvxWR:$src1, IntRegs:$src2), + (V6_vmpahb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpahb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vmpahb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpahb_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vmpahb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpybus HvxVR:$src1, IntRegs:$src2), + (V6_vmpybus HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpybus_128B HvxVR:$src1, IntRegs:$src2), + (V6_vmpybus HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpybus_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpybus_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpybus_acc_128B HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpybus_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpybusv HvxVR:$src1, HvxVR:$src2), + (V6_vmpybusv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpybusv_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmpybusv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpybusv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpybusv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpybusv_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpybusv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpybv HvxVR:$src1, HvxVR:$src2), + (V6_vmpybv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpybv_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmpybv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpybv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpybv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpybv_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpybv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyewuh HvxVR:$src1, HvxVR:$src2), + (V6_vmpyewuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyewuh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmpyewuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyh HvxVR:$src1, IntRegs:$src2), + (V6_vmpyh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyh_128B HvxVR:$src1, IntRegs:$src2), + (V6_vmpyh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyhsat_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpyhsat_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyhsat_acc_128B HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpyhsat_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyhsrs HvxVR:$src1, IntRegs:$src2), + (V6_vmpyhsrs HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyhsrs_128B HvxVR:$src1, IntRegs:$src2), + (V6_vmpyhsrs HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyhss HvxVR:$src1, IntRegs:$src2), + (V6_vmpyhss HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyhss_128B HvxVR:$src1, IntRegs:$src2), + (V6_vmpyhss HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyhus HvxVR:$src1, HvxVR:$src2), + (V6_vmpyhus HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyhus_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmpyhus HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyhus_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyhus_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyhus_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyhus_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyhv HvxVR:$src1, HvxVR:$src2), + (V6_vmpyhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyhv_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmpyhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyhv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyhv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyhv_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyhv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyhvsrs HvxVR:$src1, HvxVR:$src2), + (V6_vmpyhvsrs HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyhvsrs_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmpyhvsrs HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyieoh HvxVR:$src1, HvxVR:$src2), + (V6_vmpyieoh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyieoh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmpyieoh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyiewh_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyiewh_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyiewh_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyiewh_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyiewuh HvxVR:$src1, HvxVR:$src2), + (V6_vmpyiewuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyiewuh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmpyiewuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyiewuh_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyiewuh_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyiewuh_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyiewuh_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyih HvxVR:$src1, HvxVR:$src2), + (V6_vmpyih HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyih_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmpyih HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyih_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyih_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyih_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyih_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyihb HvxVR:$src1, IntRegs:$src2), + (V6_vmpyihb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyihb_128B HvxVR:$src1, IntRegs:$src2), + (V6_vmpyihb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyihb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpyihb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyihb_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpyihb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyiowh HvxVR:$src1, HvxVR:$src2), + (V6_vmpyiowh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyiowh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmpyiowh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyiwb HvxVR:$src1, IntRegs:$src2), + (V6_vmpyiwb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyiwb_128B HvxVR:$src1, IntRegs:$src2), + (V6_vmpyiwb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyiwb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpyiwb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyiwb_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpyiwb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyiwh HvxVR:$src1, IntRegs:$src2), + (V6_vmpyiwh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyiwh_128B HvxVR:$src1, IntRegs:$src2), + (V6_vmpyiwh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyiwh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpyiwh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyiwh_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpyiwh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyowh HvxVR:$src1, HvxVR:$src2), + (V6_vmpyowh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyowh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmpyowh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyowh_rnd HvxVR:$src1, HvxVR:$src2), + (V6_vmpyowh_rnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyowh_rnd_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmpyowh_rnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyowh_rnd_sacc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyowh_rnd_sacc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyowh_rnd_sacc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyowh_rnd_sacc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyowh_sacc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyowh_sacc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyowh_sacc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyowh_sacc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyub HvxVR:$src1, IntRegs:$src2), + (V6_vmpyub HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyub_128B HvxVR:$src1, IntRegs:$src2), + (V6_vmpyub HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyub_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpyub_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyub_acc_128B HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpyub_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyubv HvxVR:$src1, HvxVR:$src2), + (V6_vmpyubv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyubv_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmpyubv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyubv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyubv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyubv_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyubv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyuh HvxVR:$src1, IntRegs:$src2), + (V6_vmpyuh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyuh_128B HvxVR:$src1, IntRegs:$src2), + (V6_vmpyuh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyuh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpyuh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyuh_acc_128B HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpyuh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyuhv HvxVR:$src1, HvxVR:$src2), + (V6_vmpyuhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyuhv_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmpyuhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyuhv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyuhv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyuhv_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyuhv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmux HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmux HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmux_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmux HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vnavgh HvxVR:$src1, HvxVR:$src2), + (V6_vnavgh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vnavgh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vnavgh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vnavgub HvxVR:$src1, HvxVR:$src2), + (V6_vnavgub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vnavgub_128B HvxVR:$src1, HvxVR:$src2), + (V6_vnavgub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vnavgw HvxVR:$src1, HvxVR:$src2), + (V6_vnavgw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vnavgw_128B HvxVR:$src1, HvxVR:$src2), + (V6_vnavgw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vnormamth HvxVR:$src1), + (V6_vnormamth HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vnormamth_128B HvxVR:$src1), + (V6_vnormamth HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vnormamtw HvxVR:$src1), + (V6_vnormamtw HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vnormamtw_128B HvxVR:$src1), + (V6_vnormamtw HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vnot HvxVR:$src1), + (V6_vnot HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vnot_128B HvxVR:$src1), + (V6_vnot HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vor HvxVR:$src1, HvxVR:$src2), + (V6_vor HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vor_128B HvxVR:$src1, HvxVR:$src2), + (V6_vor HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vpackeb HvxVR:$src1, HvxVR:$src2), + (V6_vpackeb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vpackeb_128B HvxVR:$src1, HvxVR:$src2), + (V6_vpackeb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vpackeh HvxVR:$src1, HvxVR:$src2), + (V6_vpackeh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vpackeh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vpackeh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vpackhb_sat HvxVR:$src1, HvxVR:$src2), + (V6_vpackhb_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vpackhb_sat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vpackhb_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vpackhub_sat HvxVR:$src1, HvxVR:$src2), + (V6_vpackhub_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vpackhub_sat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vpackhub_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vpackob HvxVR:$src1, HvxVR:$src2), + (V6_vpackob HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vpackob_128B HvxVR:$src1, HvxVR:$src2), + (V6_vpackob HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vpackoh HvxVR:$src1, HvxVR:$src2), + (V6_vpackoh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vpackoh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vpackoh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vpackwh_sat HvxVR:$src1, HvxVR:$src2), + (V6_vpackwh_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vpackwh_sat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vpackwh_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vpackwuh_sat HvxVR:$src1, HvxVR:$src2), + (V6_vpackwuh_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vpackwuh_sat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vpackwuh_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vpopcounth HvxVR:$src1), + (V6_vpopcounth HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vpopcounth_128B HvxVR:$src1), + (V6_vpopcounth HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrdelta HvxVR:$src1, HvxVR:$src2), + (V6_vrdelta HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrdelta_128B HvxVR:$src1, HvxVR:$src2), + (V6_vrdelta HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_vrmpybus HvxVR:$src1, IntRegs:$src2), (V6_vrmpybus HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vrmpybus_128B HvxVR:$src1, IntRegs:$src2), @@ -2047,106 +2744,42 @@ def: Pat<(int_hexagon_V6_vrmpybusv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), (V6_vrmpybusv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vrmpybusv_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), (V6_vrmpybusv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vdsaduh HvxWR:$src1, IntRegs:$src2), - (V6_vdsaduh HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vdsaduh_128B HvxWR:$src1, IntRegs:$src2), - (V6_vdsaduh HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vdsaduh_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), - (V6_vdsaduh_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vdsaduh_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), - (V6_vdsaduh_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vrsadubi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3), - (V6_vrsadubi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vrsadubi_128B HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3), - (V6_vrsadubi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vrsadubi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4), - (V6_vrsadubi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vrsadubi_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4), - (V6_vrsadubi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vasrw HvxVR:$src1, IntRegs:$src2), - (V6_vasrw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vasrw_128B HvxVR:$src1, IntRegs:$src2), - (V6_vasrw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaslw HvxVR:$src1, IntRegs:$src2), - (V6_vaslw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaslw_128B HvxVR:$src1, IntRegs:$src2), - (V6_vaslw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vlsrw HvxVR:$src1, IntRegs:$src2), - (V6_vlsrw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vlsrw_128B HvxVR:$src1, IntRegs:$src2), - (V6_vlsrw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vasrwv HvxVR:$src1, HvxVR:$src2), - (V6_vasrwv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vasrwv_128B HvxVR:$src1, HvxVR:$src2), - (V6_vasrwv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaslwv HvxVR:$src1, HvxVR:$src2), - (V6_vaslwv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaslwv_128B HvxVR:$src1, HvxVR:$src2), - (V6_vaslwv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vlsrwv HvxVR:$src1, HvxVR:$src2), - (V6_vlsrwv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vlsrwv_128B HvxVR:$src1, HvxVR:$src2), - (V6_vlsrwv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vasrh HvxVR:$src1, IntRegs:$src2), - (V6_vasrh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vasrh_128B HvxVR:$src1, IntRegs:$src2), - (V6_vasrh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaslh HvxVR:$src1, IntRegs:$src2), - (V6_vaslh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaslh_128B HvxVR:$src1, IntRegs:$src2), - (V6_vaslh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vlsrh HvxVR:$src1, IntRegs:$src2), - (V6_vlsrh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vlsrh_128B HvxVR:$src1, IntRegs:$src2), - (V6_vlsrh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vasrhv HvxVR:$src1, HvxVR:$src2), - (V6_vasrhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vasrhv_128B HvxVR:$src1, HvxVR:$src2), - (V6_vasrhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaslhv HvxVR:$src1, HvxVR:$src2), - (V6_vaslhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaslhv_128B HvxVR:$src1, HvxVR:$src2), - (V6_vaslhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vlsrhv HvxVR:$src1, HvxVR:$src2), - (V6_vlsrhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vlsrhv_128B HvxVR:$src1, HvxVR:$src2), - (V6_vlsrhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vasrwh HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasrwh HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vasrwh_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasrwh HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vasrwhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasrwhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vasrwhsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasrwhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vasrwhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasrwhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vasrwhrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasrwhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vasrwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasrwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vasrwuhsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasrwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vroundwh HvxVR:$src1, HvxVR:$src2), - (V6_vroundwh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vroundwh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vroundwh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vroundwuh HvxVR:$src1, HvxVR:$src2), - (V6_vroundwuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vroundwuh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vroundwuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vasrhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasrhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vasrhubsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasrhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vasrhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasrhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vasrhubrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasrhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vasrhbrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasrhbrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vasrhbrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasrhbrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrmpybv HvxVR:$src1, HvxVR:$src2), + (V6_vrmpybv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrmpybv_128B HvxVR:$src1, HvxVR:$src2), + (V6_vrmpybv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrmpybv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vrmpybv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrmpybv_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vrmpybv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrmpyub HvxVR:$src1, IntRegs:$src2), + (V6_vrmpyub HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrmpyub_128B HvxVR:$src1, IntRegs:$src2), + (V6_vrmpyub HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrmpyub_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vrmpyub_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrmpyub_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vrmpyub_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrmpyubi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3), + (V6_vrmpyubi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrmpyubi_128B HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3), + (V6_vrmpyubi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrmpyubi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4), + (V6_vrmpyubi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrmpyubi_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4), + (V6_vrmpyubi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrmpyubv HvxVR:$src1, HvxVR:$src2), + (V6_vrmpyubv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrmpyubv_128B HvxVR:$src1, HvxVR:$src2), + (V6_vrmpyubv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrmpyubv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vrmpyubv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrmpyubv_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vrmpyubv_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vror HvxVR:$src1, IntRegs:$src2), + (V6_vror HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vror_128B HvxVR:$src1, IntRegs:$src2), + (V6_vror HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_vroundhb HvxVR:$src1, HvxVR:$src2), (V6_vroundhb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vroundhb_128B HvxVR:$src1, HvxVR:$src2), @@ -2155,710 +2788,22 @@ def: Pat<(int_hexagon_V6_vroundhub HvxVR:$src1, HvxVR:$src2), (V6_vroundhub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vroundhub_128B HvxVR:$src1, HvxVR:$src2), (V6_vroundhub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaslw_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vaslw_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaslw_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vaslw_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vasrw_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vasrw_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vasrw_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vasrw_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddb HvxVR:$src1, HvxVR:$src2), - (V6_vaddb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddb_128B HvxVR:$src1, HvxVR:$src2), - (V6_vaddb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubb HvxVR:$src1, HvxVR:$src2), - (V6_vsubb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubb_128B HvxVR:$src1, HvxVR:$src2), - (V6_vsubb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddb_dv HvxWR:$src1, HvxWR:$src2), - (V6_vaddb_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddb_dv_128B HvxWR:$src1, HvxWR:$src2), - (V6_vaddb_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubb_dv HvxWR:$src1, HvxWR:$src2), - (V6_vsubb_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubb_dv_128B HvxWR:$src1, HvxWR:$src2), - (V6_vsubb_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddh HvxVR:$src1, HvxVR:$src2), - (V6_vaddh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vaddh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubh HvxVR:$src1, HvxVR:$src2), - (V6_vsubh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vsubh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddh_dv HvxWR:$src1, HvxWR:$src2), - (V6_vaddh_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddh_dv_128B HvxWR:$src1, HvxWR:$src2), - (V6_vaddh_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubh_dv HvxWR:$src1, HvxWR:$src2), - (V6_vsubh_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubh_dv_128B HvxWR:$src1, HvxWR:$src2), - (V6_vsubh_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddw HvxVR:$src1, HvxVR:$src2), - (V6_vaddw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddw_128B HvxVR:$src1, HvxVR:$src2), - (V6_vaddw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubw HvxVR:$src1, HvxVR:$src2), - (V6_vsubw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubw_128B HvxVR:$src1, HvxVR:$src2), - (V6_vsubw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddw_dv HvxWR:$src1, HvxWR:$src2), - (V6_vaddw_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddw_dv_128B HvxWR:$src1, HvxWR:$src2), - (V6_vaddw_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubw_dv HvxWR:$src1, HvxWR:$src2), - (V6_vsubw_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubw_dv_128B HvxWR:$src1, HvxWR:$src2), - (V6_vsubw_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddubsat HvxVR:$src1, HvxVR:$src2), - (V6_vaddubsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddubsat_128B HvxVR:$src1, HvxVR:$src2), - (V6_vaddubsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddubsat_dv HvxWR:$src1, HvxWR:$src2), - (V6_vaddubsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddubsat_dv_128B HvxWR:$src1, HvxWR:$src2), - (V6_vaddubsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsububsat HvxVR:$src1, HvxVR:$src2), - (V6_vsububsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsububsat_128B HvxVR:$src1, HvxVR:$src2), - (V6_vsububsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsububsat_dv HvxWR:$src1, HvxWR:$src2), - (V6_vsububsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsububsat_dv_128B HvxWR:$src1, HvxWR:$src2), - (V6_vsububsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vadduhsat HvxVR:$src1, HvxVR:$src2), - (V6_vadduhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vadduhsat_128B HvxVR:$src1, HvxVR:$src2), - (V6_vadduhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vadduhsat_dv HvxWR:$src1, HvxWR:$src2), - (V6_vadduhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vadduhsat_dv_128B HvxWR:$src1, HvxWR:$src2), - (V6_vadduhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubuhsat HvxVR:$src1, HvxVR:$src2), - (V6_vsubuhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubuhsat_128B HvxVR:$src1, HvxVR:$src2), - (V6_vsubuhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubuhsat_dv HvxWR:$src1, HvxWR:$src2), - (V6_vsubuhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubuhsat_dv_128B HvxWR:$src1, HvxWR:$src2), - (V6_vsubuhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddhsat HvxVR:$src1, HvxVR:$src2), - (V6_vaddhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddhsat_128B HvxVR:$src1, HvxVR:$src2), - (V6_vaddhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddhsat_dv HvxWR:$src1, HvxWR:$src2), - (V6_vaddhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddhsat_dv_128B HvxWR:$src1, HvxWR:$src2), - (V6_vaddhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubhsat HvxVR:$src1, HvxVR:$src2), - (V6_vsubhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubhsat_128B HvxVR:$src1, HvxVR:$src2), - (V6_vsubhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubhsat_dv HvxWR:$src1, HvxWR:$src2), - (V6_vsubhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubhsat_dv_128B HvxWR:$src1, HvxWR:$src2), - (V6_vsubhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddwsat HvxVR:$src1, HvxVR:$src2), - (V6_vaddwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddwsat_128B HvxVR:$src1, HvxVR:$src2), - (V6_vaddwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddwsat_dv HvxWR:$src1, HvxWR:$src2), - (V6_vaddwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddwsat_dv_128B HvxWR:$src1, HvxWR:$src2), - (V6_vaddwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubwsat HvxVR:$src1, HvxVR:$src2), - (V6_vsubwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubwsat_128B HvxVR:$src1, HvxVR:$src2), - (V6_vsubwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubwsat_dv HvxWR:$src1, HvxWR:$src2), - (V6_vsubwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubwsat_dv_128B HvxWR:$src1, HvxWR:$src2), - (V6_vsubwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vavgub HvxVR:$src1, HvxVR:$src2), - (V6_vavgub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vavgub_128B HvxVR:$src1, HvxVR:$src2), - (V6_vavgub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vavgubrnd HvxVR:$src1, HvxVR:$src2), - (V6_vavgubrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vavgubrnd_128B HvxVR:$src1, HvxVR:$src2), - (V6_vavgubrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vavguh HvxVR:$src1, HvxVR:$src2), - (V6_vavguh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vavguh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vavguh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vavguhrnd HvxVR:$src1, HvxVR:$src2), - (V6_vavguhrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vavguhrnd_128B HvxVR:$src1, HvxVR:$src2), - (V6_vavguhrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vavgh HvxVR:$src1, HvxVR:$src2), - (V6_vavgh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vavgh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vavgh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vavghrnd HvxVR:$src1, HvxVR:$src2), - (V6_vavghrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vavghrnd_128B HvxVR:$src1, HvxVR:$src2), - (V6_vavghrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vnavgh HvxVR:$src1, HvxVR:$src2), - (V6_vnavgh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vnavgh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vnavgh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vavgw HvxVR:$src1, HvxVR:$src2), - (V6_vavgw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vavgw_128B HvxVR:$src1, HvxVR:$src2), - (V6_vavgw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vavgwrnd HvxVR:$src1, HvxVR:$src2), - (V6_vavgwrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vavgwrnd_128B HvxVR:$src1, HvxVR:$src2), - (V6_vavgwrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vnavgw HvxVR:$src1, HvxVR:$src2), - (V6_vnavgw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vnavgw_128B HvxVR:$src1, HvxVR:$src2), - (V6_vnavgw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vabsdiffub HvxVR:$src1, HvxVR:$src2), - (V6_vabsdiffub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vabsdiffub_128B HvxVR:$src1, HvxVR:$src2), - (V6_vabsdiffub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vabsdiffuh HvxVR:$src1, HvxVR:$src2), - (V6_vabsdiffuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vabsdiffuh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vabsdiffuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vabsdiffh HvxVR:$src1, HvxVR:$src2), - (V6_vabsdiffh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vabsdiffh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vabsdiffh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vabsdiffw HvxVR:$src1, HvxVR:$src2), - (V6_vabsdiffw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vabsdiffw_128B HvxVR:$src1, HvxVR:$src2), - (V6_vabsdiffw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vnavgub HvxVR:$src1, HvxVR:$src2), - (V6_vnavgub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vnavgub_128B HvxVR:$src1, HvxVR:$src2), - (V6_vnavgub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddubh HvxVR:$src1, HvxVR:$src2), - (V6_vaddubh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddubh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vaddubh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsububh HvxVR:$src1, HvxVR:$src2), - (V6_vsububh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsububh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vsububh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddhw HvxVR:$src1, HvxVR:$src2), - (V6_vaddhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddhw_128B HvxVR:$src1, HvxVR:$src2), - (V6_vaddhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubhw HvxVR:$src1, HvxVR:$src2), - (V6_vsubhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubhw_128B HvxVR:$src1, HvxVR:$src2), - (V6_vsubhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vadduhw HvxVR:$src1, HvxVR:$src2), - (V6_vadduhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vadduhw_128B HvxVR:$src1, HvxVR:$src2), - (V6_vadduhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubuhw HvxVR:$src1, HvxVR:$src2), - (V6_vsubuhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubuhw_128B HvxVR:$src1, HvxVR:$src2), - (V6_vsubuhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vd0 ), - (V6_vd0 )>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vd0_128B ), - (V6_vd0 )>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vaddbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddbq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vaddbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vsubbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubbq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vsubbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddbnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vaddbnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddbnq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vaddbnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubbnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vsubbnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubbnq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vsubbnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddhq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vaddhq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddhq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vaddhq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubhq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vsubhq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubhq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vsubhq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddhnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vaddhnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddhnq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vaddhnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubhnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vsubhnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubhnq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vsubhnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vaddwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddwq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vaddwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vsubwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubwq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vsubwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddwnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vaddwnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddwnq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vaddwnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubwnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vsubwnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubwnq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vsubwnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vabsh HvxVR:$src1), - (V6_vabsh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vabsh_128B HvxVR:$src1), - (V6_vabsh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vabsh_sat HvxVR:$src1), - (V6_vabsh_sat HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vabsh_sat_128B HvxVR:$src1), - (V6_vabsh_sat HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vabsw HvxVR:$src1), - (V6_vabsw HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vabsw_128B HvxVR:$src1), - (V6_vabsw HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vabsw_sat HvxVR:$src1), - (V6_vabsw_sat HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vabsw_sat_128B HvxVR:$src1), - (V6_vabsw_sat HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpybv HvxVR:$src1, HvxVR:$src2), - (V6_vmpybv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpybv_128B HvxVR:$src1, HvxVR:$src2), - (V6_vmpybv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpybv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpybv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpybv_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpybv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyubv HvxVR:$src1, HvxVR:$src2), - (V6_vmpyubv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyubv_128B HvxVR:$src1, HvxVR:$src2), - (V6_vmpyubv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyubv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpyubv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyubv_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpyubv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpybusv HvxVR:$src1, HvxVR:$src2), - (V6_vmpybusv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpybusv_128B HvxVR:$src1, HvxVR:$src2), - (V6_vmpybusv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpybusv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpybusv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpybusv_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpybusv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpabusv HvxWR:$src1, HvxWR:$src2), - (V6_vmpabusv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpabusv_128B HvxWR:$src1, HvxWR:$src2), - (V6_vmpabusv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpabuuv HvxWR:$src1, HvxWR:$src2), - (V6_vmpabuuv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpabuuv_128B HvxWR:$src1, HvxWR:$src2), - (V6_vmpabuuv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyhv HvxVR:$src1, HvxVR:$src2), - (V6_vmpyhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyhv_128B HvxVR:$src1, HvxVR:$src2), - (V6_vmpyhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyhv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpyhv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyhv_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpyhv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyuhv HvxVR:$src1, HvxVR:$src2), - (V6_vmpyuhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyuhv_128B HvxVR:$src1, HvxVR:$src2), - (V6_vmpyuhv HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyuhv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpyuhv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyuhv_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpyuhv_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyhvsrs HvxVR:$src1, HvxVR:$src2), - (V6_vmpyhvsrs HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyhvsrs_128B HvxVR:$src1, HvxVR:$src2), - (V6_vmpyhvsrs HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyhus HvxVR:$src1, HvxVR:$src2), - (V6_vmpyhus HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyhus_128B HvxVR:$src1, HvxVR:$src2), - (V6_vmpyhus HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyhus_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpyhus_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyhus_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpyhus_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyih HvxVR:$src1, HvxVR:$src2), - (V6_vmpyih HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyih_128B HvxVR:$src1, HvxVR:$src2), - (V6_vmpyih HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyih_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpyih_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyih_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpyih_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyewuh HvxVR:$src1, HvxVR:$src2), - (V6_vmpyewuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyewuh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vmpyewuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyowh HvxVR:$src1, HvxVR:$src2), - (V6_vmpyowh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyowh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vmpyowh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyowh_rnd HvxVR:$src1, HvxVR:$src2), - (V6_vmpyowh_rnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyowh_rnd_128B HvxVR:$src1, HvxVR:$src2), - (V6_vmpyowh_rnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyowh_sacc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpyowh_sacc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyowh_sacc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpyowh_sacc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyowh_rnd_sacc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpyowh_rnd_sacc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyowh_rnd_sacc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpyowh_rnd_sacc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyieoh HvxVR:$src1, HvxVR:$src2), - (V6_vmpyieoh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyieoh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vmpyieoh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyiewuh HvxVR:$src1, HvxVR:$src2), - (V6_vmpyiewuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyiewuh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vmpyiewuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyiowh HvxVR:$src1, HvxVR:$src2), - (V6_vmpyiowh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyiowh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vmpyiowh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyiewh_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpyiewh_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyiewh_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpyiewh_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyiewuh_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpyiewuh_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyiewuh_acc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpyiewuh_acc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyub HvxVR:$src1, IntRegs:$src2), - (V6_vmpyub HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyub_128B HvxVR:$src1, IntRegs:$src2), - (V6_vmpyub HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyub_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vmpyub_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyub_acc_128B HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vmpyub_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpybus HvxVR:$src1, IntRegs:$src2), - (V6_vmpybus HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpybus_128B HvxVR:$src1, IntRegs:$src2), - (V6_vmpybus HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpybus_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vmpybus_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpybus_acc_128B HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vmpybus_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpabus HvxWR:$src1, IntRegs:$src2), - (V6_vmpabus HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpabus_128B HvxWR:$src1, IntRegs:$src2), - (V6_vmpabus HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpabus_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), - (V6_vmpabus_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpabus_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), - (V6_vmpabus_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpahb HvxWR:$src1, IntRegs:$src2), - (V6_vmpahb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpahb_128B HvxWR:$src1, IntRegs:$src2), - (V6_vmpahb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpahb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), - (V6_vmpahb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpahb_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), - (V6_vmpahb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyh HvxVR:$src1, IntRegs:$src2), - (V6_vmpyh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyh_128B HvxVR:$src1, IntRegs:$src2), - (V6_vmpyh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyhsat_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vmpyhsat_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyhsat_acc_128B HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vmpyhsat_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyhss HvxVR:$src1, IntRegs:$src2), - (V6_vmpyhss HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyhss_128B HvxVR:$src1, IntRegs:$src2), - (V6_vmpyhss HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyhsrs HvxVR:$src1, IntRegs:$src2), - (V6_vmpyhsrs HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyhsrs_128B HvxVR:$src1, IntRegs:$src2), - (V6_vmpyhsrs HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyuh HvxVR:$src1, IntRegs:$src2), - (V6_vmpyuh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyuh_128B HvxVR:$src1, IntRegs:$src2), - (V6_vmpyuh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyuh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vmpyuh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyuh_acc_128B HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vmpyuh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyihb HvxVR:$src1, IntRegs:$src2), - (V6_vmpyihb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyihb_128B HvxVR:$src1, IntRegs:$src2), - (V6_vmpyihb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyihb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vmpyihb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyihb_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vmpyihb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyiwb HvxVR:$src1, IntRegs:$src2), - (V6_vmpyiwb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyiwb_128B HvxVR:$src1, IntRegs:$src2), - (V6_vmpyiwb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyiwb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vmpyiwb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyiwb_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vmpyiwb_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyiwh HvxVR:$src1, IntRegs:$src2), - (V6_vmpyiwh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyiwh_128B HvxVR:$src1, IntRegs:$src2), - (V6_vmpyiwh HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyiwh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vmpyiwh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyiwh_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vmpyiwh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vand HvxVR:$src1, HvxVR:$src2), - (V6_vand HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vand_128B HvxVR:$src1, HvxVR:$src2), - (V6_vand HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vor HvxVR:$src1, HvxVR:$src2), - (V6_vor HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vor_128B HvxVR:$src1, HvxVR:$src2), - (V6_vor HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vxor HvxVR:$src1, HvxVR:$src2), - (V6_vxor HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vxor_128B HvxVR:$src1, HvxVR:$src2), - (V6_vxor HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vnot HvxVR:$src1), - (V6_vnot HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vnot_128B HvxVR:$src1), - (V6_vnot HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vandqrt HvxQR:$src1, IntRegs:$src2), - (V6_vandqrt HvxQR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vandqrt_128B HvxQR:$src1, IntRegs:$src2), - (V6_vandqrt HvxQR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vandqrt_acc HvxVR:$src1, HvxQR:$src2, IntRegs:$src3), - (V6_vandqrt_acc HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vandqrt_acc_128B HvxVR:$src1, HvxQR:$src2, IntRegs:$src3), - (V6_vandqrt_acc HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vandvrt HvxVR:$src1, IntRegs:$src2), - (V6_vandvrt HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vandvrt_128B HvxVR:$src1, IntRegs:$src2), - (V6_vandvrt HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vandvrt_acc HvxQR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vandvrt_acc HvxQR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vandvrt_acc_128B HvxQR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vandvrt_acc HvxQR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vgtw HvxVR:$src1, HvxVR:$src2), - (V6_vgtw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vgtw_128B HvxVR:$src1, HvxVR:$src2), - (V6_vgtw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vgtw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vgtw_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vgtw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vgtw_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vgtw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vgtw_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_veqw HvxVR:$src1, HvxVR:$src2), - (V6_veqw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_veqw_128B HvxVR:$src1, HvxVR:$src2), - (V6_veqw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_veqw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_veqw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_veqw_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_veqw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_veqw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_veqw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_veqw_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_veqw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_veqw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_veqw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_veqw_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_veqw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vgth HvxVR:$src1, HvxVR:$src2), - (V6_vgth HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vgth_128B HvxVR:$src1, HvxVR:$src2), - (V6_vgth HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vgth_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgth_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vgth_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgth_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vgth_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgth_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vgth_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgth_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vgth_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgth_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vgth_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgth_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_veqh HvxVR:$src1, HvxVR:$src2), - (V6_veqh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_veqh_128B HvxVR:$src1, HvxVR:$src2), - (V6_veqh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_veqh_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_veqh_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_veqh_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_veqh_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_veqh_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_veqh_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_veqh_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_veqh_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_veqh_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_veqh_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_veqh_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_veqh_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vgtb HvxVR:$src1, HvxVR:$src2), - (V6_vgtb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vgtb_128B HvxVR:$src1, HvxVR:$src2), - (V6_vgtb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vgtb_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtb_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vgtb_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtb_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vgtb_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtb_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vgtb_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtb_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vgtb_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtb_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vgtb_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtb_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_veqb HvxVR:$src1, HvxVR:$src2), - (V6_veqb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_veqb_128B HvxVR:$src1, HvxVR:$src2), - (V6_veqb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_veqb_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_veqb_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_veqb_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_veqb_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_veqb_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_veqb_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_veqb_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_veqb_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_veqb_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_veqb_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_veqb_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_veqb_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vgtuw HvxVR:$src1, HvxVR:$src2), - (V6_vgtuw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vgtuw_128B HvxVR:$src1, HvxVR:$src2), - (V6_vgtuw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vgtuw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtuw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vgtuw_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtuw_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vgtuw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtuw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vgtuw_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtuw_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vgtuw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtuw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vgtuw_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtuw_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vgtuh HvxVR:$src1, HvxVR:$src2), - (V6_vgtuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vgtuh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vgtuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vgtuh_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtuh_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vgtuh_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtuh_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vgtuh_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtuh_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vgtuh_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtuh_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vgtuh_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtuh_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vgtuh_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtuh_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vgtub HvxVR:$src1, HvxVR:$src2), - (V6_vgtub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vgtub_128B HvxVR:$src1, HvxVR:$src2), - (V6_vgtub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vgtub_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtub_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vgtub_and_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtub_and HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vgtub_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtub_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vgtub_or_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtub_or HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vgtub_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtub_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vgtub_xor_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vgtub_xor HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_pred_or HvxQR:$src1, HvxQR:$src2), - (V6_pred_or HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_pred_or_128B HvxQR:$src1, HvxQR:$src2), - (V6_pred_or HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_pred_and HvxQR:$src1, HvxQR:$src2), - (V6_pred_and HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_pred_and_128B HvxQR:$src1, HvxQR:$src2), - (V6_pred_and HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_pred_not HvxQR:$src1), - (V6_pred_not HvxQR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_pred_not_128B HvxQR:$src1), - (V6_pred_not HvxQR:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_pred_xor HvxQR:$src1, HvxQR:$src2), - (V6_pred_xor HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_pred_xor_128B HvxQR:$src1, HvxQR:$src2), - (V6_pred_xor HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_pred_and_n HvxQR:$src1, HvxQR:$src2), - (V6_pred_and_n HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_pred_and_n_128B HvxQR:$src1, HvxQR:$src2), - (V6_pred_and_n HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_pred_or_n HvxQR:$src1, HvxQR:$src2), - (V6_pred_or_n HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_pred_or_n_128B HvxQR:$src1, HvxQR:$src2), - (V6_pred_or_n HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_pred_scalar2 IntRegs:$src1), - (V6_pred_scalar2 IntRegs:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_pred_scalar2_128B IntRegs:$src1), - (V6_pred_scalar2 IntRegs:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmux HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmux HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmux_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmux HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vswap HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vswap HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vswap_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vswap HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmaxub HvxVR:$src1, HvxVR:$src2), - (V6_vmaxub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmaxub_128B HvxVR:$src1, HvxVR:$src2), - (V6_vmaxub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vminub HvxVR:$src1, HvxVR:$src2), - (V6_vminub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vminub_128B HvxVR:$src1, HvxVR:$src2), - (V6_vminub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmaxuh HvxVR:$src1, HvxVR:$src2), - (V6_vmaxuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmaxuh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vmaxuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vminuh HvxVR:$src1, HvxVR:$src2), - (V6_vminuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vminuh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vminuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmaxh HvxVR:$src1, HvxVR:$src2), - (V6_vmaxh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmaxh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vmaxh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vminh HvxVR:$src1, HvxVR:$src2), - (V6_vminh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vminh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vminh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmaxw HvxVR:$src1, HvxVR:$src2), - (V6_vmaxw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmaxw_128B HvxVR:$src1, HvxVR:$src2), - (V6_vmaxw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vminw HvxVR:$src1, HvxVR:$src2), - (V6_vminw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vminw_128B HvxVR:$src1, HvxVR:$src2), - (V6_vminw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vroundwh HvxVR:$src1, HvxVR:$src2), + (V6_vroundwh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vroundwh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vroundwh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vroundwuh HvxVR:$src1, HvxVR:$src2), + (V6_vroundwuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vroundwuh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vroundwuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrsadubi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3), + (V6_vrsadubi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrsadubi_128B HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3), + (V6_vrsadubi HvxWR:$src1, IntRegs:$src2, u1_0ImmPred_timm:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrsadubi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4), + (V6_vrsadubi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrsadubi_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4), + (V6_vrsadubi_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3, u1_0ImmPred_timm:$src4)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_vsathub HvxVR:$src1, HvxVR:$src2), (V6_vsathub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vsathub_128B HvxVR:$src1, HvxVR:$src2), @@ -2867,177 +2812,229 @@ def: Pat<(int_hexagon_V6_vsatwh HvxVR:$src1, HvxVR:$src2), (V6_vsatwh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vsatwh_128B HvxVR:$src1, HvxVR:$src2), (V6_vsatwh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vshuffeb HvxVR:$src1, HvxVR:$src2), - (V6_vshuffeb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vshuffeb_128B HvxVR:$src1, HvxVR:$src2), - (V6_vshuffeb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vshuffob HvxVR:$src1, HvxVR:$src2), - (V6_vshuffob HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vshuffob_128B HvxVR:$src1, HvxVR:$src2), - (V6_vshuffob HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsb HvxVR:$src1), + (V6_vsb HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsb_128B HvxVR:$src1), + (V6_vsb HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsh HvxVR:$src1), + (V6_vsh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsh_128B HvxVR:$src1), + (V6_vsh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_vshufeh HvxVR:$src1, HvxVR:$src2), (V6_vshufeh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vshufeh_128B HvxVR:$src1, HvxVR:$src2), (V6_vshufeh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vshufoh HvxVR:$src1, HvxVR:$src2), - (V6_vshufoh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vshufoh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vshufoh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vshuffvdd HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vshuffvdd HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vshuffvdd_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vshuffvdd HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vdealvdd HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vdealvdd HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vdealvdd_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vdealvdd HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vshufoeh HvxVR:$src1, HvxVR:$src2), - (V6_vshufoeh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vshufoeh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vshufoeh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vshufoeb HvxVR:$src1, HvxVR:$src2), - (V6_vshufoeb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vshufoeb_128B HvxVR:$src1, HvxVR:$src2), - (V6_vshufoeb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vdealh HvxVR:$src1), - (V6_vdealh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vdealh_128B HvxVR:$src1), - (V6_vdealh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vdealb HvxVR:$src1), - (V6_vdealb HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vdealb_128B HvxVR:$src1), - (V6_vdealb HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vdealb4w HvxVR:$src1, HvxVR:$src2), - (V6_vdealb4w HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vdealb4w_128B HvxVR:$src1, HvxVR:$src2), - (V6_vdealb4w HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vshuffh HvxVR:$src1), - (V6_vshuffh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vshuffh_128B HvxVR:$src1), - (V6_vshuffh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; def: Pat<(int_hexagon_V6_vshuffb HvxVR:$src1), (V6_vshuffb HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; def: Pat<(int_hexagon_V6_vshuffb_128B HvxVR:$src1), (V6_vshuffb HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_extractw HvxVR:$src1, IntRegs:$src2), - (V6_extractw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_extractw_128B HvxVR:$src1, IntRegs:$src2), - (V6_extractw HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vinsertwr HvxVR:$src1, IntRegs:$src2), - (V6_vinsertwr HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vinsertwr_128B HvxVR:$src1, IntRegs:$src2), - (V6_vinsertwr HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_lvsplatw IntRegs:$src1), - (V6_lvsplatw IntRegs:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_lvsplatw_128B IntRegs:$src1), - (V6_lvsplatw IntRegs:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vassignp HvxWR:$src1), - (V6_vassignp HvxWR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vassignp_128B HvxWR:$src1), - (V6_vassignp HvxWR:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vassign HvxVR:$src1), - (V6_vassign HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vassign_128B HvxVR:$src1), - (V6_vassign HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vcombine HvxVR:$src1, HvxVR:$src2), - (V6_vcombine HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vcombine_128B HvxVR:$src1, HvxVR:$src2), - (V6_vcombine HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vdelta HvxVR:$src1, HvxVR:$src2), - (V6_vdelta HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vdelta_128B HvxVR:$src1, HvxVR:$src2), - (V6_vdelta HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vrdelta HvxVR:$src1, HvxVR:$src2), - (V6_vrdelta HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vrdelta_128B HvxVR:$src1, HvxVR:$src2), - (V6_vrdelta HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vcl0w HvxVR:$src1), - (V6_vcl0w HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vcl0w_128B HvxVR:$src1), - (V6_vcl0w HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vcl0h HvxVR:$src1), - (V6_vcl0h HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vcl0h_128B HvxVR:$src1), - (V6_vcl0h HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vnormamtw HvxVR:$src1), - (V6_vnormamtw HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vnormamtw_128B HvxVR:$src1), - (V6_vnormamtw HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vnormamth HvxVR:$src1), - (V6_vnormamth HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vnormamth_128B HvxVR:$src1), - (V6_vnormamth HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vpopcounth HvxVR:$src1), - (V6_vpopcounth HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vpopcounth_128B HvxVR:$src1), - (V6_vpopcounth HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vlutvvb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vlutvvb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vlutvvb_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vlutvvb HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vlutvvb_oracc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4), - (V6_vlutvvb_oracc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vlutvvb_oracc_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4), - (V6_vlutvvb_oracc HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vlutvwh HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vlutvwh HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vlutvwh_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vlutvwh HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vlutvwh_oracc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4), - (V6_vlutvwh_oracc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vlutvwh_oracc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4), - (V6_vlutvwh_oracc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, IntRegsLow8:$src4)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_hi HvxWR:$src1), - (V6_hi HvxWR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_hi_128B HvxWR:$src1), - (V6_hi HvxWR:$src1)>, Requires<[HasV60, UseHVX128B]>; -def: Pat<(int_hexagon_V6_lo HvxWR:$src1), - (V6_lo HvxWR:$src1)>, Requires<[HasV60, UseHVX64B]>; -def: Pat<(int_hexagon_V6_lo_128B HvxWR:$src1), - (V6_lo HvxWR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vshuffeb HvxVR:$src1, HvxVR:$src2), + (V6_vshuffeb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vshuffeb_128B HvxVR:$src1, HvxVR:$src2), + (V6_vshuffeb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vshuffh HvxVR:$src1), + (V6_vshuffh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vshuffh_128B HvxVR:$src1), + (V6_vshuffh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vshuffob HvxVR:$src1, HvxVR:$src2), + (V6_vshuffob HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vshuffob_128B HvxVR:$src1, HvxVR:$src2), + (V6_vshuffob HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vshuffvdd HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vshuffvdd HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vshuffvdd_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vshuffvdd HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vshufoeb HvxVR:$src1, HvxVR:$src2), + (V6_vshufoeb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vshufoeb_128B HvxVR:$src1, HvxVR:$src2), + (V6_vshufoeb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vshufoeh HvxVR:$src1, HvxVR:$src2), + (V6_vshufoeh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vshufoeh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vshufoeh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vshufoh HvxVR:$src1, HvxVR:$src2), + (V6_vshufoh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vshufoh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vshufoh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubb HvxVR:$src1, HvxVR:$src2), + (V6_vsubb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubb_128B HvxVR:$src1, HvxVR:$src2), + (V6_vsubb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubb_dv HvxWR:$src1, HvxWR:$src2), + (V6_vsubb_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubb_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vsubb_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubbnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vsubbnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubbnq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vsubbnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vsubbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubbq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vsubbq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubh HvxVR:$src1, HvxVR:$src2), + (V6_vsubh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vsubh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubh_dv HvxWR:$src1, HvxWR:$src2), + (V6_vsubh_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubh_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vsubh_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubhnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vsubhnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubhnq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vsubhnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubhq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vsubhq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubhq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vsubhq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubhsat HvxVR:$src1, HvxVR:$src2), + (V6_vsubhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubhsat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vsubhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubhsat_dv HvxWR:$src1, HvxWR:$src2), + (V6_vsubhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubhsat_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vsubhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubhw HvxVR:$src1, HvxVR:$src2), + (V6_vsubhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubhw_128B HvxVR:$src1, HvxVR:$src2), + (V6_vsubhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsububh HvxVR:$src1, HvxVR:$src2), + (V6_vsububh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsububh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vsububh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsububsat HvxVR:$src1, HvxVR:$src2), + (V6_vsububsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsububsat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vsububsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsububsat_dv HvxWR:$src1, HvxWR:$src2), + (V6_vsububsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsububsat_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vsububsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubuhsat HvxVR:$src1, HvxVR:$src2), + (V6_vsubuhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubuhsat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vsubuhsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubuhsat_dv HvxWR:$src1, HvxWR:$src2), + (V6_vsubuhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubuhsat_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vsubuhsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubuhw HvxVR:$src1, HvxVR:$src2), + (V6_vsubuhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubuhw_128B HvxVR:$src1, HvxVR:$src2), + (V6_vsubuhw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubw HvxVR:$src1, HvxVR:$src2), + (V6_vsubw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubw_128B HvxVR:$src1, HvxVR:$src2), + (V6_vsubw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubw_dv HvxWR:$src1, HvxWR:$src2), + (V6_vsubw_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubw_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vsubw_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubwnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vsubwnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubwnq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vsubwnq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vsubwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubwq_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vsubwq HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubwsat HvxVR:$src1, HvxVR:$src2), + (V6_vsubwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubwsat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vsubwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubwsat_dv HvxWR:$src1, HvxWR:$src2), + (V6_vsubwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubwsat_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vsubwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vswap HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vswap HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vswap_128B HvxQR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vswap HvxQR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vtmpyb HvxWR:$src1, IntRegs:$src2), + (V6_vtmpyb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vtmpyb_128B HvxWR:$src1, IntRegs:$src2), + (V6_vtmpyb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vtmpyb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vtmpyb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vtmpyb_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vtmpyb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vtmpybus HvxWR:$src1, IntRegs:$src2), + (V6_vtmpybus HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vtmpybus_128B HvxWR:$src1, IntRegs:$src2), + (V6_vtmpybus HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vtmpybus_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vtmpybus_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vtmpybus_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vtmpybus_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vtmpyhb HvxWR:$src1, IntRegs:$src2), + (V6_vtmpyhb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vtmpyhb_128B HvxWR:$src1, IntRegs:$src2), + (V6_vtmpyhb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vtmpyhb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vtmpyhb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vtmpyhb_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vtmpyhb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vunpackb HvxVR:$src1), + (V6_vunpackb HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vunpackb_128B HvxVR:$src1), + (V6_vunpackb HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vunpackh HvxVR:$src1), + (V6_vunpackh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vunpackh_128B HvxVR:$src1), + (V6_vunpackh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vunpackob HvxWR:$src1, HvxVR:$src2), + (V6_vunpackob HvxWR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vunpackob_128B HvxWR:$src1, HvxVR:$src2), + (V6_vunpackob HvxWR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vunpackoh HvxWR:$src1, HvxVR:$src2), + (V6_vunpackoh HvxWR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vunpackoh_128B HvxWR:$src1, HvxVR:$src2), + (V6_vunpackoh HvxWR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vunpackub HvxVR:$src1), + (V6_vunpackub HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vunpackub_128B HvxVR:$src1), + (V6_vunpackub HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vunpackuh HvxVR:$src1), + (V6_vunpackuh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vunpackuh_128B HvxVR:$src1), + (V6_vunpackuh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vxor HvxVR:$src1, HvxVR:$src2), + (V6_vxor HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vxor_128B HvxVR:$src1, HvxVR:$src2), + (V6_vxor HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vzb HvxVR:$src1), + (V6_vzb HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vzb_128B HvxVR:$src1), + (V6_vzb HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vzh HvxVR:$src1), + (V6_vzh HvxVR:$src1)>, Requires<[HasV60, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vzh_128B HvxVR:$src1), + (V6_vzh HvxVR:$src1)>, Requires<[HasV60, UseHVX128B]>; // V62 HVX Instructions. -def: Pat<(int_hexagon_V6_vlsrb HvxVR:$src1, IntRegs:$src2), - (V6_vlsrb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vlsrb_128B HvxVR:$src1, IntRegs:$src2), - (V6_vlsrb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vasrwuhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasrwuhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vasrwuhrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasrwuhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vasruwuhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasruwuhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vasruwuhrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasruwuhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vasrhbsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasrhbsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vasrhbsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasrhbsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vrounduwuh HvxVR:$src1, HvxVR:$src2), - (V6_vrounduwuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vrounduwuh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vrounduwuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vrounduhub HvxVR:$src1, HvxVR:$src2), - (V6_vrounduhub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vrounduhub_128B HvxVR:$src1, HvxVR:$src2), - (V6_vrounduhub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vadduwsat HvxVR:$src1, HvxVR:$src2), - (V6_vadduwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vadduwsat_128B HvxVR:$src1, HvxVR:$src2), - (V6_vadduwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vadduwsat_dv HvxWR:$src1, HvxWR:$src2), - (V6_vadduwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vadduwsat_dv_128B HvxWR:$src1, HvxWR:$src2), - (V6_vadduwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubuwsat HvxVR:$src1, HvxVR:$src2), - (V6_vsubuwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubuwsat_128B HvxVR:$src1, HvxVR:$src2), - (V6_vsubuwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubuwsat_dv HvxWR:$src1, HvxWR:$src2), - (V6_vsubuwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubuwsat_dv_128B HvxWR:$src1, HvxWR:$src2), - (V6_vsubuwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_lvsplatb IntRegs:$src1), + (V6_lvsplatb IntRegs:$src1)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_lvsplatb_128B IntRegs:$src1), + (V6_lvsplatb IntRegs:$src1)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_lvsplath IntRegs:$src1), + (V6_lvsplath IntRegs:$src1)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_lvsplath_128B IntRegs:$src1), + (V6_lvsplath IntRegs:$src1)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_pred_scalar2v2 IntRegs:$src1), + (V6_pred_scalar2v2 IntRegs:$src1)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_pred_scalar2v2_128B IntRegs:$src1), + (V6_pred_scalar2v2 IntRegs:$src1)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_shuffeqh HvxQR:$src1, HvxQR:$src2), + (V6_shuffeqh HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_shuffeqh_128B HvxQR:$src1, HvxQR:$src2), + (V6_shuffeqh HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_shuffeqw HvxQR:$src1, HvxQR:$src2), + (V6_shuffeqw HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_shuffeqw_128B HvxQR:$src1, HvxQR:$src2), + (V6_shuffeqw HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV62, UseHVX128B]>; def: Pat<(int_hexagon_V6_vaddbsat HvxVR:$src1, HvxVR:$src2), (V6_vaddbsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; def: Pat<(int_hexagon_V6_vaddbsat_128B HvxVR:$src1, HvxVR:$src2), @@ -3046,66 +3043,42 @@ def: Pat<(int_hexagon_V6_vaddbsat_dv HvxWR:$src1, HvxWR:$src2), (V6_vaddbsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX64B]>; def: Pat<(int_hexagon_V6_vaddbsat_dv_128B HvxWR:$src1, HvxWR:$src2), (V6_vaddbsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubbsat HvxVR:$src1, HvxVR:$src2), - (V6_vsubbsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubbsat_128B HvxVR:$src1, HvxVR:$src2), - (V6_vsubbsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubbsat_dv HvxWR:$src1, HvxWR:$src2), - (V6_vsubbsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubbsat_dv_128B HvxWR:$src1, HvxWR:$src2), - (V6_vsubbsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX128B]>; def: Pat<(int_hexagon_V6_vaddcarry HvxVR:$src1, HvxVR:$src2, HvxQR:$src3), (V6_vaddcarry HvxVR:$src1, HvxVR:$src2, HvxQR:$src3)>, Requires<[HasV62, UseHVX64B]>; def: Pat<(int_hexagon_V6_vaddcarry_128B HvxVR:$src1, HvxVR:$src2, HvxQR:$src3), (V6_vaddcarry HvxVR:$src1, HvxVR:$src2, HvxQR:$src3)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubcarry HvxVR:$src1, HvxVR:$src2, HvxQR:$src3), - (V6_vsubcarry HvxVR:$src1, HvxVR:$src2, HvxQR:$src3)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubcarry_128B HvxVR:$src1, HvxVR:$src2, HvxQR:$src3), - (V6_vsubcarry HvxVR:$src1, HvxVR:$src2, HvxQR:$src3)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddububb_sat HvxVR:$src1, HvxVR:$src2), - (V6_vaddububb_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddububb_sat_128B HvxVR:$src1, HvxVR:$src2), - (V6_vaddububb_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vsubububb_sat HvxVR:$src1, HvxVR:$src2), - (V6_vsubububb_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vsubububb_sat_128B HvxVR:$src1, HvxVR:$src2), - (V6_vsubububb_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddclbh HvxVR:$src1, HvxVR:$src2), + (V6_vaddclbh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddclbh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vaddclbh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddclbw HvxVR:$src1, HvxVR:$src2), + (V6_vaddclbw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddclbw_128B HvxVR:$src1, HvxVR:$src2), + (V6_vaddclbw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; def: Pat<(int_hexagon_V6_vaddhw_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), (V6_vaddhw_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX64B]>; def: Pat<(int_hexagon_V6_vaddhw_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), (V6_vaddhw_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vadduhw_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vadduhw_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vadduhw_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vadduhw_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX128B]>; def: Pat<(int_hexagon_V6_vaddubh_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), (V6_vaddubh_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX64B]>; def: Pat<(int_hexagon_V6_vaddubh_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), (V6_vaddubh_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyewuh_64 HvxVR:$src1, HvxVR:$src2), - (V6_vmpyewuh_64 HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyewuh_64_128B HvxVR:$src1, HvxVR:$src2), - (V6_vmpyewuh_64 HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyowh_64_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpyowh_64_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyowh_64_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vmpyowh_64_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpauhb HvxWR:$src1, IntRegs:$src2), - (V6_vmpauhb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpauhb_128B HvxWR:$src1, IntRegs:$src2), - (V6_vmpauhb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpauhb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), - (V6_vmpauhb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpauhb_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), - (V6_vmpauhb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyiwub HvxVR:$src1, IntRegs:$src2), - (V6_vmpyiwub HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyiwub_128B HvxVR:$src1, IntRegs:$src2), - (V6_vmpyiwub HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyiwub_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vmpyiwub_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyiwub_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vmpyiwub_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaddububb_sat HvxVR:$src1, HvxVR:$src2), + (V6_vaddububb_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaddububb_sat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vaddububb_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vadduhw_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vadduhw_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vadduhw_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vadduhw_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vadduwsat HvxVR:$src1, HvxVR:$src2), + (V6_vadduwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vadduwsat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vadduwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vadduwsat_dv HvxWR:$src1, HvxWR:$src2), + (V6_vadduwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vadduwsat_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vadduwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX128B]>; def: Pat<(int_hexagon_V6_vandnqrt HvxQR:$src1, IntRegs:$src2), (V6_vandnqrt HvxQR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>; def: Pat<(int_hexagon_V6_vandnqrt_128B HvxQR:$src1, IntRegs:$src2), @@ -3114,26 +3087,54 @@ def: Pat<(int_hexagon_V6_vandnqrt_acc HvxVR:$src1, HvxQR:$src2, IntRegs:$src3), (V6_vandnqrt_acc HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>, Requires<[HasV62, UseHVX64B]>; def: Pat<(int_hexagon_V6_vandnqrt_acc_128B HvxVR:$src1, HvxQR:$src2, IntRegs:$src3), (V6_vandnqrt_acc HvxVR:$src1, HvxQR:$src2, IntRegs:$src3)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vandvqv HvxQR:$src1, HvxVR:$src2), - (V6_vandvqv HvxQR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vandvqv_128B HvxQR:$src1, HvxVR:$src2), - (V6_vandvqv HvxQR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; def: Pat<(int_hexagon_V6_vandvnqv HvxQR:$src1, HvxVR:$src2), (V6_vandvnqv HvxQR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; def: Pat<(int_hexagon_V6_vandvnqv_128B HvxQR:$src1, HvxVR:$src2), (V6_vandvnqv HvxQR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_pred_scalar2v2 IntRegs:$src1), - (V6_pred_scalar2v2 IntRegs:$src1)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_pred_scalar2v2_128B IntRegs:$src1), - (V6_pred_scalar2v2 IntRegs:$src1)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_shuffeqw HvxQR:$src1, HvxQR:$src2), - (V6_shuffeqw HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_shuffeqw_128B HvxQR:$src1, HvxQR:$src2), - (V6_shuffeqw HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_shuffeqh HvxQR:$src1, HvxQR:$src2), - (V6_shuffeqh HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_shuffeqh_128B HvxQR:$src1, HvxQR:$src2), - (V6_shuffeqh HvxQR:$src1, HvxQR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vandvqv HvxQR:$src1, HvxVR:$src2), + (V6_vandvqv HvxQR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vandvqv_128B HvxQR:$src1, HvxVR:$src2), + (V6_vandvqv HvxQR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasrhbsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrhbsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasrhbsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrhbsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasruwuhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasruwuhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasruwuhrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasruwuhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasrwuhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrwuhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasrwuhrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasrwuhrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlsrb HvxVR:$src1, IntRegs:$src2), + (V6_vlsrb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlsrb_128B HvxVR:$src1, IntRegs:$src2), + (V6_vlsrb HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlutvvb_nm HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vlutvvb_nm HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlutvvb_nm_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vlutvvb_nm HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlutvvb_oracci HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred_timm:$src4), + (V6_vlutvvb_oracci HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred_timm:$src4)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlutvvb_oracci_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred_timm:$src4), + (V6_vlutvvb_oracci HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred_timm:$src4)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlutvvbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3), + (V6_vlutvvbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlutvvbi_128B HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3), + (V6_vlutvvbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlutvwh_nm HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vlutvwh_nm HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlutvwh_nm_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vlutvwh_nm HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlutvwh_oracci HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred_timm:$src4), + (V6_vlutvwh_oracci HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred_timm:$src4)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlutvwh_oracci_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred_timm:$src4), + (V6_vlutvwh_oracci HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred_timm:$src4)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlutvwhi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3), + (V6_vlutvwhi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlutvwhi_128B HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3), + (V6_vlutvwhi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV62, UseHVX128B]>; def: Pat<(int_hexagon_V6_vmaxb HvxVR:$src1, HvxVR:$src2), (V6_vmaxb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; def: Pat<(int_hexagon_V6_vmaxb_128B HvxVR:$src1, HvxVR:$src2), @@ -3142,97 +3143,69 @@ def: Pat<(int_hexagon_V6_vminb HvxVR:$src1, HvxVR:$src2), (V6_vminb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; def: Pat<(int_hexagon_V6_vminb_128B HvxVR:$src1, HvxVR:$src2), (V6_vminb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpauhb HvxWR:$src1, IntRegs:$src2), + (V6_vmpauhb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpauhb_128B HvxWR:$src1, IntRegs:$src2), + (V6_vmpauhb HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpauhb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vmpauhb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpauhb_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), + (V6_vmpauhb_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyewuh_64 HvxVR:$src1, HvxVR:$src2), + (V6_vmpyewuh_64 HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyewuh_64_128B HvxVR:$src1, HvxVR:$src2), + (V6_vmpyewuh_64 HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyiwub HvxVR:$src1, IntRegs:$src2), + (V6_vmpyiwub HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyiwub_128B HvxVR:$src1, IntRegs:$src2), + (V6_vmpyiwub HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyiwub_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpyiwub_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyiwub_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpyiwub_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyowh_64_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyowh_64_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyowh_64_acc_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vmpyowh_64_acc HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrounduhub HvxVR:$src1, HvxVR:$src2), + (V6_vrounduhub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrounduhub_128B HvxVR:$src1, HvxVR:$src2), + (V6_vrounduhub HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrounduwuh HvxVR:$src1, HvxVR:$src2), + (V6_vrounduwuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrounduwuh_128B HvxVR:$src1, HvxVR:$src2), + (V6_vrounduwuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; def: Pat<(int_hexagon_V6_vsatuwuh HvxVR:$src1, HvxVR:$src2), (V6_vsatuwuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; def: Pat<(int_hexagon_V6_vsatuwuh_128B HvxVR:$src1, HvxVR:$src2), (V6_vsatuwuh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_lvsplath IntRegs:$src1), - (V6_lvsplath IntRegs:$src1)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_lvsplath_128B IntRegs:$src1), - (V6_lvsplath IntRegs:$src1)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_lvsplatb IntRegs:$src1), - (V6_lvsplatb IntRegs:$src1)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_lvsplatb_128B IntRegs:$src1), - (V6_lvsplatb IntRegs:$src1)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddclbw HvxVR:$src1, HvxVR:$src2), - (V6_vaddclbw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddclbw_128B HvxVR:$src1, HvxVR:$src2), - (V6_vaddclbw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaddclbh HvxVR:$src1, HvxVR:$src2), - (V6_vaddclbh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaddclbh_128B HvxVR:$src1, HvxVR:$src2), - (V6_vaddclbh HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vlutvvbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3), - (V6_vlutvvbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vlutvvbi_128B HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3), - (V6_vlutvvbi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vlutvvb_oracci HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred_timm:$src4), - (V6_vlutvvb_oracci HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred_timm:$src4)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vlutvvb_oracci_128B HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred_timm:$src4), - (V6_vlutvvb_oracci HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred_timm:$src4)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vlutvwhi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3), - (V6_vlutvwhi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vlutvwhi_128B HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3), - (V6_vlutvwhi HvxVR:$src1, HvxVR:$src2, u3_0ImmPred_timm:$src3)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vlutvwh_oracci HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred_timm:$src4), - (V6_vlutvwh_oracci HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred_timm:$src4)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vlutvwh_oracci_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred_timm:$src4), - (V6_vlutvwh_oracci HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, u3_0ImmPred_timm:$src4)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vlutvvb_nm HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vlutvvb_nm HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vlutvvb_nm_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vlutvvb_nm HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vlutvwh_nm HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vlutvwh_nm HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vlutvwh_nm_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vlutvwh_nm HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubbsat HvxVR:$src1, HvxVR:$src2), + (V6_vsubbsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubbsat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vsubbsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubbsat_dv HvxWR:$src1, HvxWR:$src2), + (V6_vsubbsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubbsat_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vsubbsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubcarry HvxVR:$src1, HvxVR:$src2, HvxQR:$src3), + (V6_vsubcarry HvxVR:$src1, HvxVR:$src2, HvxQR:$src3)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubcarry_128B HvxVR:$src1, HvxVR:$src2, HvxQR:$src3), + (V6_vsubcarry HvxVR:$src1, HvxVR:$src2, HvxQR:$src3)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubububb_sat HvxVR:$src1, HvxVR:$src2), + (V6_vsubububb_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubububb_sat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vsubububb_sat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubuwsat HvxVR:$src1, HvxVR:$src2), + (V6_vsubuwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubuwsat_128B HvxVR:$src1, HvxVR:$src2), + (V6_vsubuwsat HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV62, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vsubuwsat_dv HvxWR:$src1, HvxWR:$src2), + (V6_vsubuwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vsubuwsat_dv_128B HvxWR:$src1, HvxWR:$src2), + (V6_vsubuwsat_dv HvxWR:$src1, HvxWR:$src2)>, Requires<[HasV62, UseHVX128B]>; // V65 HVX Instructions. -def: Pat<(int_hexagon_V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vasruwuhsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vasruhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasruhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vasruhubsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasruhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vasruhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasruhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vasruhubrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), - (V6_vasruhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vaslh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vaslh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vaslh_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vaslh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vasrh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vasrh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vasrh_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vasrh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vavguw HvxVR:$src1, HvxVR:$src2), - (V6_vavguw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vavguw_128B HvxVR:$src1, HvxVR:$src2), - (V6_vavguw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vavguwrnd HvxVR:$src1, HvxVR:$src2), - (V6_vavguwrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vavguwrnd_128B HvxVR:$src1, HvxVR:$src2), - (V6_vavguwrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vavgb HvxVR:$src1, HvxVR:$src2), - (V6_vavgb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vavgb_128B HvxVR:$src1, HvxVR:$src2), - (V6_vavgb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vavgbrnd HvxVR:$src1, HvxVR:$src2), - (V6_vavgbrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vavgbrnd_128B HvxVR:$src1, HvxVR:$src2), - (V6_vavgbrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vnavgb HvxVR:$src1, HvxVR:$src2), - (V6_vnavgb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vnavgb_128B HvxVR:$src1, HvxVR:$src2), - (V6_vnavgb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vdd0 ), - (V6_vdd0 )>, Requires<[HasV65, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vdd0_128B ), - (V6_vdd0 )>, Requires<[HasV65, UseHVX128B]>; def: Pat<(int_hexagon_V6_vabsb HvxVR:$src1), (V6_vabsb HvxVR:$src1)>, Requires<[HasV65, UseHVX64B]>; def: Pat<(int_hexagon_V6_vabsb_128B HvxVR:$src1), @@ -3241,6 +3214,50 @@ def: Pat<(int_hexagon_V6_vabsb_sat HvxVR:$src1), (V6_vabsb_sat HvxVR:$src1)>, Requires<[HasV65, UseHVX64B]>; def: Pat<(int_hexagon_V6_vabsb_sat_128B HvxVR:$src1), (V6_vabsb_sat HvxVR:$src1)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vaslh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vaslh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vaslh_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vaslh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasrh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vasrh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasrh_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vasrh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasruhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasruhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasruhubrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasruhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasruhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasruhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasruhubsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasruhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasruwuhsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), + (V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vavgb HvxVR:$src1, HvxVR:$src2), + (V6_vavgb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vavgb_128B HvxVR:$src1, HvxVR:$src2), + (V6_vavgb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vavgbrnd HvxVR:$src1, HvxVR:$src2), + (V6_vavgbrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vavgbrnd_128B HvxVR:$src1, HvxVR:$src2), + (V6_vavgbrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vavguw HvxVR:$src1, HvxVR:$src2), + (V6_vavguw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vavguw_128B HvxVR:$src1, HvxVR:$src2), + (V6_vavguw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vavguwrnd HvxVR:$src1, HvxVR:$src2), + (V6_vavguwrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vavguwrnd_128B HvxVR:$src1, HvxVR:$src2), + (V6_vavguwrnd HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vdd0 ), + (V6_vdd0 )>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vdd0_128B ), + (V6_vdd0 )>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vlut4 HvxVR:$src1, DoubleRegs:$src2), + (V6_vlut4 HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vlut4_128B HvxVR:$src1, DoubleRegs:$src2), + (V6_vlut4 HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65, UseHVX128B]>; def: Pat<(int_hexagon_V6_vmpabuu HvxWR:$src1, IntRegs:$src2), (V6_vmpabuu HvxWR:$src1, IntRegs:$src2)>, Requires<[HasV65, UseHVX64B]>; def: Pat<(int_hexagon_V6_vmpabuu_128B HvxWR:$src1, IntRegs:$src2), @@ -3249,10 +3266,6 @@ def: Pat<(int_hexagon_V6_vmpabuu_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), (V6_vmpabuu_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX64B]>; def: Pat<(int_hexagon_V6_vmpabuu_acc_128B HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), (V6_vmpabuu_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vmpyh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vmpyh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vmpyh_acc_128B HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), - (V6_vmpyh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX128B]>; def: Pat<(int_hexagon_V6_vmpahhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vmpahhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX64B]>; def: Pat<(int_hexagon_V6_vmpahhsat_128B HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), @@ -3265,10 +3278,10 @@ def: Pat<(int_hexagon_V6_vmpsuhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3) (V6_vmpsuhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX64B]>; def: Pat<(int_hexagon_V6_vmpsuhuhsat_128B HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3), (V6_vmpsuhuhsat HvxVR:$src1, HvxVR:$src2, DoubleRegs:$src3)>, Requires<[HasV65, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vlut4 HvxVR:$src1, DoubleRegs:$src2), - (V6_vlut4 HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vlut4_128B HvxVR:$src1, DoubleRegs:$src2), - (V6_vlut4 HvxVR:$src1, DoubleRegs:$src2)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vmpyh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpyh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vmpyh_acc_128B HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), + (V6_vmpyh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX128B]>; def: Pat<(int_hexagon_V6_vmpyuhe HvxVR:$src1, IntRegs:$src2), (V6_vmpyuhe HvxVR:$src1, IntRegs:$src2)>, Requires<[HasV65, UseHVX64B]>; def: Pat<(int_hexagon_V6_vmpyuhe_128B HvxVR:$src1, IntRegs:$src2), @@ -3277,42 +3290,10 @@ def: Pat<(int_hexagon_V6_vmpyuhe_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vmpyuhe_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX64B]>; def: Pat<(int_hexagon_V6_vmpyuhe_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vmpyuhe_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3)>, Requires<[HasV65, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vscattermw IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), - (V6_vscattermw IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vscattermw_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), - (V6_vscattermw IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vscattermh IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), - (V6_vscattermh IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vscattermh_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), - (V6_vscattermh IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vscattermw_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), - (V6_vscattermw_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vscattermw_add_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), - (V6_vscattermw_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vscattermh_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), - (V6_vscattermh_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vscattermh_add_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), - (V6_vscattermh_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vscattermwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5), - (V6_vscattermwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5)>, Requires<[HasV65, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vscattermwq_128B HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5), - (V6_vscattermwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5)>, Requires<[HasV65, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vscattermhq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5), - (V6_vscattermhq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5)>, Requires<[HasV65, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vscattermhq_128B HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5), - (V6_vscattermhq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5)>, Requires<[HasV65, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vscattermhw IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4), - (V6_vscattermhw IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vscattermhw_128B IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4), - (V6_vscattermhw IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vscattermhwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxWR:$src4, HvxVR:$src5), - (V6_vscattermhwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxWR:$src4, HvxVR:$src5)>, Requires<[HasV65, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vscattermhwq_128B HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxWR:$src4, HvxVR:$src5), - (V6_vscattermhwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxWR:$src4, HvxVR:$src5)>, Requires<[HasV65, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vscattermhw_add IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4), - (V6_vscattermhw_add IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vscattermhw_add_128B IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4), - (V6_vscattermhw_add IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vnavgb HvxVR:$src1, HvxVR:$src2), + (V6_vnavgb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vnavgb_128B HvxVR:$src1, HvxVR:$src2), + (V6_vnavgb HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV65, UseHVX128B]>; def: Pat<(int_hexagon_V6_vprefixqb HvxQR:$src1), (V6_vprefixqb HvxQR:$src1)>, Requires<[HasV65, UseHVX64B]>; def: Pat<(int_hexagon_V6_vprefixqb_128B HvxQR:$src1), @@ -3325,22 +3306,77 @@ def: Pat<(int_hexagon_V6_vprefixqw HvxQR:$src1), (V6_vprefixqw HvxQR:$src1)>, Requires<[HasV65, UseHVX64B]>; def: Pat<(int_hexagon_V6_vprefixqw_128B HvxQR:$src1), (V6_vprefixqw HvxQR:$src1)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vscattermh IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), + (V6_vscattermh IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vscattermh_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), + (V6_vscattermh IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vscattermh_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), + (V6_vscattermh_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vscattermh_add_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), + (V6_vscattermh_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vscattermhq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5), + (V6_vscattermhq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vscattermhq_128B HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5), + (V6_vscattermhq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vscattermhw IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4), + (V6_vscattermhw IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vscattermhw_128B IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4), + (V6_vscattermhw IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vscattermhw_add IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4), + (V6_vscattermhw_add IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vscattermhw_add_128B IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4), + (V6_vscattermhw_add IntRegs:$src1, ModRegs:$src2, HvxWR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vscattermhwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxWR:$src4, HvxVR:$src5), + (V6_vscattermhwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxWR:$src4, HvxVR:$src5)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vscattermhwq_128B HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxWR:$src4, HvxVR:$src5), + (V6_vscattermhwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxWR:$src4, HvxVR:$src5)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vscattermw IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), + (V6_vscattermw IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vscattermw_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), + (V6_vscattermw IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vscattermw_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), + (V6_vscattermw_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vscattermw_add_128B IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4), + (V6_vscattermw_add IntRegs:$src1, ModRegs:$src2, HvxVR:$src3, HvxVR:$src4)>, Requires<[HasV65, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vscattermwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5), + (V6_vscattermwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5)>, Requires<[HasV65, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vscattermwq_128B HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5), + (V6_vscattermwq HvxQR:$src1, IntRegs:$src2, ModRegs:$src3, HvxVR:$src4, HvxVR:$src5)>, Requires<[HasV65, UseHVX128B]>; // V66 HVX Instructions. -def: Pat<(int_hexagon_V6_vrotr HvxVR:$src1, HvxVR:$src2), - (V6_vrotr HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV66, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vrotr_128B HvxVR:$src1, HvxVR:$src2), - (V6_vrotr HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV66, UseHVX128B]>; -def: Pat<(int_hexagon_V6_vasr_into HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vasr_into HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV66, UseHVX64B]>; -def: Pat<(int_hexagon_V6_vasr_into_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), - (V6_vasr_into HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV66, UseHVX128B]>; def: Pat<(int_hexagon_V6_vaddcarrysat HvxVR:$src1, HvxVR:$src2, HvxQR:$src3), (V6_vaddcarrysat HvxVR:$src1, HvxVR:$src2, HvxQR:$src3)>, Requires<[HasV66, UseHVX64B]>; def: Pat<(int_hexagon_V6_vaddcarrysat_128B HvxVR:$src1, HvxVR:$src2, HvxQR:$src3), (V6_vaddcarrysat HvxVR:$src1, HvxVR:$src2, HvxQR:$src3)>, Requires<[HasV66, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vasr_into HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vasr_into HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV66, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vasr_into_128B HvxWR:$src1, HvxVR:$src2, HvxVR:$src3), + (V6_vasr_into HvxWR:$src1, HvxVR:$src2, HvxVR:$src3)>, Requires<[HasV66, UseHVX128B]>; +def: Pat<(int_hexagon_V6_vrotr HvxVR:$src1, HvxVR:$src2), + (V6_vrotr HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV66, UseHVX64B]>; +def: Pat<(int_hexagon_V6_vrotr_128B HvxVR:$src1, HvxVR:$src2), + (V6_vrotr HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV66, UseHVX128B]>; def: Pat<(int_hexagon_V6_vsatdw HvxVR:$src1, HvxVR:$src2), (V6_vsatdw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV66, UseHVX64B]>; def: Pat<(int_hexagon_V6_vsatdw_128B HvxVR:$src1, HvxVR:$src2), (V6_vsatdw HvxVR:$src1, HvxVR:$src2)>, Requires<[HasV66, UseHVX128B]>; + +// V68 HVX Instructions. + +def: Pat<(int_hexagon_V6_v6mpyhubs10 HvxWR:$src1, HvxWR:$src2, u2_0ImmPred_timm:$src3), + (V6_v6mpyhubs10 HvxWR:$src1, HvxWR:$src2, u2_0ImmPred_timm:$src3)>, Requires<[HasV68, UseHVX64B]>; +def: Pat<(int_hexagon_V6_v6mpyhubs10_128B HvxWR:$src1, HvxWR:$src2, u2_0ImmPred_timm:$src3), + (V6_v6mpyhubs10 HvxWR:$src1, HvxWR:$src2, u2_0ImmPred_timm:$src3)>, Requires<[HasV68, UseHVX128B]>; +def: Pat<(int_hexagon_V6_v6mpyhubs10_vxx HvxWR:$src1, HvxWR:$src2, HvxWR:$src3, u2_0ImmPred_timm:$src4), + (V6_v6mpyhubs10_vxx HvxWR:$src1, HvxWR:$src2, HvxWR:$src3, u2_0ImmPred_timm:$src4)>, Requires<[HasV68, UseHVX64B]>; +def: Pat<(int_hexagon_V6_v6mpyhubs10_vxx_128B HvxWR:$src1, HvxWR:$src2, HvxWR:$src3, u2_0ImmPred_timm:$src4), + (V6_v6mpyhubs10_vxx HvxWR:$src1, HvxWR:$src2, HvxWR:$src3, u2_0ImmPred_timm:$src4)>, Requires<[HasV68, UseHVX128B]>; +def: Pat<(int_hexagon_V6_v6mpyvubs10 HvxWR:$src1, HvxWR:$src2, u2_0ImmPred_timm:$src3), + (V6_v6mpyvubs10 HvxWR:$src1, HvxWR:$src2, u2_0ImmPred_timm:$src3)>, Requires<[HasV68, UseHVX64B]>; +def: Pat<(int_hexagon_V6_v6mpyvubs10_128B HvxWR:$src1, HvxWR:$src2, u2_0ImmPred_timm:$src3), + (V6_v6mpyvubs10 HvxWR:$src1, HvxWR:$src2, u2_0ImmPred_timm:$src3)>, Requires<[HasV68, UseHVX128B]>; +def: Pat<(int_hexagon_V6_v6mpyvubs10_vxx HvxWR:$src1, HvxWR:$src2, HvxWR:$src3, u2_0ImmPred_timm:$src4), + (V6_v6mpyvubs10_vxx HvxWR:$src1, HvxWR:$src2, HvxWR:$src3, u2_0ImmPred_timm:$src4)>, Requires<[HasV68, UseHVX64B]>; +def: Pat<(int_hexagon_V6_v6mpyvubs10_vxx_128B HvxWR:$src1, HvxWR:$src2, HvxWR:$src3, u2_0ImmPred_timm:$src4), + (V6_v6mpyvubs10_vxx HvxWR:$src1, HvxWR:$src2, HvxWR:$src3, u2_0ImmPred_timm:$src4)>, Requires<[HasV68, UseHVX128B]>; diff --git a/lib/Target/Hexagon/HexagonDepMappings.td b/lib/Target/Hexagon/HexagonDepMappings.td index 3fca1aee9a6..919cb996ad1 100644 --- a/lib/Target/Hexagon/HexagonDepMappings.td +++ b/lib/Target/Hexagon/HexagonDepMappings.td @@ -197,6 +197,8 @@ def V6_stqnt0Alias : InstAlias<"if ($Qv4) vmem($Rt32):nt = $Vs32", (V6_vS32b_nt_ def V6_stu0Alias : InstAlias<"vmemu($Rt32) = $Vs32", (V6_vS32Ub_ai IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; def V6_stunp0Alias : InstAlias<"if (!$Pv4) vmemu($Rt32) = $Vs32", (V6_vS32Ub_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; def V6_stup0Alias : InstAlias<"if ($Pv4) vmemu($Rt32) = $Vs32", (V6_vS32Ub_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, HvxVR:$Vs32)>, Requires<[UseHVX]>; +def V6_v6mpyhubs10_altAlias : InstAlias<"$Vdd32.w = v6mpy($Vuu32.ub,$Vvv32.b10,#$Ii):h", (V6_v6mpyhubs10 HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32, u2_0Imm:$Ii)>, Requires<[UseHVX]>; +def V6_v6mpyvubs10_altAlias : InstAlias<"$Vdd32.w = v6mpy($Vuu32.ub,$Vvv32.b10,#$Ii):v", (V6_v6mpyvubs10 HvxWR:$Vdd32, HvxWR:$Vuu32, HvxWR:$Vvv32, u2_0Imm:$Ii)>, Requires<[UseHVX]>; def V6_vabsb_altAlias : InstAlias<"$Vd32 = vabsb($Vu32)", (V6_vabsb HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; def V6_vabsb_sat_altAlias : InstAlias<"$Vd32 = vabsb($Vu32):sat", (V6_vabsb_sat HvxVR:$Vd32, HvxVR:$Vu32)>, Requires<[UseHVX]>; def V6_vabsdiffh_altAlias : InstAlias<"$Vd32 = vabsdiffh($Vu32,$Vv32)", (V6_vabsdiffh HvxVR:$Vd32, HvxVR:$Vu32, HvxVR:$Vv32)>, Requires<[UseHVX]>; diff --git a/lib/Target/Hexagon/HexagonDepMask.h b/lib/Target/Hexagon/HexagonDepMask.h index 742fe2d14d5..45e1a1e0f39 100644 --- a/lib/Target/Hexagon/HexagonDepMask.h +++ b/lib/Target/Hexagon/HexagonDepMask.h @@ -8,10 +8,10 @@ // Automatically generated file, do not edit! //===----------------------------------------------------------------------===// + #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPMASK_H #define LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPMASK_H -// clang-format off HexagonInstruction InstructionEncodings[] = { { /*Tag:A2_addi*/ /*Rd32=add(Rs32,#s16)*/ @@ -2816,6 +2816,5 @@ HexagonInstruction InstructionEncodings[] = { 0x00002404, 0 } }; -// clang-format off #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPMASK_H diff --git a/lib/Target/Hexagon/HexagonDepOperands.td b/lib/Target/Hexagon/HexagonDepOperands.td index 6ef668d3076..4bdda2cdd52 100644 --- a/lib/Target/Hexagon/HexagonDepOperands.td +++ b/lib/Target/Hexagon/HexagonDepOperands.td @@ -13,120 +13,120 @@ multiclass ImmOpPred { def _timm : PatLeaf<(vt timm), pred>; } +def s6_0ImmOperand : AsmOperandClass { let Name = "s6_0Imm"; let RenderMethod = "addSignedImmOperands"; } +def s6_0Imm : Operand { let ParserMatchClass = s6_0ImmOperand; let DecoderMethod = "s6_0ImmDecoder"; } +defm s6_0ImmPred : ImmOpPred<[{ return isShiftedInt<6, 0>(N->getSExtValue());}]>; def s32_0ImmOperand : AsmOperandClass { let Name = "s32_0Imm"; let RenderMethod = "addSignedImmOperands"; } def s32_0Imm : Operand { let ParserMatchClass = s32_0ImmOperand; let DecoderMethod = "s32_0ImmDecoder"; } defm s32_0ImmPred : ImmOpPred<[{ return isShiftedInt<32, 0>(N->getSExtValue());}]>; -def s8_0ImmOperand : AsmOperandClass { let Name = "s8_0Imm"; let RenderMethod = "addSignedImmOperands"; } -def s8_0Imm : Operand { let ParserMatchClass = s8_0ImmOperand; let DecoderMethod = "s8_0ImmDecoder"; } -defm s8_0ImmPred : ImmOpPred<[{ return isShiftedInt<8, 0>(N->getSExtValue());}]>; -def u16_0ImmOperand : AsmOperandClass { let Name = "u16_0Imm"; let RenderMethod = "addImmOperands"; } -def u16_0Imm : Operand { let ParserMatchClass = u16_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } -defm u16_0ImmPred : ImmOpPred<[{ return isShiftedUInt<16, 0>(N->getSExtValue());}]>; -def u5_0ImmOperand : AsmOperandClass { let Name = "u5_0Imm"; let RenderMethod = "addImmOperands"; } -def u5_0Imm : Operand { let ParserMatchClass = u5_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } -defm u5_0ImmPred : ImmOpPred<[{ return isShiftedUInt<5, 0>(N->getSExtValue());}]>; -def u8_0ImmOperand : AsmOperandClass { let Name = "u8_0Imm"; let RenderMethod = "addImmOperands"; } -def u8_0Imm : Operand { let ParserMatchClass = u8_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } -defm u8_0ImmPred : ImmOpPred<[{ return isShiftedUInt<8, 0>(N->getSExtValue());}]>; -def u32_0ImmOperand : AsmOperandClass { let Name = "u32_0Imm"; let RenderMethod = "addImmOperands"; } -def u32_0Imm : Operand { let ParserMatchClass = u32_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } -defm u32_0ImmPred : ImmOpPred<[{ return isShiftedUInt<32, 0>(N->getSExtValue());}]>; -def u26_6ImmOperand : AsmOperandClass { let Name = "u26_6Imm"; let RenderMethod = "addImmOperands"; } -def u26_6Imm : Operand { let ParserMatchClass = u26_6ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } -defm u26_6ImmPred : ImmOpPred<[{ return isShiftedUInt<26, 6>(N->getSExtValue());}]>; -def u7_0ImmOperand : AsmOperandClass { let Name = "u7_0Imm"; let RenderMethod = "addImmOperands"; } -def u7_0Imm : Operand { let ParserMatchClass = u7_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } -defm u7_0ImmPred : ImmOpPred<[{ return isShiftedUInt<7, 0>(N->getSExtValue());}]>; -def u6_0ImmOperand : AsmOperandClass { let Name = "u6_0Imm"; let RenderMethod = "addImmOperands"; } -def u6_0Imm : Operand { let ParserMatchClass = u6_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } -defm u6_0ImmPred : ImmOpPred<[{ return isShiftedUInt<6, 0>(N->getSExtValue());}]>; def u10_0ImmOperand : AsmOperandClass { let Name = "u10_0Imm"; let RenderMethod = "addImmOperands"; } def u10_0Imm : Operand { let ParserMatchClass = u10_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } defm u10_0ImmPred : ImmOpPred<[{ return isShiftedUInt<10, 0>(N->getSExtValue());}]>; +def u32_0ImmOperand : AsmOperandClass { let Name = "u32_0Imm"; let RenderMethod = "addImmOperands"; } +def u32_0Imm : Operand { let ParserMatchClass = u32_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +defm u32_0ImmPred : ImmOpPred<[{ return isShiftedUInt<32, 0>(N->getSExtValue());}]>; +def m32_0ImmOperand : AsmOperandClass { let Name = "m32_0Imm"; let RenderMethod = "addImmOperands"; } +def m32_0Imm : Operand { let ParserMatchClass = m32_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +defm m32_0ImmPred : ImmOpPred<[{ return isShiftedInt<32, 0>(N->getSExtValue());}]>; +def b13_2ImmOperand : AsmOperandClass { let Name = "b13_2Imm"; let RenderMethod = "addSignedImmOperands"; } +def b13_2Imm : Operand { let ParserMatchClass = b13_2ImmOperand; let DecoderMethod = "brtargetDecoder"; let PrintMethod = "printBrtarget"; } +defm b13_2ImmPred : ImmOpPred<[{ return isShiftedInt<13, 2>(N->getSExtValue());}]>; +def b15_2ImmOperand : AsmOperandClass { let Name = "b15_2Imm"; let RenderMethod = "addSignedImmOperands"; } +def b15_2Imm : Operand { let ParserMatchClass = b15_2ImmOperand; let DecoderMethod = "brtargetDecoder"; let PrintMethod = "printBrtarget"; } +defm b15_2ImmPred : ImmOpPred<[{ return isShiftedInt<15, 2>(N->getSExtValue());}]>; def a30_2ImmOperand : AsmOperandClass { let Name = "a30_2Imm"; let RenderMethod = "addSignedImmOperands"; } def a30_2Imm : Operand { let ParserMatchClass = a30_2ImmOperand; let DecoderMethod = "brtargetDecoder"; let PrintMethod = "printBrtarget"; } defm a30_2ImmPred : ImmOpPred<[{ return isShiftedInt<32, 2>(N->getSExtValue());}]>; def b30_2ImmOperand : AsmOperandClass { let Name = "b30_2Imm"; let RenderMethod = "addSignedImmOperands"; } def b30_2Imm : Operand { let ParserMatchClass = b30_2ImmOperand; let DecoderMethod = "brtargetDecoder"; let PrintMethod = "printBrtarget"; } defm b30_2ImmPred : ImmOpPred<[{ return isShiftedInt<32, 2>(N->getSExtValue());}]>; -def b15_2ImmOperand : AsmOperandClass { let Name = "b15_2Imm"; let RenderMethod = "addSignedImmOperands"; } -def b15_2Imm : Operand { let ParserMatchClass = b15_2ImmOperand; let DecoderMethod = "brtargetDecoder"; let PrintMethod = "printBrtarget"; } -defm b15_2ImmPred : ImmOpPred<[{ return isShiftedInt<15, 2>(N->getSExtValue());}]>; -def b13_2ImmOperand : AsmOperandClass { let Name = "b13_2Imm"; let RenderMethod = "addSignedImmOperands"; } -def b13_2Imm : Operand { let ParserMatchClass = b13_2ImmOperand; let DecoderMethod = "brtargetDecoder"; let PrintMethod = "printBrtarget"; } -defm b13_2ImmPred : ImmOpPred<[{ return isShiftedInt<13, 2>(N->getSExtValue());}]>; -def s4_0ImmOperand : AsmOperandClass { let Name = "s4_0Imm"; let RenderMethod = "addSignedImmOperands"; } -def s4_0Imm : Operand { let ParserMatchClass = s4_0ImmOperand; let DecoderMethod = "s4_0ImmDecoder"; } -defm s4_0ImmPred : ImmOpPred<[{ return isShiftedInt<4, 0>(N->getSExtValue());}]>; def s31_1ImmOperand : AsmOperandClass { let Name = "s31_1Imm"; let RenderMethod = "addSignedImmOperands"; } def s31_1Imm : Operand { let ParserMatchClass = s31_1ImmOperand; let DecoderMethod = "s31_1ImmDecoder"; } defm s31_1ImmPred : ImmOpPred<[{ return isShiftedInt<32, 1>(N->getSExtValue());}]>; -def s4_1ImmOperand : AsmOperandClass { let Name = "s4_1Imm"; let RenderMethod = "addSignedImmOperands"; } -def s4_1Imm : Operand { let ParserMatchClass = s4_1ImmOperand; let DecoderMethod = "s4_1ImmDecoder"; } -defm s4_1ImmPred : ImmOpPred<[{ return isShiftedInt<4, 1>(N->getSExtValue());}]>; def s30_2ImmOperand : AsmOperandClass { let Name = "s30_2Imm"; let RenderMethod = "addSignedImmOperands"; } def s30_2Imm : Operand { let ParserMatchClass = s30_2ImmOperand; let DecoderMethod = "s30_2ImmDecoder"; } defm s30_2ImmPred : ImmOpPred<[{ return isShiftedInt<32, 2>(N->getSExtValue());}]>; -def s4_2ImmOperand : AsmOperandClass { let Name = "s4_2Imm"; let RenderMethod = "addSignedImmOperands"; } -def s4_2Imm : Operand { let ParserMatchClass = s4_2ImmOperand; let DecoderMethod = "s4_2ImmDecoder"; } -defm s4_2ImmPred : ImmOpPred<[{ return isShiftedInt<4, 2>(N->getSExtValue());}]>; def s29_3ImmOperand : AsmOperandClass { let Name = "s29_3Imm"; let RenderMethod = "addSignedImmOperands"; } def s29_3Imm : Operand { let ParserMatchClass = s29_3ImmOperand; let DecoderMethod = "s29_3ImmDecoder"; } defm s29_3ImmPred : ImmOpPred<[{ return isShiftedInt<32, 3>(N->getSExtValue());}]>; -def s4_3ImmOperand : AsmOperandClass { let Name = "s4_3Imm"; let RenderMethod = "addSignedImmOperands"; } -def s4_3Imm : Operand { let ParserMatchClass = s4_3ImmOperand; let DecoderMethod = "s4_3ImmDecoder"; } -defm s4_3ImmPred : ImmOpPred<[{ return isShiftedInt<4, 3>(N->getSExtValue());}]>; -def u29_3ImmOperand : AsmOperandClass { let Name = "u29_3Imm"; let RenderMethod = "addImmOperands"; } -def u29_3Imm : Operand { let ParserMatchClass = u29_3ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } -defm u29_3ImmPred : ImmOpPred<[{ return isShiftedUInt<32, 3>(N->getSExtValue());}]>; -def u31_1ImmOperand : AsmOperandClass { let Name = "u31_1Imm"; let RenderMethod = "addImmOperands"; } -def u31_1Imm : Operand { let ParserMatchClass = u31_1ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } -defm u31_1ImmPred : ImmOpPred<[{ return isShiftedUInt<32, 1>(N->getSExtValue());}]>; -def u30_2ImmOperand : AsmOperandClass { let Name = "u30_2Imm"; let RenderMethod = "addImmOperands"; } -def u30_2Imm : Operand { let ParserMatchClass = u30_2ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } -defm u30_2ImmPred : ImmOpPred<[{ return isShiftedUInt<32, 2>(N->getSExtValue());}]>; -def u2_0ImmOperand : AsmOperandClass { let Name = "u2_0Imm"; let RenderMethod = "addImmOperands"; } -def u2_0Imm : Operand { let ParserMatchClass = u2_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } -defm u2_0ImmPred : ImmOpPred<[{ return isShiftedUInt<2, 0>(N->getSExtValue());}]>; -def m32_0ImmOperand : AsmOperandClass { let Name = "m32_0Imm"; let RenderMethod = "addImmOperands"; } -def m32_0Imm : Operand { let ParserMatchClass = m32_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } -defm m32_0ImmPred : ImmOpPred<[{ return isShiftedInt<32, 0>(N->getSExtValue());}]>; -def u6_2ImmOperand : AsmOperandClass { let Name = "u6_2Imm"; let RenderMethod = "addImmOperands"; } -def u6_2Imm : Operand { let ParserMatchClass = u6_2ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } -defm u6_2ImmPred : ImmOpPred<[{ return isShiftedUInt<6, 2>(N->getSExtValue());}]>; -def u3_0ImmOperand : AsmOperandClass { let Name = "u3_0Imm"; let RenderMethod = "addImmOperands"; } -def u3_0Imm : Operand { let ParserMatchClass = u3_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } -defm u3_0ImmPred : ImmOpPred<[{ return isShiftedUInt<3, 0>(N->getSExtValue());}]>; -def u11_3ImmOperand : AsmOperandClass { let Name = "u11_3Imm"; let RenderMethod = "addImmOperands"; } -def u11_3Imm : Operand { let ParserMatchClass = u11_3ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } -defm u11_3ImmPred : ImmOpPred<[{ return isShiftedUInt<11, 3>(N->getSExtValue());}]>; -def u4_0ImmOperand : AsmOperandClass { let Name = "u4_0Imm"; let RenderMethod = "addImmOperands"; } -def u4_0Imm : Operand { let ParserMatchClass = u4_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } -defm u4_0ImmPred : ImmOpPred<[{ return isShiftedUInt<4, 0>(N->getSExtValue());}]>; -def s6_0ImmOperand : AsmOperandClass { let Name = "s6_0Imm"; let RenderMethod = "addSignedImmOperands"; } -def s6_0Imm : Operand { let ParserMatchClass = s6_0ImmOperand; let DecoderMethod = "s6_0ImmDecoder"; } -defm s6_0ImmPred : ImmOpPred<[{ return isShiftedInt<6, 0>(N->getSExtValue());}]>; -def u6_1ImmOperand : AsmOperandClass { let Name = "u6_1Imm"; let RenderMethod = "addImmOperands"; } -def u6_1Imm : Operand { let ParserMatchClass = u6_1ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } -defm u6_1ImmPred : ImmOpPred<[{ return isShiftedUInt<6, 1>(N->getSExtValue());}]>; -def u4_2ImmOperand : AsmOperandClass { let Name = "u4_2Imm"; let RenderMethod = "addImmOperands"; } -def u4_2Imm : Operand { let ParserMatchClass = u4_2ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } -defm u4_2ImmPred : ImmOpPred<[{ return isShiftedUInt<4, 2>(N->getSExtValue());}]>; -def u5_3ImmOperand : AsmOperandClass { let Name = "u5_3Imm"; let RenderMethod = "addImmOperands"; } -def u5_3Imm : Operand { let ParserMatchClass = u5_3ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } -defm u5_3ImmPred : ImmOpPred<[{ return isShiftedUInt<5, 3>(N->getSExtValue());}]>; -def u3_1ImmOperand : AsmOperandClass { let Name = "u3_1Imm"; let RenderMethod = "addImmOperands"; } -def u3_1Imm : Operand { let ParserMatchClass = u3_1ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } -defm u3_1ImmPred : ImmOpPred<[{ return isShiftedUInt<3, 1>(N->getSExtValue());}]>; -def u5_2ImmOperand : AsmOperandClass { let Name = "u5_2Imm"; let RenderMethod = "addImmOperands"; } -def u5_2Imm : Operand { let ParserMatchClass = u5_2ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } -defm u5_2ImmPred : ImmOpPred<[{ return isShiftedUInt<5, 2>(N->getSExtValue());}]>; -def s6_3ImmOperand : AsmOperandClass { let Name = "s6_3Imm"; let RenderMethod = "addSignedImmOperands"; } -def s6_3Imm : Operand { let ParserMatchClass = s6_3ImmOperand; let DecoderMethod = "s6_3ImmDecoder"; } -defm s6_3ImmPred : ImmOpPred<[{ return isShiftedInt<6, 3>(N->getSExtValue());}]>; def s3_0ImmOperand : AsmOperandClass { let Name = "s3_0Imm"; let RenderMethod = "addSignedImmOperands"; } def s3_0Imm : Operand { let ParserMatchClass = s3_0ImmOperand; let DecoderMethod = "s3_0ImmDecoder"; } defm s3_0ImmPred : ImmOpPred<[{ return isShiftedInt<3, 0>(N->getSExtValue());}]>; +def s4_0ImmOperand : AsmOperandClass { let Name = "s4_0Imm"; let RenderMethod = "addSignedImmOperands"; } +def s4_0Imm : Operand { let ParserMatchClass = s4_0ImmOperand; let DecoderMethod = "s4_0ImmDecoder"; } +defm s4_0ImmPred : ImmOpPred<[{ return isShiftedInt<4, 0>(N->getSExtValue());}]>; +def s4_1ImmOperand : AsmOperandClass { let Name = "s4_1Imm"; let RenderMethod = "addSignedImmOperands"; } +def s4_1Imm : Operand { let ParserMatchClass = s4_1ImmOperand; let DecoderMethod = "s4_1ImmDecoder"; } +defm s4_1ImmPred : ImmOpPred<[{ return isShiftedInt<4, 1>(N->getSExtValue());}]>; +def s4_2ImmOperand : AsmOperandClass { let Name = "s4_2Imm"; let RenderMethod = "addSignedImmOperands"; } +def s4_2Imm : Operand { let ParserMatchClass = s4_2ImmOperand; let DecoderMethod = "s4_2ImmDecoder"; } +defm s4_2ImmPred : ImmOpPred<[{ return isShiftedInt<4, 2>(N->getSExtValue());}]>; +def s4_3ImmOperand : AsmOperandClass { let Name = "s4_3Imm"; let RenderMethod = "addSignedImmOperands"; } +def s4_3Imm : Operand { let ParserMatchClass = s4_3ImmOperand; let DecoderMethod = "s4_3ImmDecoder"; } +defm s4_3ImmPred : ImmOpPred<[{ return isShiftedInt<4, 3>(N->getSExtValue());}]>; +def s6_3ImmOperand : AsmOperandClass { let Name = "s6_3Imm"; let RenderMethod = "addSignedImmOperands"; } +def s6_3Imm : Operand { let ParserMatchClass = s6_3ImmOperand; let DecoderMethod = "s6_3ImmDecoder"; } +defm s6_3ImmPred : ImmOpPred<[{ return isShiftedInt<6, 3>(N->getSExtValue());}]>; +def s8_0ImmOperand : AsmOperandClass { let Name = "s8_0Imm"; let RenderMethod = "addSignedImmOperands"; } +def s8_0Imm : Operand { let ParserMatchClass = s8_0ImmOperand; let DecoderMethod = "s8_0ImmDecoder"; } +defm s8_0ImmPred : ImmOpPred<[{ return isShiftedInt<8, 0>(N->getSExtValue());}]>; def u1_0ImmOperand : AsmOperandClass { let Name = "u1_0Imm"; let RenderMethod = "addImmOperands"; } def u1_0Imm : Operand { let ParserMatchClass = u1_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } defm u1_0ImmPred : ImmOpPred<[{ return isShiftedUInt<1, 0>(N->getSExtValue());}]>; +def u11_3ImmOperand : AsmOperandClass { let Name = "u11_3Imm"; let RenderMethod = "addImmOperands"; } +def u11_3Imm : Operand { let ParserMatchClass = u11_3ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +defm u11_3ImmPred : ImmOpPred<[{ return isShiftedUInt<11, 3>(N->getSExtValue());}]>; +def u16_0ImmOperand : AsmOperandClass { let Name = "u16_0Imm"; let RenderMethod = "addImmOperands"; } +def u16_0Imm : Operand { let ParserMatchClass = u16_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +defm u16_0ImmPred : ImmOpPred<[{ return isShiftedUInt<16, 0>(N->getSExtValue());}]>; +def u2_0ImmOperand : AsmOperandClass { let Name = "u2_0Imm"; let RenderMethod = "addImmOperands"; } +def u2_0Imm : Operand { let ParserMatchClass = u2_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +defm u2_0ImmPred : ImmOpPred<[{ return isShiftedUInt<2, 0>(N->getSExtValue());}]>; +def u26_6ImmOperand : AsmOperandClass { let Name = "u26_6Imm"; let RenderMethod = "addImmOperands"; } +def u26_6Imm : Operand { let ParserMatchClass = u26_6ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +defm u26_6ImmPred : ImmOpPred<[{ return isShiftedUInt<26, 6>(N->getSExtValue());}]>; +def u3_0ImmOperand : AsmOperandClass { let Name = "u3_0Imm"; let RenderMethod = "addImmOperands"; } +def u3_0Imm : Operand { let ParserMatchClass = u3_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +defm u3_0ImmPred : ImmOpPred<[{ return isShiftedUInt<3, 0>(N->getSExtValue());}]>; +def u3_1ImmOperand : AsmOperandClass { let Name = "u3_1Imm"; let RenderMethod = "addImmOperands"; } +def u3_1Imm : Operand { let ParserMatchClass = u3_1ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +defm u3_1ImmPred : ImmOpPred<[{ return isShiftedUInt<3, 1>(N->getSExtValue());}]>; +def u4_0ImmOperand : AsmOperandClass { let Name = "u4_0Imm"; let RenderMethod = "addImmOperands"; } +def u4_0Imm : Operand { let ParserMatchClass = u4_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +defm u4_0ImmPred : ImmOpPred<[{ return isShiftedUInt<4, 0>(N->getSExtValue());}]>; +def u4_2ImmOperand : AsmOperandClass { let Name = "u4_2Imm"; let RenderMethod = "addImmOperands"; } +def u4_2Imm : Operand { let ParserMatchClass = u4_2ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +defm u4_2ImmPred : ImmOpPred<[{ return isShiftedUInt<4, 2>(N->getSExtValue());}]>; +def u5_0ImmOperand : AsmOperandClass { let Name = "u5_0Imm"; let RenderMethod = "addImmOperands"; } +def u5_0Imm : Operand { let ParserMatchClass = u5_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +defm u5_0ImmPred : ImmOpPred<[{ return isShiftedUInt<5, 0>(N->getSExtValue());}]>; +def u5_2ImmOperand : AsmOperandClass { let Name = "u5_2Imm"; let RenderMethod = "addImmOperands"; } +def u5_2Imm : Operand { let ParserMatchClass = u5_2ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +defm u5_2ImmPred : ImmOpPred<[{ return isShiftedUInt<5, 2>(N->getSExtValue());}]>; +def u5_3ImmOperand : AsmOperandClass { let Name = "u5_3Imm"; let RenderMethod = "addImmOperands"; } +def u5_3Imm : Operand { let ParserMatchClass = u5_3ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +defm u5_3ImmPred : ImmOpPred<[{ return isShiftedUInt<5, 3>(N->getSExtValue());}]>; +def u6_0ImmOperand : AsmOperandClass { let Name = "u6_0Imm"; let RenderMethod = "addImmOperands"; } +def u6_0Imm : Operand { let ParserMatchClass = u6_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +defm u6_0ImmPred : ImmOpPred<[{ return isShiftedUInt<6, 0>(N->getSExtValue());}]>; +def u6_1ImmOperand : AsmOperandClass { let Name = "u6_1Imm"; let RenderMethod = "addImmOperands"; } +def u6_1Imm : Operand { let ParserMatchClass = u6_1ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +defm u6_1ImmPred : ImmOpPred<[{ return isShiftedUInt<6, 1>(N->getSExtValue());}]>; +def u31_1ImmOperand : AsmOperandClass { let Name = "u31_1Imm"; let RenderMethod = "addImmOperands"; } +def u31_1Imm : Operand { let ParserMatchClass = u31_1ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +defm u31_1ImmPred : ImmOpPred<[{ return isShiftedUInt<32, 1>(N->getSExtValue());}]>; +def u6_2ImmOperand : AsmOperandClass { let Name = "u6_2Imm"; let RenderMethod = "addImmOperands"; } +def u6_2Imm : Operand { let ParserMatchClass = u6_2ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +defm u6_2ImmPred : ImmOpPred<[{ return isShiftedUInt<6, 2>(N->getSExtValue());}]>; +def u30_2ImmOperand : AsmOperandClass { let Name = "u30_2Imm"; let RenderMethod = "addImmOperands"; } +def u30_2Imm : Operand { let ParserMatchClass = u30_2ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +defm u30_2ImmPred : ImmOpPred<[{ return isShiftedUInt<32, 2>(N->getSExtValue());}]>; +def u29_3ImmOperand : AsmOperandClass { let Name = "u29_3Imm"; let RenderMethod = "addImmOperands"; } +def u29_3Imm : Operand { let ParserMatchClass = u29_3ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +defm u29_3ImmPred : ImmOpPred<[{ return isShiftedUInt<32, 3>(N->getSExtValue());}]>; +def u7_0ImmOperand : AsmOperandClass { let Name = "u7_0Imm"; let RenderMethod = "addImmOperands"; } +def u7_0Imm : Operand { let ParserMatchClass = u7_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +defm u7_0ImmPred : ImmOpPred<[{ return isShiftedUInt<7, 0>(N->getSExtValue());}]>; +def u8_0ImmOperand : AsmOperandClass { let Name = "u8_0Imm"; let RenderMethod = "addImmOperands"; } +def u8_0Imm : Operand { let ParserMatchClass = u8_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +defm u8_0ImmPred : ImmOpPred<[{ return isShiftedUInt<8, 0>(N->getSExtValue());}]>; diff --git a/lib/Target/Hexagon/HexagonDepTimingClasses.h b/lib/Target/Hexagon/HexagonDepTimingClasses.h index dba39232433..1afe0f00e2b 100644 --- a/lib/Target/Hexagon/HexagonDepTimingClasses.h +++ b/lib/Target/Hexagon/HexagonDepTimingClasses.h @@ -95,6 +95,16 @@ inline bool is_TC2(unsigned SchedClass) { } } +inline bool is_TC2early(unsigned SchedClass) { + switch (SchedClass) { + case Hexagon::Sched::tc_45f9d1be: + case Hexagon::Sched::tc_a4ee89db: + return true; + default: + return false; + } +} + inline bool is_TC3x(unsigned SchedClass) { switch (SchedClass) { case Hexagon::Sched::tc_01e1be3b: @@ -126,16 +136,6 @@ inline bool is_TC3x(unsigned SchedClass) { } } -inline bool is_TC2early(unsigned SchedClass) { - switch (SchedClass) { - case Hexagon::Sched::tc_45f9d1be: - case Hexagon::Sched::tc_a4ee89db: - return true; - default: - return false; - } -} - inline bool is_TC4x(unsigned SchedClass) { switch (SchedClass) { case Hexagon::Sched::tc_02fe1c65: diff --git a/lib/Target/Hexagon/HexagonSchedule.td b/lib/Target/Hexagon/HexagonSchedule.td index 5efd02ada54..88d775f16a7 100644 --- a/lib/Target/Hexagon/HexagonSchedule.td +++ b/lib/Target/Hexagon/HexagonSchedule.td @@ -68,3 +68,4 @@ include "HexagonScheduleV65.td" include "HexagonScheduleV66.td" include "HexagonScheduleV67.td" include "HexagonScheduleV67T.td" +include "HexagonScheduleV68.td" diff --git a/lib/Target/Hexagon/HexagonScheduleV68.td b/lib/Target/Hexagon/HexagonScheduleV68.td new file mode 100644 index 00000000000..fefc1301f33 --- /dev/null +++ b/lib/Target/Hexagon/HexagonScheduleV68.td @@ -0,0 +1,38 @@ +//=-HexagonScheduleV68.td - HexagonV68 Scheduling Definitions *- tablegen -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// +// ScalarItin and HVXItin contain some old itineraries +// still used by a handful of instructions. Hopefully, we will be able +// to get rid of them soon. +def HexagonV68ItinList : DepScalarItinV68, ScalarItin, + DepHVXItinV68, HVXItin, PseudoItin { + list ItinList = + !listconcat(DepScalarItinV68_list, ScalarItin_list, + DepHVXItinV68_list, HVXItin_list, PseudoItin_list); +} + +def HexagonItinerariesV68 : + ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP, + CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1, + CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL, + CVI_ALL_NOMEM, CVI_ZW], + [Hex_FWD, HVX_FWD], + HexagonV68ItinList.ItinList>; + +def HexagonModelV68 : SchedMachineModel { + // Max issue per cycle == bundle width. + let IssueWidth = 4; + let Itineraries = HexagonItinerariesV68; + let LoadLatency = 1; + let CompleteModel = 0; +} + +//===----------------------------------------------------------------------===// +// Hexagon V68 Resource Definitions - +//===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/HexagonSubtarget.h b/lib/Target/Hexagon/HexagonSubtarget.h index 7b7fb8d04f4..5d5a3c48858 100644 --- a/lib/Target/Hexagon/HexagonSubtarget.h +++ b/lib/Target/Hexagon/HexagonSubtarget.h @@ -179,6 +179,12 @@ public: bool hasV67OpsOnly() const { return getHexagonArchVersion() == Hexagon::ArchEnum::V67; } + bool hasV68Ops() const { + return getHexagonArchVersion() >= Hexagon::ArchEnum::V68; + } + bool hasV68OpsOnly() const { + return getHexagonArchVersion() == Hexagon::ArchEnum::V68; + } bool useAudioOps() const { return UseAudioOps; } bool useCompound() const { return UseCompound; } @@ -212,6 +218,9 @@ public: bool useHVXV67Ops() const { return HexagonHVXVersion >= Hexagon::ArchEnum::V67; } + bool useHVXV68Ops() const { + return HexagonHVXVersion >= Hexagon::ArchEnum::V68; + } bool useHVX128BOps() const { return useHVXOps() && UseHVX128BOps; } bool useHVX64BOps() const { return useHVXOps() && UseHVX64BOps; } diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp index 5e4138ae6e0..32b0c610d63 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp @@ -78,6 +78,8 @@ cl::opt MV67("mv67", cl::Hidden, cl::desc("Build for Hexagon V67"), cl::init(false)); cl::opt MV67T("mv67t", cl::Hidden, cl::desc("Build for Hexagon V67T"), cl::init(false)); +cl::opt MV68("mv68", cl::Hidden, cl::desc("Build for Hexagon V68"), + cl::init(false)); cl::opt EnableHVX("mhvx", @@ -88,6 +90,7 @@ cl::opt clEnumValN(Hexagon::ArchEnum::V65, "v65", "Build for HVX v65"), clEnumValN(Hexagon::ArchEnum::V66, "v66", "Build for HVX v66"), clEnumValN(Hexagon::ArchEnum::V67, "v67", "Build for HVX v67"), + clEnumValN(Hexagon::ArchEnum::V68, "v68", "Build for HVX v68"), // Sentinel for no value specified. clEnumValN(Hexagon::ArchEnum::Generic, "", "")), // Sentinel for flag not present. @@ -118,6 +121,8 @@ static StringRef HexagonGetArchVariant() { return "hexagonv67"; if (MV67T) return "hexagonv67t"; + if (MV68) + return "hexagonv68"; return ""; } @@ -363,6 +368,9 @@ std::string selectHexagonFS(StringRef CPU, StringRef FS) { case Hexagon::ArchEnum::V67: Result.push_back("+hvxv67"); break; + case Hexagon::ArchEnum::V68: + Result.push_back("+hvxv68"); + break; case Hexagon::ArchEnum::Generic:{ Result.push_back(StringSwitch(CPU) .Case("hexagonv60", "+hvxv60") @@ -370,7 +378,8 @@ std::string selectHexagonFS(StringRef CPU, StringRef FS) { .Case("hexagonv65", "+hvxv65") .Case("hexagonv66", "+hvxv66") .Case("hexagonv67", "+hvxv67") - .Case("hexagonv67t", "+hvxv67")); + .Case("hexagonv67t", "+hvxv67") + .Case("hexagonv68", "+hvxv68")); break; } case Hexagon::ArchEnum::NoArch: @@ -413,8 +422,8 @@ FeatureBitset Hexagon_MC::completeHVXFeatures(const FeatureBitset &S) { // turns on hvxvNN, corresponding to the existing ArchVNN. FeatureBitset FB = S; unsigned CpuArch = ArchV5; - for (unsigned F : {ArchV67, ArchV66, ArchV65, ArchV62, ArchV60, ArchV55, - ArchV5}) { + for (unsigned F : {ArchV68, ArchV67, ArchV66, ArchV65, ArchV62, ArchV60, + ArchV55, ArchV5}) { if (!FB.test(F)) continue; CpuArch = F; @@ -429,7 +438,7 @@ FeatureBitset Hexagon_MC::completeHVXFeatures(const FeatureBitset &S) { } bool HasHvxVer = false; for (unsigned F : {ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, - ExtensionHVXV66, ExtensionHVXV67}) { + ExtensionHVXV66, ExtensionHVXV67, ExtensionHVXV68}) { if (!FB.test(F)) continue; HasHvxVer = true; @@ -442,6 +451,9 @@ FeatureBitset Hexagon_MC::completeHVXFeatures(const FeatureBitset &S) { // HasHvxVer is false, and UseHvx is true. switch (CpuArch) { + case ArchV68: + FB.set(ExtensionHVXV68); + LLVM_FALLTHROUGH; case ArchV67: FB.set(ExtensionHVXV67); LLVM_FALLTHROUGH; @@ -525,6 +537,7 @@ unsigned Hexagon_MC::GetELFFlags(const MCSubtargetInfo &STI) { {"hexagonv66", ELF::EF_HEXAGON_MACH_V66}, {"hexagonv67", ELF::EF_HEXAGON_MACH_V67}, {"hexagonv67t", ELF::EF_HEXAGON_MACH_V67T}, + {"hexagonv68", ELF::EF_HEXAGON_MACH_V68}, }; auto F = ElfFlags.find(STI.getCPU());