mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-22 02:33:06 +01:00
[ARM][LowOverheadLoops] Allow all MVE instrs.
We have a whitelist of instructions that we allow when tail predicating, since these are trivial ones that we've deemed need no special handling. Now change ARMLowOverheadLoops to allow the non-trivial instructions if they're contained within a valid VPT block. Since a valid block is one that is predicated upon the VCTP so we know that these non-trivial instructions will still behave as expected once the implicit predication is used instead. This also fixes a previous test failure. Differential Revision: https://reviews.llvm.org/D72509
This commit is contained in:
Sam Parker
parent
c3fc55b29b
commit
66428b5494
@ -138,28 +138,13 @@ namespace {
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MF = ML->getHeader()->getParent();
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}
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bool RecordVPTBlocks(MachineInstr *MI);
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// If this is an MVE instruction, check that we know how to use tail
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// predication with it.
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// predication with it. Record VPT blocks and return whether the
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// instruction is valid for tail predication.
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bool ValidateMVEInst(MachineInstr *MI);
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void AnalyseMVEInst(MachineInstr *MI) {
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if (CannotTailPredicate)
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return;
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if (!RecordVPTBlocks(MI)) {
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CannotTailPredicate = true;
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return;
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}
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const MCInstrDesc &MCID = MI->getDesc();
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uint64_t Flags = MCID.TSFlags;
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if ((Flags & ARMII::DomainMask) != ARMII::DomainMVE)
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return;
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if ((Flags & ARMII::ValidForTailPredication) == 0) {
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LLVM_DEBUG(dbgs() << "ARM Loops: Can't tail predicate: " << *MI);
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CannotTailPredicate = true;
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}
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CannotTailPredicate = !ValidateMVEInst(MI);
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}
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bool IsTailPredicationLegal() const {
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@ -495,7 +480,7 @@ void LowOverheadLoop::CheckLegality(ARMBasicBlockUtils *BBUtils,
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dbgs() << "ARM Loops: Couldn't validate tail predicate.\n");
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}
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bool LowOverheadLoop::RecordVPTBlocks(MachineInstr* MI) {
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bool LowOverheadLoop::ValidateMVEInst(MachineInstr* MI) {
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if (CannotTailPredicate)
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return false;
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@ -551,6 +536,18 @@ bool LowOverheadLoop::RecordVPTBlocks(MachineInstr* MI) {
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return false;
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}
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uint64_t Flags = MCID.TSFlags;
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if ((Flags & ARMII::DomainMask) != ARMII::DomainMVE)
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return true;
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// If we find an instruction that has been marked as not valid for tail
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// predication, only allow the instruction if it's contained within a valid
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// VPT block.
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if ((Flags & ARMII::ValidForTailPredication) == 0 && !IsUse) {
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LLVM_DEBUG(dbgs() << "ARM Loops: Can't tail predicate: " << *MI);
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return false;
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}
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return true;
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}
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255
test/CodeGen/Thumb2/LowOverheadLoops/add_reduce.mir
Normal file
255
test/CodeGen/Thumb2/LowOverheadLoops/add_reduce.mir
Normal file
@ -0,0 +1,255 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s
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--- |
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define hidden i32 @max_min_add_reduce(i8* %input_1_vect, i8* %input_2_vect, i32 %input_1_offset, i32 %input_2_offset, i32* %output, i32 %out_offset, i32 %out_mult, i32 %out_shift, i32 %out_activation_min, i32 %out_activation_max, i32 %block_size) local_unnamed_addr #0 {
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entry:
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%add = add i32 %block_size, 3
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%div = lshr i32 %add, 2
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%0 = call i1 @llvm.test.set.loop.iterations.i32(i32 %div)
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br i1 %0, label %for.body.lr.ph, label %for.cond.cleanup
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for.body.lr.ph: ; preds = %entry
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%.splatinsert.i41 = insertelement <4 x i32> undef, i32 %out_activation_min, i32 0
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%.splat.i42 = shufflevector <4 x i32> %.splatinsert.i41, <4 x i32> undef, <4 x i32> zeroinitializer
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%.splatinsert.i = insertelement <4 x i32> undef, i32 %out_activation_max, i32 0
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%.splat.i = shufflevector <4 x i32> %.splatinsert.i, <4 x i32> undef, <4 x i32> zeroinitializer
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%scevgep = getelementptr i32, i32* %output, i32 -1
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br label %for.body
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for.cond.cleanup: ; preds = %for.body, %entry
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ret i32 0
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for.body: ; preds = %for.body, %for.body.lr.ph
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%lsr.iv3 = phi i32 [ %lsr.iv.next, %for.body ], [ %div, %for.body.lr.ph ]
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%lsr.iv = phi i32* [ %scevgep1, %for.body ], [ %scevgep, %for.body.lr.ph ]
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%input_1_vect.addr.052 = phi i8* [ %input_1_vect, %for.body.lr.ph ], [ %add.ptr, %for.body ]
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%input_2_vect.addr.051 = phi i8* [ %input_2_vect, %for.body.lr.ph ], [ %add.ptr14, %for.body ]
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%num_elements.049 = phi i32 [ %block_size, %for.body.lr.ph ], [ %sub, %for.body ]
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%input_2_cast = bitcast i8* %input_2_vect.addr.051 to <4 x i32>*
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%input_1_cast = bitcast i8* %input_1_vect.addr.052 to <4 x i32>*
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%scevgep2 = getelementptr i32, i32* %lsr.iv, i32 1
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%pred = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %num_elements.049)
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%load.1 = tail call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %input_1_cast, i32 4, <4 x i1> %pred, <4 x i32> undef)
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%insert.input_1_offset = insertelement <4 x i32> undef, i32 %input_1_offset, i32 0
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%splat.input_1_offset = shufflevector <4 x i32> %insert.input_1_offset, <4 x i32> undef, <4 x i32> zeroinitializer
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%insert.input_2_offset = insertelement <4 x i32> undef, i32 %input_2_offset, i32 0
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%splat.input_2_offset = shufflevector <4 x i32> %insert.input_2_offset, <4 x i32> undef, <4 x i32> zeroinitializer
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%add.1 = add <4 x i32> %load.1, %splat.input_1_offset
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%load.2 = tail call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %input_2_cast, i32 4, <4 x i1> %pred, <4 x i32> undef)
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%add.2 = add <4 x i32> %load.2, %splat.input_2_offset
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%mul = mul <4 x i32> %add.1, %add.2
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%insert.output = insertelement <4 x i32> undef, i32 %out_offset, i32 0
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%splat.output = shufflevector <4 x i32> %insert.output, <4 x i32> undef, <4 x i32> zeroinitializer
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%add7 = add <4 x i32> %mul, %splat.output
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%max = tail call <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32> %add7, <4 x i32> %.splat.i42, i32 1, <4 x i1> %pred, <4 x i32> undef)
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%min = tail call <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32> %max, <4 x i32> %.splat.i, i32 1, <4 x i1> %pred, <4 x i32> undef)
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%reduce = tail call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %min)
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store i32 %reduce, i32* %scevgep2
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%add.ptr = getelementptr inbounds i8, i8* %input_1_vect.addr.052, i32 4
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%add.ptr14 = getelementptr inbounds i8, i8* %input_2_vect.addr.051, i32 4
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%sub = add i32 %num_elements.049, -4
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%iv.next = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv3, i32 1)
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%cmp = icmp ne i32 %iv.next, 0
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%scevgep1 = getelementptr i32, i32* %lsr.iv, i32 1
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%lsr.iv.next = add i32 %lsr.iv3, -1
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br i1 %cmp, label %for.body, label %for.cond.cleanup
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}
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declare <4 x i1> @llvm.arm.mve.vctp32(i32) #1
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declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>) #2
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declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>) #3
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declare <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
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declare <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
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declare i1 @llvm.test.set.loop.iterations.i32(i32) #4
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declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #4
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declare i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32>) #5
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...
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---
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name: max_min_add_reduce
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alignment: 2
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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registers: []
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liveins:
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- { reg: '$r0', virtual-reg: '' }
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- { reg: '$r1', virtual-reg: '' }
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- { reg: '$r2', virtual-reg: '' }
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- { reg: '$r3', virtual-reg: '' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 24
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offsetAdjustment: 0
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maxAlignment: 4
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 0
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack:
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- { id: 0, type: default, offset: 24, size: 4, alignment: 8, stack-id: default,
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isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 1, type: default, offset: 20, size: 4, alignment: 4, stack-id: default,
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isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 2, type: default, offset: 16, size: 4, alignment: 8, stack-id: default,
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isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 3, type: default, offset: 12, size: 4, alignment: 4, stack-id: default,
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isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 4, type: default, offset: 8, size: 4, alignment: 8, stack-id: default,
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isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 5, type: default, offset: 4, size: 4, alignment: 4, stack-id: default,
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isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 6, type: default, offset: 0, size: 4, alignment: 8, stack-id: default,
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isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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stack:
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- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r8', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r6', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 4, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 5, name: '', type: spill-slot, offset: -24, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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callSites: []
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constants: []
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machineFunctionInfo: {}
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body: |
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; CHECK-LABEL: name: max_min_add_reduce
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; CHECK: bb.0.entry:
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; CHECK: successors: %bb.1(0x40000000), %bb.3(0x40000000)
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; CHECK: liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $lr
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; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $lr
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; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 24
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; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
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; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -8
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; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -12
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; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -16
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; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -20
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; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -24
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; CHECK: renamable $r12 = t2LDRi12 $sp, 48, 14, $noreg :: (load 4 from %fixed-stack.6, align 8)
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; CHECK: renamable $r5 = t2ADDri renamable $r12, 3, 14, $noreg, $noreg
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; CHECK: renamable $r7, dead $cpsr = tLSRri killed renamable $r5, 2, 14, $noreg
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; CHECK: $lr = t2WLS renamable $r7, %bb.3
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; CHECK: bb.1.for.body.lr.ph:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: liveins: $r0, $r1, $r2, $r3, $r7, $r12
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; CHECK: $r6, $r5 = t2LDRDi8 $sp, 40, 14, $noreg :: (load 4 from %fixed-stack.4, align 8), (load 4 from %fixed-stack.5)
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; CHECK: $r4 = tMOVr killed $r7, 14, $noreg
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; CHECK: $r7, $r8 = t2LDRDi8 $sp, 24, 14, $noreg :: (load 4 from %fixed-stack.0, align 8), (load 4 from %fixed-stack.1)
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; CHECK: renamable $q0 = MVE_VDUP32 killed renamable $r5, 0, $noreg, undef renamable $q0
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; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r6, 0, $noreg, undef renamable $q1
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; CHECK: renamable $r5, dead $cpsr = tSUBi3 killed renamable $r7, 4, 14, $noreg
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; CHECK: bb.2.for.body:
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; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
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; CHECK: liveins: $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r5, $r8, $r12
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; CHECK: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg
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; CHECK: MVE_VPST 8, implicit $vpr
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; CHECK: renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 4, 1, renamable $vpr :: (load 16 from %ir.input_2_cast, align 4)
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; CHECK: MVE_VPST 8, implicit $vpr
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; CHECK: renamable $r0, renamable $q3 = MVE_VLDRWU32_post killed renamable $r0, 4, 1, renamable $vpr :: (load 16 from %ir.input_1_cast, align 4)
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; CHECK: renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r3, 0, $noreg, undef renamable $q2
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; CHECK: renamable $q3 = MVE_VADD_qr_i32 killed renamable $q3, renamable $r2, 0, $noreg, undef renamable $q3
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; CHECK: $lr = tMOVr $r4, 14, $noreg
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; CHECK: renamable $q2 = MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2
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; CHECK: renamable $r4, dead $cpsr = tSUBi8 killed $r4, 1, 14, $noreg
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; CHECK: renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r8, 0, $noreg, undef renamable $q2
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; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg
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; CHECK: MVE_VPST 4, implicit $vpr
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; CHECK: renamable $q2 = MVE_VMAXu32 killed renamable $q2, renamable $q1, 1, renamable $vpr, undef renamable $q2
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; CHECK: renamable $q2 = MVE_VMINu32 killed renamable $q2, renamable $q0, 1, killed renamable $vpr, undef renamable $q2
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; CHECK: renamable $r6 = MVE_VADDVu32no_acc killed renamable $q2, 0, $noreg
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; CHECK: early-clobber renamable $r5 = t2STR_PRE killed renamable $r6, killed renamable $r5, 4, 14, $noreg :: (store 4 into %ir.scevgep2)
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; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
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; CHECK: bb.3.for.cond.cleanup:
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; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg
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; CHECK: $sp = t2LDMIA_RET $sp, 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $pc, implicit killed $r0
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bb.0.entry:
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successors: %bb.1(0x40000000), %bb.3(0x40000000)
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liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $lr
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$sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $lr
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frame-setup CFI_INSTRUCTION def_cfa_offset 24
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frame-setup CFI_INSTRUCTION offset $lr, -4
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frame-setup CFI_INSTRUCTION offset $r8, -8
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frame-setup CFI_INSTRUCTION offset $r7, -12
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frame-setup CFI_INSTRUCTION offset $r6, -16
|
||||
frame-setup CFI_INSTRUCTION offset $r5, -20
|
||||
frame-setup CFI_INSTRUCTION offset $r4, -24
|
||||
renamable $r12 = t2LDRi12 $sp, 48, 14, $noreg :: (load 4 from %fixed-stack.0, align 8)
|
||||
renamable $r5 = t2ADDri renamable $r12, 3, 14, $noreg, $noreg
|
||||
renamable $r7, dead $cpsr = tLSRri killed renamable $r5, 2, 14, $noreg
|
||||
t2WhileLoopStart renamable $r7, %bb.3, implicit-def dead $cpsr
|
||||
tB %bb.1, 14, $noreg
|
||||
|
||||
bb.1.for.body.lr.ph:
|
||||
successors: %bb.2(0x80000000)
|
||||
liveins: $r0, $r1, $r2, $r3, $r7, $r12
|
||||
|
||||
$r6, $r5 = t2LDRDi8 $sp, 40, 14, $noreg :: (load 4 from %fixed-stack.2, align 8), (load 4 from %fixed-stack.1)
|
||||
$r4 = tMOVr killed $r7, 14, $noreg
|
||||
$r7, $r8 = t2LDRDi8 $sp, 24, 14, $noreg :: (load 4 from %fixed-stack.6, align 8), (load 4 from %fixed-stack.5)
|
||||
renamable $q0 = MVE_VDUP32 killed renamable $r5, 0, $noreg, undef renamable $q0
|
||||
renamable $q1 = MVE_VDUP32 killed renamable $r6, 0, $noreg, undef renamable $q1
|
||||
renamable $r5, dead $cpsr = tSUBi3 killed renamable $r7, 4, 14, $noreg
|
||||
|
||||
bb.2.for.body:
|
||||
successors: %bb.2(0x7c000000), %bb.3(0x04000000)
|
||||
liveins: $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r5, $r8, $r12
|
||||
|
||||
renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg
|
||||
MVE_VPST 8, implicit $vpr
|
||||
renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 4, 1, renamable $vpr :: (load 16 from %ir.input_2_cast, align 4)
|
||||
MVE_VPST 8, implicit $vpr
|
||||
renamable $r0, renamable $q3 = MVE_VLDRWU32_post killed renamable $r0, 4, 1, renamable $vpr :: (load 16 from %ir.input_1_cast, align 4)
|
||||
renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r3, 0, $noreg, undef renamable $q2
|
||||
renamable $q3 = MVE_VADD_qr_i32 killed renamable $q3, renamable $r2, 0, $noreg, undef renamable $q3
|
||||
$lr = tMOVr $r4, 14, $noreg
|
||||
renamable $q2 = MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2
|
||||
renamable $r4, dead $cpsr = tSUBi8 killed $r4, 1, 14, $noreg
|
||||
renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r8, 0, $noreg, undef renamable $q2
|
||||
renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg
|
||||
MVE_VPST 4, implicit $vpr
|
||||
renamable $q2 = MVE_VMAXu32 killed renamable $q2, renamable $q1, 1, renamable $vpr, undef renamable $q2
|
||||
renamable $q2 = MVE_VMINu32 killed renamable $q2, renamable $q0, 1, killed renamable $vpr, undef renamable $q2
|
||||
renamable $r6 = MVE_VADDVu32no_acc killed renamable $q2, 0, $noreg
|
||||
early-clobber renamable $r5 = t2STR_PRE killed renamable $r6, killed renamable $r5, 4, 14, $noreg :: (store 4 into %ir.scevgep2)
|
||||
renamable $lr = t2LoopDec killed renamable $lr, 1
|
||||
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
|
||||
tB %bb.3, 14, $noreg
|
||||
|
||||
bb.3.for.cond.cleanup:
|
||||
$r0, dead $cpsr = tMOVi8 0, 14, $noreg
|
||||
$sp = t2LDMIA_RET $sp, 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $pc, implicit killed $r0
|
||||
|
||||
...
|
||||
239
test/CodeGen/Thumb2/LowOverheadLoops/vmldava_in_vpt.mir
Normal file
239
test/CodeGen/Thumb2/LowOverheadLoops/vmldava_in_vpt.mir
Normal file
@ -0,0 +1,239 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s
|
||||
|
||||
--- |
|
||||
define hidden i32 @vmldava_in_vpt(i8* %input_1_vect, i8* %input_2_vect, i32 %input_1_offset, i32 %input_2_offset, i32 %out_offset, i32 %out_mult, i32 %out_shift, i32 %out_activation_min, i32 %out_activation_max, i32 %block_size) local_unnamed_addr #0 {
|
||||
entry:
|
||||
%add = add i32 %block_size, 3
|
||||
%div = lshr i32 %add, 2
|
||||
%0 = call i1 @llvm.test.set.loop.iterations.i32(i32 %div)
|
||||
br i1 %0, label %for.body.lr.ph, label %for.cond.cleanup
|
||||
|
||||
for.body.lr.ph: ; preds = %entry
|
||||
%.splatinsert.i41 = insertelement <4 x i32> undef, i32 %out_activation_min, i32 0
|
||||
%.splat.i42 = shufflevector <4 x i32> %.splatinsert.i41, <4 x i32> undef, <4 x i32> zeroinitializer
|
||||
%.splatinsert.i = insertelement <4 x i32> undef, i32 %out_activation_max, i32 0
|
||||
%.splat.i = shufflevector <4 x i32> %.splatinsert.i, <4 x i32> undef, <4 x i32> zeroinitializer
|
||||
br label %for.body
|
||||
|
||||
for.cond.cleanup: ; preds = %for.body, %entry
|
||||
%res = phi i32 [ 0, %entry ], [ %acc.next, %for.body ]
|
||||
ret i32 %res
|
||||
|
||||
for.body: ; preds = %for.body, %for.body.lr.ph
|
||||
%lsr.iv = phi i32 [ %lsr.iv.next, %for.body ], [ %div, %for.body.lr.ph ]
|
||||
%input_1_vect.addr.052 = phi i8* [ %input_1_vect, %for.body.lr.ph ], [ %add.ptr, %for.body ]
|
||||
%input_2_vect.addr.051 = phi i8* [ %input_2_vect, %for.body.lr.ph ], [ %add.ptr14, %for.body ]
|
||||
%num_elements.049 = phi i32 [ %block_size, %for.body.lr.ph ], [ %sub, %for.body ]
|
||||
%acc = phi i32 [ 0, %for.body.lr.ph ], [ %acc.next, %for.body ]
|
||||
%input_2_cast = bitcast i8* %input_2_vect.addr.051 to <4 x i32>*
|
||||
%input_1_cast = bitcast i8* %input_1_vect.addr.052 to <4 x i32>*
|
||||
%pred = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %num_elements.049)
|
||||
%load.1 = tail call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %input_1_cast, i32 4, <4 x i1> %pred, <4 x i32> undef)
|
||||
%insert.input_1_offset = insertelement <4 x i32> undef, i32 %input_1_offset, i32 0
|
||||
%splat.input_1_offset = shufflevector <4 x i32> %insert.input_1_offset, <4 x i32> undef, <4 x i32> zeroinitializer
|
||||
%insert.input_2_offset = insertelement <4 x i32> undef, i32 %input_2_offset, i32 0
|
||||
%splat.input_2_offset = shufflevector <4 x i32> %insert.input_2_offset, <4 x i32> undef, <4 x i32> zeroinitializer
|
||||
%add.1 = add <4 x i32> %load.1, %splat.input_1_offset
|
||||
%load.2 = tail call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %input_2_cast, i32 4, <4 x i1> %pred, <4 x i32> undef)
|
||||
%add.2 = add <4 x i32> %load.2, %splat.input_2_offset
|
||||
%mul = mul <4 x i32> %add.1, %add.2
|
||||
%insert.output = insertelement <4 x i32> undef, i32 %out_offset, i32 0
|
||||
%splat.output = shufflevector <4 x i32> %insert.output, <4 x i32> undef, <4 x i32> zeroinitializer
|
||||
%add7 = add <4 x i32> %mul, %splat.output
|
||||
%max = tail call <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32> %add7, <4 x i32> %.splat.i42, i32 1, <4 x i1> %pred, <4 x i32> undef)
|
||||
%min = tail call <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32> %max, <4 x i32> %.splat.i, i32 1, <4 x i1> %pred, <4 x i32> undef)
|
||||
%acc.next = call i32 @llvm.arm.mve.vmldava.predicated.v4i32.v4i1(i32 0, i32 0, i32 0, i32 %acc, <4 x i32> %min, <4 x i32> %max, <4 x i1> %pred)
|
||||
%add.ptr = getelementptr inbounds i8, i8* %input_1_vect.addr.052, i32 4
|
||||
%add.ptr14 = getelementptr inbounds i8, i8* %input_2_vect.addr.051, i32 4
|
||||
%sub = add i32 %num_elements.049, -4
|
||||
%iv.next = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv, i32 1)
|
||||
%cmp = icmp ne i32 %iv.next, 0
|
||||
%lsr.iv.next = add i32 %lsr.iv, -1
|
||||
br i1 %cmp, label %for.body, label %for.cond.cleanup
|
||||
}
|
||||
declare <4 x i1> @llvm.arm.mve.vctp32(i32) #1
|
||||
declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>) #2
|
||||
declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>) #3
|
||||
declare <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
|
||||
declare <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1
|
||||
declare i32 @llvm.arm.mve.vmldava.predicated.v4i32.v4i1(i32, i32, i32, i32, <4 x i32>, <4 x i32>, <4 x i1>) #1
|
||||
declare i1 @llvm.test.set.loop.iterations.i32(i32) #4
|
||||
declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #4
|
||||
...
|
||||
---
|
||||
name: vmldava_in_vpt
|
||||
alignment: 2
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
failedISel: false
|
||||
tracksRegLiveness: true
|
||||
hasWinCFI: false
|
||||
registers: []
|
||||
liveins:
|
||||
- { reg: '$r0', virtual-reg: '' }
|
||||
- { reg: '$r1', virtual-reg: '' }
|
||||
- { reg: '$r2', virtual-reg: '' }
|
||||
- { reg: '$r3', virtual-reg: '' }
|
||||
frameInfo:
|
||||
isFrameAddressTaken: false
|
||||
isReturnAddressTaken: false
|
||||
hasStackMap: false
|
||||
hasPatchPoint: false
|
||||
stackSize: 20
|
||||
offsetAdjustment: 0
|
||||
maxAlignment: 4
|
||||
adjustsStack: false
|
||||
hasCalls: false
|
||||
stackProtector: ''
|
||||
maxCallFrameSize: 0
|
||||
cvBytesOfCalleeSavedRegisters: 0
|
||||
hasOpaqueSPAdjustment: false
|
||||
hasVAStart: false
|
||||
hasMustTailInVarArgFunc: false
|
||||
localFrameSize: 0
|
||||
savePoint: ''
|
||||
restorePoint: ''
|
||||
fixedStack:
|
||||
- { id: 0, type: default, offset: 20, size: 4, alignment: 4, stack-id: default,
|
||||
isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
|
||||
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
|
||||
- { id: 1, type: default, offset: 16, size: 4, alignment: 8, stack-id: default,
|
||||
isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
|
||||
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
|
||||
- { id: 2, type: default, offset: 12, size: 4, alignment: 4, stack-id: default,
|
||||
isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
|
||||
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
|
||||
- { id: 3, type: default, offset: 8, size: 4, alignment: 8, stack-id: default,
|
||||
isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
|
||||
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
|
||||
- { id: 4, type: default, offset: 4, size: 4, alignment: 4, stack-id: default,
|
||||
isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
|
||||
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
|
||||
- { id: 5, type: default, offset: 0, size: 4, alignment: 8, stack-id: default,
|
||||
isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
|
||||
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
|
||||
stack:
|
||||
- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
|
||||
stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
|
||||
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
|
||||
- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
|
||||
stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
|
||||
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
|
||||
- { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
|
||||
stack-id: default, callee-saved-register: '$r6', callee-saved-restored: true,
|
||||
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
|
||||
- { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,
|
||||
stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true,
|
||||
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
|
||||
- { id: 4, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4,
|
||||
stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
|
||||
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
|
||||
callSites: []
|
||||
constants: []
|
||||
machineFunctionInfo: {}
|
||||
body: |
|
||||
; CHECK-LABEL: name: vmldava_in_vpt
|
||||
; CHECK: bb.0.entry:
|
||||
; CHECK: successors: %bb.1(0x40000000), %bb.3(0x40000000)
|
||||
; CHECK: liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $lr
|
||||
; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $lr, implicit-def $sp, implicit $sp
|
||||
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20
|
||||
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
|
||||
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
|
||||
; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12
|
||||
; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -16
|
||||
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -20
|
||||
; CHECK: renamable $r7 = tLDRspi $sp, 10, 14, $noreg :: (load 4 from %fixed-stack.5)
|
||||
; CHECK: renamable $r12 = t2MOVi 0, 14, $noreg, $noreg
|
||||
; CHECK: $lr = MVE_WLSTP_32 renamable $r7, %bb.3
|
||||
; CHECK: bb.1.for.body.lr.ph:
|
||||
; CHECK: successors: %bb.2(0x80000000)
|
||||
; CHECK: liveins: $r0, $r1, $r2, $r3, $r5, $r7
|
||||
; CHECK: $r6 = tMOVr killed $r5, 14, $noreg
|
||||
; CHECK: $r5, $r12 = t2LDRDi8 $sp, 32, 14, $noreg :: (load 4 from %fixed-stack.3), (load 4 from %fixed-stack.4, align 8)
|
||||
; CHECK: renamable $r4 = tLDRspi $sp, 5, 14, $noreg :: (load 4 from %fixed-stack.0, align 8)
|
||||
; CHECK: renamable $q0 = MVE_VDUP32 killed renamable $r12, 0, $noreg, undef renamable $q0
|
||||
; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r5, 0, $noreg, undef renamable $q1
|
||||
; CHECK: renamable $r12 = t2MOVi 0, 14, $noreg, $noreg
|
||||
; CHECK: bb.2.for.body:
|
||||
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
|
||||
; CHECK: liveins: $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r6, $r7, $r12
|
||||
; CHECK: renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 4, 0, $noreg :: (load 16 from %ir.input_2_cast, align 4)
|
||||
; CHECK: renamable $r0, renamable $q3 = MVE_VLDRWU32_post killed renamable $r0, 4, 0, $noreg :: (load 16 from %ir.input_1_cast, align 4)
|
||||
; CHECK: renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r3, 0, $noreg, undef renamable $q2
|
||||
; CHECK: renamable $q3 = MVE_VADD_qr_i32 killed renamable $q3, renamable $r2, 0, $noreg, undef renamable $q3
|
||||
; CHECK: $lr = tMOVr $r6, 14, $noreg
|
||||
; CHECK: renamable $q2 = MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2
|
||||
; CHECK: renamable $r6, dead $cpsr = tSUBi8 killed $r6, 1, 14, $noreg
|
||||
; CHECK: renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r4, 0, $noreg, undef renamable $q2
|
||||
; CHECK: renamable $q2 = MVE_VMAXu32 killed renamable $q2, renamable $q1, 0, $noreg, undef renamable $q2
|
||||
; CHECK: renamable $q3 = MVE_VMINu32 renamable $q2, renamable $q0, 0, $noreg, undef renamable $q3
|
||||
; CHECK: renamable $r12 = MVE_VMLADAVas32 killed renamable $r12, killed renamable $q3, killed renamable $q2, 0, killed $noreg
|
||||
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
|
||||
; CHECK: bb.3.for.cond.cleanup:
|
||||
; CHECK: liveins: $r12
|
||||
; CHECK: $r0 = tMOVr killed $r12, 14, $noreg
|
||||
; CHECK: tPOP_RET 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc, implicit killed $r0
|
||||
bb.0.entry:
|
||||
successors: %bb.1(0x40000000), %bb.3(0x40000000)
|
||||
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $lr
|
||||
|
||||
frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $lr, implicit-def $sp, implicit $sp
|
||||
frame-setup CFI_INSTRUCTION def_cfa_offset 20
|
||||
frame-setup CFI_INSTRUCTION offset $lr, -4
|
||||
frame-setup CFI_INSTRUCTION offset $r7, -8
|
||||
frame-setup CFI_INSTRUCTION offset $r6, -12
|
||||
frame-setup CFI_INSTRUCTION offset $r5, -16
|
||||
frame-setup CFI_INSTRUCTION offset $r4, -20
|
||||
renamable $r7 = tLDRspi $sp, 10, 14, $noreg :: (load 4 from %fixed-stack.0)
|
||||
renamable $r12 = t2MOVi 0, 14, $noreg, $noreg
|
||||
renamable $r4, dead $cpsr = tADDi3 renamable $r7, 3, 14, $noreg
|
||||
renamable $r5, dead $cpsr = tLSRri killed renamable $r4, 2, 14, $noreg
|
||||
t2WhileLoopStart renamable $r5, %bb.3, implicit-def dead $cpsr
|
||||
tB %bb.1, 14, $noreg
|
||||
|
||||
bb.1.for.body.lr.ph:
|
||||
successors: %bb.2(0x80000000)
|
||||
liveins: $r0, $r1, $r2, $r3, $r5, $r7
|
||||
|
||||
$r6 = tMOVr killed $r5, 14, $noreg
|
||||
$r5, $r12 = t2LDRDi8 $sp, 32, 14, $noreg :: (load 4 from %fixed-stack.2), (load 4 from %fixed-stack.1, align 8)
|
||||
renamable $r4 = tLDRspi $sp, 5, 14, $noreg :: (load 4 from %fixed-stack.5, align 8)
|
||||
renamable $q0 = MVE_VDUP32 killed renamable $r12, 0, $noreg, undef renamable $q0
|
||||
renamable $q1 = MVE_VDUP32 killed renamable $r5, 0, $noreg, undef renamable $q1
|
||||
renamable $r12 = t2MOVi 0, 14, $noreg, $noreg
|
||||
|
||||
bb.2.for.body:
|
||||
successors: %bb.2(0x7c000000), %bb.3(0x04000000)
|
||||
liveins: $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r6, $r7, $r12
|
||||
|
||||
renamable $vpr = MVE_VCTP32 renamable $r7, 0, $noreg
|
||||
MVE_VPST 8, implicit $vpr
|
||||
renamable $r1, renamable $q2 = MVE_VLDRWU32_post killed renamable $r1, 4, 1, renamable $vpr :: (load 16 from %ir.input_2_cast, align 4)
|
||||
MVE_VPST 8, implicit $vpr
|
||||
renamable $r0, renamable $q3 = MVE_VLDRWU32_post killed renamable $r0, 4, 1, renamable $vpr :: (load 16 from %ir.input_1_cast, align 4)
|
||||
renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r3, 0, $noreg, undef renamable $q2
|
||||
renamable $q3 = MVE_VADD_qr_i32 killed renamable $q3, renamable $r2, 0, $noreg, undef renamable $q3
|
||||
$lr = tMOVr $r6, 14, $noreg
|
||||
renamable $q2 = MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2
|
||||
renamable $r6, dead $cpsr = tSUBi8 killed $r6, 1, 14, $noreg
|
||||
renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r4, 0, $noreg, undef renamable $q2
|
||||
renamable $r7, dead $cpsr = tSUBi8 killed renamable $r7, 4, 14, $noreg
|
||||
MVE_VPST 2, implicit $vpr
|
||||
renamable $q2 = MVE_VMAXu32 killed renamable $q2, renamable $q1, 1, renamable $vpr, undef renamable $q2
|
||||
renamable $q3 = MVE_VMINu32 renamable $q2, renamable $q0, 1, renamable $vpr, undef renamable $q3
|
||||
renamable $r12 = MVE_VMLADAVas32 killed renamable $r12, killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr
|
||||
renamable $lr = t2LoopDec killed renamable $lr, 1
|
||||
t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
|
||||
tB %bb.3, 14, $noreg
|
||||
|
||||
bb.3.for.cond.cleanup:
|
||||
liveins: $r12
|
||||
|
||||
$r0 = tMOVr killed $r12, 14, $noreg
|
||||
tPOP_RET 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc, implicit killed $r0
|
||||
|
||||
...
|
||||
@ -302,8 +302,6 @@ TEST(MachineInstrValidTailPredication, IsCorrect) {
|
||||
case MVE_VORRIZ24v4i32:
|
||||
case MVE_VORRIZ8v4i32:
|
||||
case MVE_VORRIZ8v8i16:
|
||||
case MVE_VPNOT:
|
||||
case MVE_VPSEL:
|
||||
case MVE_VPST:
|
||||
case MVE_VQABSs16:
|
||||
case MVE_VQABSs32:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user