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[PowerPC][NFC] Testing ROTL of v1i128.
Summary: A bug is reported in bugzilla-45628, where the swap_with_shift case can’t be matched to a single HW instruction xxswapd as expected. In fact the case matches the idiom of rotate, but PPC doesn’t support ROTL v1i128. This is a NFC patch for testing ROTL with v1i128 at master. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D81073
This commit is contained in:
Esme-Yi
parent
1e218d6779
commit
668ef1d81b
385
test/CodeGen/PowerPC/pr45628.ll
Normal file
385
test/CodeGen/PowerPC/pr45628.ll
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@ -0,0 +1,385 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
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; RUN: -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck %s \
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; RUN: -check-prefix=CHECK-VSX
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; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
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; RUN: -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs -mattr=-vsx < %s | FileCheck %s \
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; RUN: -check-prefix=CHECK-NOVSX
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define <1 x i128> @rotl_64(<1 x i128> %num) {
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; CHECK-VSX-LABEL: rotl_64:
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; CHECK-VSX: # %bb.0: # %entry
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; CHECK-VSX-NEXT: addis r3, r2, .LCPI0_0@toc@ha
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; CHECK-VSX-NEXT: addi r3, r3, .LCPI0_0@toc@l
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; CHECK-VSX-NEXT: lxvx v3, 0, r3
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; CHECK-VSX-NEXT: vslo v4, v2, v3
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; CHECK-VSX-NEXT: vspltb v5, v3, 15
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; CHECK-VSX-NEXT: vsro v2, v2, v3
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; CHECK-VSX-NEXT: vsl v4, v4, v5
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; CHECK-VSX-NEXT: vsr v2, v2, v5
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; CHECK-VSX-NEXT: xxlor v2, v4, v2
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; CHECK-VSX-NEXT: blr
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;
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; CHECK-NOVSX-LABEL: rotl_64:
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; CHECK-NOVSX: # %bb.0: # %entry
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; CHECK-NOVSX-NEXT: addis r3, r2, .LCPI0_0@toc@ha
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; CHECK-NOVSX-NEXT: addi r3, r3, .LCPI0_0@toc@l
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; CHECK-NOVSX-NEXT: lvx v3, 0, r3
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; CHECK-NOVSX-NEXT: vslo v4, v2, v3
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; CHECK-NOVSX-NEXT: vspltb v5, v3, 15
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; CHECK-NOVSX-NEXT: vsro v2, v2, v3
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; CHECK-NOVSX-NEXT: vsl v4, v4, v5
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; CHECK-NOVSX-NEXT: vsr v2, v2, v5
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; CHECK-NOVSX-NEXT: vor v2, v4, v2
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; CHECK-NOVSX-NEXT: blr
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entry:
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%shl = shl <1 x i128> %num, <i128 64>
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%shr = lshr <1 x i128> %num, <i128 64>
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%or = or <1 x i128> %shl, %shr
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ret <1 x i128> %or
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}
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define <1 x i128> @rotl_32(<1 x i128> %num) {
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; CHECK-VSX-LABEL: rotl_32:
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; CHECK-VSX: # %bb.0: # %entry
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; CHECK-VSX-NEXT: addis r3, r2, .LCPI1_0@toc@ha
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; CHECK-VSX-NEXT: addi r3, r3, .LCPI1_0@toc@l
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; CHECK-VSX-NEXT: lxvx v3, 0, r3
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; CHECK-VSX-NEXT: addis r3, r2, .LCPI1_1@toc@ha
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; CHECK-VSX-NEXT: addi r3, r3, .LCPI1_1@toc@l
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; CHECK-VSX-NEXT: vslo v4, v2, v3
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; CHECK-VSX-NEXT: vspltb v3, v3, 15
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; CHECK-VSX-NEXT: vsl v3, v4, v3
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; CHECK-VSX-NEXT: lxvx v4, 0, r3
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; CHECK-VSX-NEXT: vsro v2, v2, v4
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; CHECK-VSX-NEXT: vspltb v4, v4, 15
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; CHECK-VSX-NEXT: vsr v2, v2, v4
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; CHECK-VSX-NEXT: xxlor v2, v3, v2
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; CHECK-VSX-NEXT: blr
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;
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; CHECK-NOVSX-LABEL: rotl_32:
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; CHECK-NOVSX: # %bb.0: # %entry
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; CHECK-NOVSX-NEXT: addis r3, r2, .LCPI1_0@toc@ha
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; CHECK-NOVSX-NEXT: addi r3, r3, .LCPI1_0@toc@l
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; CHECK-NOVSX-NEXT: lvx v3, 0, r3
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; CHECK-NOVSX-NEXT: addis r3, r2, .LCPI1_1@toc@ha
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; CHECK-NOVSX-NEXT: addi r3, r3, .LCPI1_1@toc@l
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; CHECK-NOVSX-NEXT: vslo v4, v2, v3
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; CHECK-NOVSX-NEXT: vspltb v3, v3, 15
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; CHECK-NOVSX-NEXT: vsl v3, v4, v3
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; CHECK-NOVSX-NEXT: lvx v4, 0, r3
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; CHECK-NOVSX-NEXT: vsro v2, v2, v4
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; CHECK-NOVSX-NEXT: vspltb v4, v4, 15
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; CHECK-NOVSX-NEXT: vsr v2, v2, v4
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; CHECK-NOVSX-NEXT: vor v2, v3, v2
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; CHECK-NOVSX-NEXT: blr
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entry:
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%shl = shl <1 x i128> %num, <i128 32>
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%shr = lshr <1 x i128> %num, <i128 96>
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%or = or <1 x i128> %shl, %shr
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ret <1 x i128> %or
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}
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define <1 x i128> @rotl_96(<1 x i128> %num) {
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; CHECK-VSX-LABEL: rotl_96:
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; CHECK-VSX: # %bb.0: # %entry
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; CHECK-VSX-NEXT: addis r3, r2, .LCPI2_0@toc@ha
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; CHECK-VSX-NEXT: addi r3, r3, .LCPI2_0@toc@l
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; CHECK-VSX-NEXT: lxvx v3, 0, r3
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; CHECK-VSX-NEXT: addis r3, r2, .LCPI2_1@toc@ha
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; CHECK-VSX-NEXT: addi r3, r3, .LCPI2_1@toc@l
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; CHECK-VSX-NEXT: vslo v4, v2, v3
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; CHECK-VSX-NEXT: vspltb v3, v3, 15
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; CHECK-VSX-NEXT: vsl v3, v4, v3
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; CHECK-VSX-NEXT: lxvx v4, 0, r3
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; CHECK-VSX-NEXT: vsro v2, v2, v4
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; CHECK-VSX-NEXT: vspltb v4, v4, 15
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; CHECK-VSX-NEXT: vsr v2, v2, v4
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; CHECK-VSX-NEXT: xxlor v2, v3, v2
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; CHECK-VSX-NEXT: blr
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;
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; CHECK-NOVSX-LABEL: rotl_96:
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; CHECK-NOVSX: # %bb.0: # %entry
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; CHECK-NOVSX-NEXT: addis r3, r2, .LCPI2_0@toc@ha
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; CHECK-NOVSX-NEXT: addi r3, r3, .LCPI2_0@toc@l
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; CHECK-NOVSX-NEXT: lvx v3, 0, r3
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; CHECK-NOVSX-NEXT: addis r3, r2, .LCPI2_1@toc@ha
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; CHECK-NOVSX-NEXT: addi r3, r3, .LCPI2_1@toc@l
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; CHECK-NOVSX-NEXT: vslo v4, v2, v3
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; CHECK-NOVSX-NEXT: vspltb v3, v3, 15
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; CHECK-NOVSX-NEXT: vsl v3, v4, v3
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; CHECK-NOVSX-NEXT: lvx v4, 0, r3
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; CHECK-NOVSX-NEXT: vsro v2, v2, v4
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; CHECK-NOVSX-NEXT: vspltb v4, v4, 15
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; CHECK-NOVSX-NEXT: vsr v2, v2, v4
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; CHECK-NOVSX-NEXT: vor v2, v3, v2
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; CHECK-NOVSX-NEXT: blr
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entry:
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%shl = shl <1 x i128> %num, <i128 96>
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%shr = lshr <1 x i128> %num, <i128 32>
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%or = or <1 x i128> %shl, %shr
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ret <1 x i128> %or
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}
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define <1 x i128> @rotl_16(<1 x i128> %num) {
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; CHECK-VSX-LABEL: rotl_16:
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; CHECK-VSX: # %bb.0: # %entry
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; CHECK-VSX-NEXT: addis r3, r2, .LCPI3_0@toc@ha
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; CHECK-VSX-NEXT: addi r3, r3, .LCPI3_0@toc@l
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; CHECK-VSX-NEXT: lxvx v3, 0, r3
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; CHECK-VSX-NEXT: addis r3, r2, .LCPI3_1@toc@ha
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; CHECK-VSX-NEXT: addi r3, r3, .LCPI3_1@toc@l
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; CHECK-VSX-NEXT: vslo v4, v2, v3
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; CHECK-VSX-NEXT: vspltb v3, v3, 15
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; CHECK-VSX-NEXT: vsl v3, v4, v3
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; CHECK-VSX-NEXT: lxvx v4, 0, r3
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; CHECK-VSX-NEXT: vsro v2, v2, v4
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; CHECK-VSX-NEXT: vspltb v4, v4, 15
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; CHECK-VSX-NEXT: vsr v2, v2, v4
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; CHECK-VSX-NEXT: xxlor v2, v3, v2
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; CHECK-VSX-NEXT: blr
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;
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; CHECK-NOVSX-LABEL: rotl_16:
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; CHECK-NOVSX: # %bb.0: # %entry
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; CHECK-NOVSX-NEXT: addis r3, r2, .LCPI3_0@toc@ha
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; CHECK-NOVSX-NEXT: addi r3, r3, .LCPI3_0@toc@l
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; CHECK-NOVSX-NEXT: lvx v3, 0, r3
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; CHECK-NOVSX-NEXT: addis r3, r2, .LCPI3_1@toc@ha
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; CHECK-NOVSX-NEXT: addi r3, r3, .LCPI3_1@toc@l
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; CHECK-NOVSX-NEXT: vslo v4, v2, v3
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; CHECK-NOVSX-NEXT: vspltb v3, v3, 15
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; CHECK-NOVSX-NEXT: vsl v3, v4, v3
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; CHECK-NOVSX-NEXT: lvx v4, 0, r3
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; CHECK-NOVSX-NEXT: vsro v2, v2, v4
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; CHECK-NOVSX-NEXT: vspltb v4, v4, 15
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; CHECK-NOVSX-NEXT: vsr v2, v2, v4
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; CHECK-NOVSX-NEXT: vor v2, v3, v2
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; CHECK-NOVSX-NEXT: blr
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entry:
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%shl = shl <1 x i128> %num, <i128 16>
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%shr = lshr <1 x i128> %num, <i128 112>
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%or = or <1 x i128> %shl, %shr
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ret <1 x i128> %or
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}
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define <1 x i128> @rotl_112(<1 x i128> %num) {
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; CHECK-VSX-LABEL: rotl_112:
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; CHECK-VSX: # %bb.0: # %entry
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; CHECK-VSX-NEXT: addis r3, r2, .LCPI4_0@toc@ha
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; CHECK-VSX-NEXT: addi r3, r3, .LCPI4_0@toc@l
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; CHECK-VSX-NEXT: lxvx v3, 0, r3
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; CHECK-VSX-NEXT: addis r3, r2, .LCPI4_1@toc@ha
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; CHECK-VSX-NEXT: addi r3, r3, .LCPI4_1@toc@l
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; CHECK-VSX-NEXT: vslo v4, v2, v3
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; CHECK-VSX-NEXT: vspltb v3, v3, 15
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; CHECK-VSX-NEXT: vsl v3, v4, v3
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; CHECK-VSX-NEXT: lxvx v4, 0, r3
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; CHECK-VSX-NEXT: vsro v2, v2, v4
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; CHECK-VSX-NEXT: vspltb v4, v4, 15
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; CHECK-VSX-NEXT: vsr v2, v2, v4
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; CHECK-VSX-NEXT: xxlor v2, v3, v2
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; CHECK-VSX-NEXT: blr
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;
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; CHECK-NOVSX-LABEL: rotl_112:
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; CHECK-NOVSX: # %bb.0: # %entry
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; CHECK-NOVSX-NEXT: addis r3, r2, .LCPI4_0@toc@ha
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; CHECK-NOVSX-NEXT: addi r3, r3, .LCPI4_0@toc@l
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; CHECK-NOVSX-NEXT: lvx v3, 0, r3
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; CHECK-NOVSX-NEXT: addis r3, r2, .LCPI4_1@toc@ha
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; CHECK-NOVSX-NEXT: addi r3, r3, .LCPI4_1@toc@l
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; CHECK-NOVSX-NEXT: vslo v4, v2, v3
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; CHECK-NOVSX-NEXT: vspltb v3, v3, 15
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; CHECK-NOVSX-NEXT: vsl v3, v4, v3
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; CHECK-NOVSX-NEXT: lvx v4, 0, r3
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; CHECK-NOVSX-NEXT: vsro v2, v2, v4
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; CHECK-NOVSX-NEXT: vspltb v4, v4, 15
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; CHECK-NOVSX-NEXT: vsr v2, v2, v4
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; CHECK-NOVSX-NEXT: vor v2, v3, v2
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; CHECK-NOVSX-NEXT: blr
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entry:
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%shl = shl <1 x i128> %num, <i128 112>
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%shr = lshr <1 x i128> %num, <i128 16>
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%or = or <1 x i128> %shl, %shr
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ret <1 x i128> %or
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}
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define <1 x i128> @rotl_8(<1 x i128> %num) {
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; CHECK-VSX-LABEL: rotl_8:
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; CHECK-VSX: # %bb.0: # %entry
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; CHECK-VSX-NEXT: addis r3, r2, .LCPI5_0@toc@ha
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; CHECK-VSX-NEXT: addi r3, r3, .LCPI5_0@toc@l
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; CHECK-VSX-NEXT: lxvx v3, 0, r3
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; CHECK-VSX-NEXT: addis r3, r2, .LCPI5_1@toc@ha
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; CHECK-VSX-NEXT: addi r3, r3, .LCPI5_1@toc@l
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; CHECK-VSX-NEXT: vslo v4, v2, v3
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; CHECK-VSX-NEXT: vspltb v3, v3, 15
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; CHECK-VSX-NEXT: vsl v3, v4, v3
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; CHECK-VSX-NEXT: lxvx v4, 0, r3
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; CHECK-VSX-NEXT: vsro v2, v2, v4
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; CHECK-VSX-NEXT: vspltb v4, v4, 15
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; CHECK-VSX-NEXT: vsr v2, v2, v4
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; CHECK-VSX-NEXT: xxlor v2, v3, v2
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; CHECK-VSX-NEXT: blr
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;
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; CHECK-NOVSX-LABEL: rotl_8:
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; CHECK-NOVSX: # %bb.0: # %entry
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; CHECK-NOVSX-NEXT: addis r3, r2, .LCPI5_0@toc@ha
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; CHECK-NOVSX-NEXT: addi r3, r3, .LCPI5_0@toc@l
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; CHECK-NOVSX-NEXT: lvx v3, 0, r3
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; CHECK-NOVSX-NEXT: addis r3, r2, .LCPI5_1@toc@ha
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; CHECK-NOVSX-NEXT: addi r3, r3, .LCPI5_1@toc@l
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; CHECK-NOVSX-NEXT: vslo v4, v2, v3
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; CHECK-NOVSX-NEXT: vspltb v3, v3, 15
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; CHECK-NOVSX-NEXT: vsl v3, v4, v3
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; CHECK-NOVSX-NEXT: lvx v4, 0, r3
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; CHECK-NOVSX-NEXT: vsro v2, v2, v4
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; CHECK-NOVSX-NEXT: vspltb v4, v4, 15
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; CHECK-NOVSX-NEXT: vsr v2, v2, v4
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; CHECK-NOVSX-NEXT: vor v2, v3, v2
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; CHECK-NOVSX-NEXT: blr
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entry:
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%shl = shl <1 x i128> %num, <i128 8>
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%shr = lshr <1 x i128> %num, <i128 120>
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%or = or <1 x i128> %shl, %shr
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ret <1 x i128> %or
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}
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define <1 x i128> @rotl_120(<1 x i128> %num) {
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; CHECK-VSX-LABEL: rotl_120:
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; CHECK-VSX: # %bb.0: # %entry
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; CHECK-VSX-NEXT: addis r3, r2, .LCPI6_0@toc@ha
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; CHECK-VSX-NEXT: addi r3, r3, .LCPI6_0@toc@l
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; CHECK-VSX-NEXT: lxvx v3, 0, r3
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; CHECK-VSX-NEXT: addis r3, r2, .LCPI6_1@toc@ha
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; CHECK-VSX-NEXT: addi r3, r3, .LCPI6_1@toc@l
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; CHECK-VSX-NEXT: vslo v4, v2, v3
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; CHECK-VSX-NEXT: vspltb v3, v3, 15
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; CHECK-VSX-NEXT: vsl v3, v4, v3
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; CHECK-VSX-NEXT: lxvx v4, 0, r3
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; CHECK-VSX-NEXT: vsro v2, v2, v4
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; CHECK-VSX-NEXT: vspltb v4, v4, 15
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; CHECK-VSX-NEXT: vsr v2, v2, v4
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; CHECK-VSX-NEXT: xxlor v2, v3, v2
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; CHECK-VSX-NEXT: blr
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;
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; CHECK-NOVSX-LABEL: rotl_120:
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; CHECK-NOVSX: # %bb.0: # %entry
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; CHECK-NOVSX-NEXT: addis r3, r2, .LCPI6_0@toc@ha
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; CHECK-NOVSX-NEXT: addi r3, r3, .LCPI6_0@toc@l
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; CHECK-NOVSX-NEXT: lvx v3, 0, r3
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; CHECK-NOVSX-NEXT: addis r3, r2, .LCPI6_1@toc@ha
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; CHECK-NOVSX-NEXT: addi r3, r3, .LCPI6_1@toc@l
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; CHECK-NOVSX-NEXT: vslo v4, v2, v3
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; CHECK-NOVSX-NEXT: vspltb v3, v3, 15
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; CHECK-NOVSX-NEXT: vsl v3, v4, v3
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; CHECK-NOVSX-NEXT: lvx v4, 0, r3
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; CHECK-NOVSX-NEXT: vsro v2, v2, v4
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; CHECK-NOVSX-NEXT: vspltb v4, v4, 15
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; CHECK-NOVSX-NEXT: vsr v2, v2, v4
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; CHECK-NOVSX-NEXT: vor v2, v3, v2
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; CHECK-NOVSX-NEXT: blr
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entry:
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%shl = shl <1 x i128> %num, <i128 120>
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%shr = lshr <1 x i128> %num, <i128 8>
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%or = or <1 x i128> %shl, %shr
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ret <1 x i128> %or
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}
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define <1 x i128> @rotl_28(<1 x i128> %num) {
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; CHECK-VSX-LABEL: rotl_28:
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; CHECK-VSX: # %bb.0: # %entry
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; CHECK-VSX-NEXT: addis r3, r2, .LCPI7_0@toc@ha
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; CHECK-VSX-NEXT: addi r3, r3, .LCPI7_0@toc@l
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; CHECK-VSX-NEXT: lxvx v3, 0, r3
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; CHECK-VSX-NEXT: addis r3, r2, .LCPI7_1@toc@ha
|
||||
; CHECK-VSX-NEXT: addi r3, r3, .LCPI7_1@toc@l
|
||||
; CHECK-VSX-NEXT: vslo v4, v2, v3
|
||||
; CHECK-VSX-NEXT: vspltb v3, v3, 15
|
||||
; CHECK-VSX-NEXT: vsl v3, v4, v3
|
||||
; CHECK-VSX-NEXT: lxvx v4, 0, r3
|
||||
; CHECK-VSX-NEXT: vsro v2, v2, v4
|
||||
; CHECK-VSX-NEXT: vspltb v4, v4, 15
|
||||
; CHECK-VSX-NEXT: vsr v2, v2, v4
|
||||
; CHECK-VSX-NEXT: xxlor v2, v3, v2
|
||||
; CHECK-VSX-NEXT: blr
|
||||
;
|
||||
; CHECK-NOVSX-LABEL: rotl_28:
|
||||
; CHECK-NOVSX: # %bb.0: # %entry
|
||||
; CHECK-NOVSX-NEXT: addis r3, r2, .LCPI7_0@toc@ha
|
||||
; CHECK-NOVSX-NEXT: addi r3, r3, .LCPI7_0@toc@l
|
||||
; CHECK-NOVSX-NEXT: lvx v3, 0, r3
|
||||
; CHECK-NOVSX-NEXT: addis r3, r2, .LCPI7_1@toc@ha
|
||||
; CHECK-NOVSX-NEXT: addi r3, r3, .LCPI7_1@toc@l
|
||||
; CHECK-NOVSX-NEXT: vslo v4, v2, v3
|
||||
; CHECK-NOVSX-NEXT: vspltb v3, v3, 15
|
||||
; CHECK-NOVSX-NEXT: vsl v3, v4, v3
|
||||
; CHECK-NOVSX-NEXT: lvx v4, 0, r3
|
||||
; CHECK-NOVSX-NEXT: vsro v2, v2, v4
|
||||
; CHECK-NOVSX-NEXT: vspltb v4, v4, 15
|
||||
; CHECK-NOVSX-NEXT: vsr v2, v2, v4
|
||||
; CHECK-NOVSX-NEXT: vor v2, v3, v2
|
||||
; CHECK-NOVSX-NEXT: blr
|
||||
entry:
|
||||
%shl = shl <1 x i128> %num, <i128 28>
|
||||
%shr = lshr <1 x i128> %num, <i128 100>
|
||||
%or = or <1 x i128> %shl, %shr
|
||||
ret <1 x i128> %or
|
||||
}
|
||||
|
||||
define <1 x i128> @NO_rotl(<1 x i128> %num) {
|
||||
; CHECK-VSX-LABEL: NO_rotl:
|
||||
; CHECK-VSX: # %bb.0: # %entry
|
||||
; CHECK-VSX-NEXT: addis r3, r2, .LCPI8_0@toc@ha
|
||||
; CHECK-VSX-NEXT: addi r3, r3, .LCPI8_0@toc@l
|
||||
; CHECK-VSX-NEXT: lxvx v3, 0, r3
|
||||
; CHECK-VSX-NEXT: addis r3, r2, .LCPI8_1@toc@ha
|
||||
; CHECK-VSX-NEXT: addi r3, r3, .LCPI8_1@toc@l
|
||||
; CHECK-VSX-NEXT: vslo v4, v2, v3
|
||||
; CHECK-VSX-NEXT: vspltb v3, v3, 15
|
||||
; CHECK-VSX-NEXT: vsl v3, v4, v3
|
||||
; CHECK-VSX-NEXT: lxvx v4, 0, r3
|
||||
; CHECK-VSX-NEXT: vsro v2, v2, v4
|
||||
; CHECK-VSX-NEXT: vspltb v4, v4, 15
|
||||
; CHECK-VSX-NEXT: vsr v2, v2, v4
|
||||
; CHECK-VSX-NEXT: xxlor v2, v3, v2
|
||||
; CHECK-VSX-NEXT: blr
|
||||
;
|
||||
; CHECK-NOVSX-LABEL: NO_rotl:
|
||||
; CHECK-NOVSX: # %bb.0: # %entry
|
||||
; CHECK-NOVSX-NEXT: addis r3, r2, .LCPI8_0@toc@ha
|
||||
; CHECK-NOVSX-NEXT: addi r3, r3, .LCPI8_0@toc@l
|
||||
; CHECK-NOVSX-NEXT: lvx v3, 0, r3
|
||||
; CHECK-NOVSX-NEXT: addis r3, r2, .LCPI8_1@toc@ha
|
||||
; CHECK-NOVSX-NEXT: addi r3, r3, .LCPI8_1@toc@l
|
||||
; CHECK-NOVSX-NEXT: vslo v4, v2, v3
|
||||
; CHECK-NOVSX-NEXT: vspltb v3, v3, 15
|
||||
; CHECK-NOVSX-NEXT: vsl v3, v4, v3
|
||||
; CHECK-NOVSX-NEXT: lvx v4, 0, r3
|
||||
; CHECK-NOVSX-NEXT: vsro v2, v2, v4
|
||||
; CHECK-NOVSX-NEXT: vspltb v4, v4, 15
|
||||
; CHECK-NOVSX-NEXT: vsr v2, v2, v4
|
||||
; CHECK-NOVSX-NEXT: vor v2, v3, v2
|
||||
; CHECK-NOVSX-NEXT: blr
|
||||
entry:
|
||||
%shl = shl <1 x i128> %num, <i128 20>
|
||||
%shr = lshr <1 x i128> %num, <i128 100>
|
||||
%or = or <1 x i128> %shl, %shr
|
||||
ret <1 x i128> %or
|
||||
}
|
||||
|
||||
define <1 x i128> @shufflevector(<1 x i128> %num) {
|
||||
; CHECK-VSX-LABEL: shufflevector:
|
||||
; CHECK-VSX: # %bb.0: # %entry
|
||||
; CHECK-VSX-NEXT: xxswapd v2, v2
|
||||
; CHECK-VSX-NEXT: blr
|
||||
;
|
||||
; CHECK-NOVSX-LABEL: shufflevector:
|
||||
; CHECK-NOVSX: # %bb.0: # %entry
|
||||
; CHECK-NOVSX-NEXT: vsldoi v2, v2, v2, 8
|
||||
; CHECK-NOVSX-NEXT: blr
|
||||
entry:
|
||||
%0 = bitcast <1 x i128> %num to <2 x i64>
|
||||
%vecins2 = shufflevector <2 x i64> %0, <2 x i64> undef, <2 x i32> <i32 1, i32 0>
|
||||
%1 = bitcast <2 x i64> %vecins2 to <1 x i128>
|
||||
ret <1 x i128> %1
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user