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[X86][SSE] Add test showing missed opportunity to combine to pshuflw

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We are combining shuffles to bit shifts before unary permutes, which means we can't fold loads plus the destination register is destructive

llvm-svn: 306976
This commit is contained in:
Simon Pilgrim 2017-07-02 12:56:10 +00:00
parent 1032df3c54
commit 66c4c00993
1 changed files with 18 additions and 0 deletions
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18
test/CodeGen/X86/vector-shuffle-combining-ssse3.ll
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@ -445,6 +445,24 @@ define <16 x i8> @combine_pshufb_not_as_pshufw(<16 x i8> %a0) {
ret <16 x i8> %res1
}
; TODO - we could fold the load if we lowered to pshuflw instead.
define <16 x i8> @combine_vpshufb_as_pshuflw_not_pslld(<16 x i8> *%a0) {
; SSE-LABEL: combine_vpshufb_as_pshuflw_not_pslld:
; SSE: # BB#0:
; SSE-NEXT: movdqa (%rdi), %xmm0
; SSE-NEXT: pslld $16, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vpshufb_as_pshuflw_not_pslld:
; AVX: # BB#0:
; AVX-NEXT: vmovdqa (%rdi), %xmm0
; AVX-NEXT: vpslld $16, %xmm0, %xmm0
; AVX-NEXT: retq
%res0 = load <16 x i8>, <16 x i8> *%a0, align 16
%res1 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %res0, <16 x i8> <i8 undef, i8 undef, i8 0, i8 1, i8 undef, i8 undef, i8 4, i8 5, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>)
ret <16 x i8> %res1
}
define <16 x i8> @combine_pshufb_as_unary_unpcklbw(<16 x i8> %a0) {
; SSE-LABEL: combine_pshufb_as_unary_unpcklbw:
; SSE: # BB#0: