RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 03:33:20 +01:00
Code Issues Projects Releases Wiki Activity

ARM instruction don't have instruction prefixes, so remove the helper functions

Browse Source 
for them from the MCCodeEmitter.

llvm-svn: 115975
This commit is contained in:
Jim Grosbach 2010-10-07 20:41:30 +00:00
parent ea4028ac17
commit 671713cc62
1 changed files with 1 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
lib/Target/ARM/ARMMCCodeEmitter.cpp
View File

@ -13,7 +13,7 @@
#define DEBUG_TYPE "arm-emitter"
#include "ARM.h"
#include "ARMInstrInfo.h"
#include "ARMBaseInfo.h"
#include "llvm/MC/MCCodeEmitter.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
@ -75,10 +75,6 @@ public:
void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups) const;
void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
const MCInst &MI, const TargetInstrDesc &Desc,
raw_ostream &OS) const;
};
} // end anonymous namespace
@ -97,17 +93,6 @@ EmitImmediate(const MCOperand &DispOp, unsigned Size, MCFixupKind FixupKind,
assert(0 && "ARMMCCodeEmitter::EmitImmediate() not yet implemented.");
}
/// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode.
///
/// MemOperand is the operand # of the start of a memory operand if present. If
/// Not present, it is -1.
void ARMMCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
int MemOperand, const MCInst &MI,
const TargetInstrDesc &Desc,
raw_ostream &OS) const {
assert(0 && "ARMMCCodeEmitter::EmitOpcodePrefix() not yet implemented.");
}
void ARMMCCodeEmitter::
EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups) const {