mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2025-01-31 20:51:52 +01:00
[LegalizerTypes] Add support for scalarizing the operand of an FP_EXTEND when the result type is legal.
This commit is contained in:
parent
6165ecd19b
commit
671af695d9
@ -776,6 +776,8 @@ private:
|
||||
SDValue ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo);
|
||||
SDValue ScalarizeVecOp_FP_ROUND(SDNode *N, unsigned OpNo);
|
||||
SDValue ScalarizeVecOp_STRICT_FP_ROUND(SDNode *N, unsigned OpNo);
|
||||
SDValue ScalarizeVecOp_FP_EXTEND(SDNode *N);
|
||||
SDValue ScalarizeVecOp_STRICT_FP_EXTEND(SDNode *N);
|
||||
SDValue ScalarizeVecOp_VECREDUCE(SDNode *N);
|
||||
SDValue ScalarizeVecOp_VECREDUCE_SEQ(SDNode *N);
|
||||
|
||||
|
@ -607,6 +607,12 @@ bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
|
||||
case ISD::FP_ROUND:
|
||||
Res = ScalarizeVecOp_FP_ROUND(N, OpNo);
|
||||
break;
|
||||
case ISD::STRICT_FP_EXTEND:
|
||||
Res = ScalarizeVecOp_STRICT_FP_EXTEND(N);
|
||||
break;
|
||||
case ISD::FP_EXTEND:
|
||||
Res = ScalarizeVecOp_FP_EXTEND(N);
|
||||
break;
|
||||
case ISD::VECREDUCE_FADD:
|
||||
case ISD::VECREDUCE_FMUL:
|
||||
case ISD::VECREDUCE_ADD:
|
||||
@ -770,6 +776,7 @@ SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
|
||||
/// If the value to round is a vector that needs to be scalarized, it must be
|
||||
/// <1 x ty>. Convert the element instead.
|
||||
SDValue DAGTypeLegalizer::ScalarizeVecOp_FP_ROUND(SDNode *N, unsigned OpNo) {
|
||||
assert(OpNo == 0 && "Wrong operand for scalarization!");
|
||||
SDValue Elt = GetScalarizedVector(N->getOperand(0));
|
||||
SDValue Res = DAG.getNode(ISD::FP_ROUND, SDLoc(N),
|
||||
N->getValueType(0).getVectorElementType(), Elt,
|
||||
@ -795,7 +802,36 @@ SDValue DAGTypeLegalizer::ScalarizeVecOp_STRICT_FP_ROUND(SDNode *N,
|
||||
// handled all replacements since caller can only handle a single result.
|
||||
ReplaceValueWith(SDValue(N, 0), Res);
|
||||
return SDValue();
|
||||
}
|
||||
}
|
||||
|
||||
/// If the value to extend is a vector that needs to be scalarized, it must be
|
||||
/// <1 x ty>. Convert the element instead.
|
||||
SDValue DAGTypeLegalizer::ScalarizeVecOp_FP_EXTEND(SDNode *N) {
|
||||
SDValue Elt = GetScalarizedVector(N->getOperand(0));
|
||||
SDValue Res = DAG.getNode(ISD::FP_EXTEND, SDLoc(N),
|
||||
N->getValueType(0).getVectorElementType(), Elt);
|
||||
return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res);
|
||||
}
|
||||
|
||||
/// If the value to extend is a vector that needs to be scalarized, it must be
|
||||
/// <1 x ty>. Convert the element instead.
|
||||
SDValue DAGTypeLegalizer::ScalarizeVecOp_STRICT_FP_EXTEND(SDNode *N) {
|
||||
SDValue Elt = GetScalarizedVector(N->getOperand(1));
|
||||
SDValue Res =
|
||||
DAG.getNode(ISD::STRICT_FP_EXTEND, SDLoc(N),
|
||||
{N->getValueType(0).getVectorElementType(), MVT::Other},
|
||||
{N->getOperand(0), Elt});
|
||||
// Legalize the chain result - switch anything that used the old chain to
|
||||
// use the new one.
|
||||
ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
|
||||
|
||||
Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res);
|
||||
|
||||
// Do our own replacement and return SDValue() to tell the caller that we
|
||||
// handled all replacements since caller can only handle a single result.
|
||||
ReplaceValueWith(SDValue(N, 0), Res);
|
||||
return SDValue();
|
||||
}
|
||||
|
||||
SDValue DAGTypeLegalizer::ScalarizeVecOp_VECREDUCE(SDNode *N) {
|
||||
SDValue Res = GetScalarizedVector(N->getOperand(0));
|
||||
|
26
test/CodeGen/AArch64/neon-fpextend_f16.ll
Normal file
26
test/CodeGen/AArch64/neon-fpextend_f16.ll
Normal file
@ -0,0 +1,26 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s
|
||||
|
||||
; This is testing that we can scalarize the v1f16 input to fp_extend even
|
||||
; though the v1f64 result is legal.
|
||||
|
||||
define <1 x double> @fpext_v1f16_v1f64(<1 x half>* %a) {
|
||||
; CHECK-LABEL: fpext_v1f16_v1f64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ldr h0, [x0]
|
||||
; CHECK-NEXT: fcvt d0, h0
|
||||
; CHECK-NEXT: ret
|
||||
%b = load <1 x half>, <1 x half>* %a
|
||||
%c = fpext <1 x half> %b to <1 x double>
|
||||
ret <1 x double> %c
|
||||
}
|
||||
|
||||
define <1 x double> @strict_fpext_v1f32_v1f64(<1 x half> %x) #0 {
|
||||
; CHECK-LABEL: strict_fpext_v1f32_v1f64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: fcvt d0, h0
|
||||
; CHECK-NEXT: ret
|
||||
%val = call <1 x double> @llvm.experimental.constrained.fpext.v1f64.v1f16(<1 x half> %x, metadata !"fpexcept.strict") strictfp
|
||||
ret <1 x double> %val
|
||||
}
|
||||
declare <1 x double> @llvm.experimental.constrained.fpext.v1f64.v1f16(<1 x half>, metadata)
|
Loading…
x
Reference in New Issue
Block a user