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[PowerPC][Power10] Add Instruction definition/MC Tests for Load/Store Rightmost VSX Vector

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This patch adds the instruction definitions and the assembly/disassembly
tests for the Load/Store VSX Vector Rightmose instructions.

Differential Revision: https://reviews.llvm.org/D83364
This commit is contained in:
Albion Fung 2020-07-09 17:03:41 -05:00 committed by Amy Kwan
parent e330e469db
commit 6720e74af7
3 changed files with 66 additions and 0 deletions
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18
lib/Target/PowerPC/PPCInstrPrefix.td
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@ -942,8 +942,26 @@ let Predicates = [IsISA3_1] in {
"vclrrb $vD, $vA, $rB", IIC_VecGeneral,
[(set v16i8:$vD,
(int_ppc_altivec_vclrrb v16i8:$vA, i32:$rB))]>;
// The XFormMemOp flag for the following 8 instructions is set on
// the instruction format.
let mayLoad = 1, mayStore = 0 in {
def LXVRBX : X_XT6_RA5_RB5<31, 13, "lxvrbx", vsrc, []>;
def LXVRHX : X_XT6_RA5_RB5<31, 45, "lxvrhx", vsrc, []>;
def LXVRWX : X_XT6_RA5_RB5<31, 77, "lxvrwx", vsrc, []>;
def LXVRDX : X_XT6_RA5_RB5<31, 109, "lxvrdx", vsrc, []>;
}
let mayLoad = 0, mayStore = 1 in {
def STXVRBX : X_XS6_RA5_RB5<31, 141, "stxvrbx", vsrc, []>;
def STXVRHX : X_XS6_RA5_RB5<31, 173, "stxvrhx", vsrc, []>;
def STXVRWX : X_XS6_RA5_RB5<31, 205, "stxvrwx", vsrc, []>;
def STXVRDX : X_XS6_RA5_RB5<31, 237, "stxvrdx", vsrc, []>;
}
}
//---------------------------- Anonymous Patterns ----------------------------//
let Predicates = [IsISA3_1] in {
def : Pat<(v16i8 (int_ppc_vsx_xxgenpcvbm v16i8:$VRB, imm:$IMM)),

24
test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
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@ -278,3 +278,27 @@
# CHECK: vinsdrx 1, 2, 3
0x10 0x22 0x1b 0xcf
# CHECK: lxvrbx 32, 1, 2
0x7c 0x01 0x10 0x1b
# CHECK: lxvrhx 33, 1, 2
0x7c 0x21 0x10 0x5b
# CHECK: lxvrdx 34, 1, 2
0x7c 0x41 0x10 0xdb
# CHECK: lxvrwx 35, 1, 2
0x7c 0x61 0x10 0x9b
# CHECK: stxvrbx 32, 3, 1
0x7c 0x03 0x09 0x1b
# CHECK: stxvrhx 33, 3, 1
0x7c 0x23 0x09 0x5b
# CHECK: stxvrwx 34, 3, 1
0x7c 0x43 0x09 0x9b
# CHECK: stxvrdx 35, 3, 1
0x7c 0x63 0x09 0xdb

24
test/MC/PowerPC/ppc64-encoding-ISA31.s
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@ -405,3 +405,27 @@
# CHECK-BE: vinsdrx 1, 2, 3 # encoding: [0x10,0x22,0x1b,0xcf]
# CHECK-LE: vinsdrx 1, 2, 3 # encoding: [0xcf,0x1b,0x22,0x10]
vinsdrx 1, 2, 3
# CHECK-BE: lxvrbx 32, 1, 2 # encoding: [0x7c,0x01,0x10,0x1b]
# CHECK-LE: lxvrbx 32, 1, 2 # encoding: [0x1b,0x10,0x01,0x7c]
lxvrbx 32, 1, 2
# CHECK-BE: lxvrhx 33, 1, 2 # encoding: [0x7c,0x21,0x10,0x5b]
# CHECK-LE: lxvrhx 33, 1, 2 # encoding: [0x5b,0x10,0x21,0x7c]
lxvrhx 33, 1, 2
# CHECK-BE: lxvrdx 34, 1, 2 # encoding: [0x7c,0x41,0x10,0xdb]
# CHECK-LE: lxvrdx 34, 1, 2 # encoding: [0xdb,0x10,0x41,0x7c]
lxvrdx 34, 1, 2
# CHECK-BE: lxvrwx 35, 1, 2 # encoding: [0x7c,0x61,0x10,0x9b]
# CHECK-LE: lxvrwx 35, 1, 2 # encoding: [0x9b,0x10,0x61,0x7c]
lxvrwx 35, 1, 2
# CHECK-BE: stxvrbx 32, 3, 1 # encoding: [0x7c,0x03,0x09,0x1b]
# CHECK-LE: stxvrbx 32, 3, 1 # encoding: [0x1b,0x09,0x03,0x7c]
stxvrbx 32, 3, 1
# CHECK-BE: stxvrhx 33, 3, 1 # encoding: [0x7c,0x23,0x09,0x5b]
# CHECK-LE: stxvrhx 33, 3, 1 # encoding: [0x5b,0x09,0x23,0x7c]
stxvrhx 33, 3, 1
# CHECK-BE: stxvrwx 34, 3, 1 # encoding: [0x7c,0x43,0x09,0x9b]
# CHECK-LE: stxvrwx 34, 3, 1 # encoding: [0x9b,0x09,0x43,0x7c]
stxvrwx 34, 3, 1
# CHECK-BE: stxvrdx 35, 3, 1 # encoding: [0x7c,0x63,0x09,0xdb]
# CHECK-LE: stxvrdx 35, 3, 1 # encoding: [0xdb,0x09,0x63,0x7c]
stxvrdx 35, 3, 1