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Fix bad indentation, 80-column violations, and trailing whitespace.
llvm-svn: 99295
This commit is contained in:
Bob Wilson
parent
00ac54b896
commit
672147e9a2
@ -1,10 +1,10 @@
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//===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=//
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//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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@ -178,13 +178,13 @@ class InstTemplate<AddrMode am, SizeFlagVal sz, IndexMode im,
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// TSFlagsFields
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AddrMode AM = am;
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bits<4> AddrModeBits = AM.Value;
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SizeFlagVal SZ = sz;
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bits<3> SizeFlag = SZ.Value;
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IndexMode IM = im;
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bits<2> IndexModeBits = IM.Value;
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Format F = f;
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bits<6> Form = F.Value;
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@ -196,7 +196,7 @@ class InstTemplate<AddrMode am, SizeFlagVal sz, IndexMode im,
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//
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bit isUnaryDataProc = 0;
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bit canXformTo16Bit = 0;
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let Constraints = cstr;
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let Itinerary = itin;
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}
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@ -215,9 +215,9 @@ class InstThumb<AddrMode am, SizeFlagVal sz, IndexMode im,
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Format f, Domain d, string cstr, InstrItinClass itin>
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: InstTemplate<am, sz, im, f, d, cstr, itin>;
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class PseudoInst<dag oops, dag iops, InstrItinClass itin,
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class PseudoInst<dag oops, dag iops, InstrItinClass itin,
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string asm, list<dag> pattern>
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: InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, GenericDomain,
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: InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, GenericDomain,
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"", itin> {
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let OutOperandList = oops;
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let InOperandList = iops;
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@ -227,7 +227,7 @@ class PseudoInst<dag oops, dag iops, InstrItinClass itin,
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// Almost all ARM instructions are predicable.
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class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
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IndexMode im, Format f, InstrItinClass itin,
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IndexMode im, Format f, InstrItinClass itin,
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string opc, string asm, string cstr,
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list<dag> pattern>
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: InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
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@ -239,9 +239,9 @@ class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
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}
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// A few are not predicable
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class InoP<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
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IndexMode im, Format f, InstrItinClass itin,
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string opc, string asm, string cstr,
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list<dag> pattern>
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IndexMode im, Format f, InstrItinClass itin,
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string opc, string asm, string cstr,
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list<dag> pattern>
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: InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
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let OutOperandList = oops;
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let InOperandList = iops;
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@ -291,9 +291,9 @@ class AXI<dag oops, dag iops, Format f, InstrItinClass itin,
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: XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
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asm, "", pattern>;
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class AInoP<dag oops, dag iops, Format f, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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string opc, string asm, list<dag> pattern>
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: InoP<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
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opc, asm, "", pattern>;
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opc, asm, "", pattern>;
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// Ctrl flow instructions
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class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
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@ -363,7 +363,7 @@ class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
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let Inst{24-21} = opcod;
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let Inst{27-26} = {0,0};
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}
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class AI1x2<dag oops, dag iops, Format f, InstrItinClass itin,
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class AI1x2<dag oops, dag iops, Format f, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: I<oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, itin,
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opc, asm, "", pattern>;
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@ -388,7 +388,7 @@ class AI2ldw<dag oops, dag iops, Format f, InstrItinClass itin,
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let Inst{24} = 1; // P bit
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let Inst{27-26} = {0,1};
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}
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class AXI2ldw<dag oops, dag iops, Format f, InstrItinClass itin,
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class AXI2ldw<dag oops, dag iops, Format f, InstrItinClass itin,
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string asm, list<dag> pattern>
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: XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
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asm, "", pattern> {
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@ -408,7 +408,7 @@ class AI2ldb<dag oops, dag iops, Format f, InstrItinClass itin,
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let Inst{24} = 1; // P bit
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let Inst{27-26} = {0,1};
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}
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class AXI2ldb<dag oops, dag iops, Format f, InstrItinClass itin,
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class AXI2ldb<dag oops, dag iops, Format f, InstrItinClass itin,
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string asm, list<dag> pattern>
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: XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, itin,
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asm, "", pattern> {
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@ -550,7 +550,7 @@ class AI2stbpo<dag oops, dag iops, Format f, InstrItinClass itin,
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}
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// addrmode3 instructions
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class AI3<dag oops, dag iops, Format f, InstrItinClass itin,
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class AI3<dag oops, dag iops, Format f, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
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opc, asm, "", pattern>;
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@ -854,7 +854,6 @@ class AI3stdpo<dag oops, dag iops, Format f, InstrItinClass itin,
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let Inst{27-25} = 0b000;
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}
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// addrmode4 instructions
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class AXI4ld<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
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string asm, string cstr, list<dag> pattern>
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@ -962,20 +961,25 @@ class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
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: ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>;
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// Two-address instructions
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class TIt<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
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: ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "$lhs = $dst", pattern>;
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class TIt<dag oops, dag iops, InstrItinClass itin, string asm,
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list<dag> pattern>
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: ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "$lhs = $dst",
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pattern>;
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// tBL, tBX 32-bit instructions
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class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3,
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dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
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: ThumbI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>, Encoding {
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dag oops, dag iops, InstrItinClass itin, string asm,
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list<dag> pattern>
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: ThumbI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>,
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Encoding {
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let Inst{31-27} = opcod1;
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let Inst{15-14} = opcod2;
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let Inst{12} = opcod3;
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}
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// BR_JT instructions
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class TJTI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
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class TJTI<dag oops, dag iops, InstrItinClass itin, string asm,
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list<dag> pattern>
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: ThumbI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
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// Thumb1 only
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@ -1002,7 +1006,7 @@ class T1JTI<dag oops, dag iops, InstrItinClass itin,
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// Two-address instructions
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class T1It<dag oops, dag iops, InstrItinClass itin,
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string asm, string cstr, list<dag> pattern>
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: Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin,
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: Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin,
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asm, cstr, pattern>;
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// Thumb1 instruction that can either be predicated or set CPSR.
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@ -1025,7 +1029,7 @@ class T1sI<dag oops, dag iops, InstrItinClass itin,
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class T1sIt<dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
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"$lhs = $dst", pattern>;
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"$lhs = $dst", pattern>;
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// Thumb1 instruction that can be predicated.
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class Thumb1pI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
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@ -1047,7 +1051,7 @@ class T1pI<dag oops, dag iops, InstrItinClass itin,
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class T1pIt<dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
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"$lhs = $dst", pattern>;
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"$lhs = $dst", pattern>;
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class T1pI1<dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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@ -1058,7 +1062,7 @@ class T1pI2<dag oops, dag iops, InstrItinClass itin,
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class T1pI4<dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: Thumb1pI<oops, iops, AddrModeT1_4, Size2Bytes, itin, opc, asm, "", pattern>;
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class T1pIs<dag oops, dag iops,
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class T1pIs<dag oops, dag iops,
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InstrItinClass itin, string opc, string asm, list<dag> pattern>
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: Thumb1pI<oops, iops, AddrModeT1_s, Size2Bytes, itin, opc, asm, "", pattern>;
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@ -1147,8 +1151,8 @@ class Thumb2XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
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}
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class ThumbXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
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InstrItinClass itin,
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string asm, string cstr, list<dag> pattern>
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InstrItinClass itin,
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string asm, string cstr, list<dag> pattern>
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: InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
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let OutOperandList = oops;
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let InOperandList = iops;
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@ -1162,7 +1166,7 @@ class T2I<dag oops, dag iops, InstrItinClass itin,
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: Thumb2I<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>;
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class T2Ii12<dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: Thumb2I<oops, iops, AddrModeT2_i12, Size4Bytes, itin, opc, asm, "", pattern>;
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: Thumb2I<oops, iops, AddrModeT2_i12, Size4Bytes, itin, opc, asm, "",pattern>;
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class T2Ii8<dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: Thumb2I<oops, iops, AddrModeT2_i8, Size4Bytes, itin, opc, asm, "", pattern>;
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@ -1197,7 +1201,7 @@ class T2JTI<dag oops, dag iops, InstrItinClass itin,
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: Thumb2XI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
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class T2Ix2<dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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string opc, string asm, list<dag> pattern>
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: Thumb2I<oops, iops, AddrModeNone, Size8Bytes, itin, opc, asm, "", pattern>;
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// Two-address instructions
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@ -1296,7 +1300,7 @@ class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
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InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
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VFPLdStFrm, itin, opc, asm, "", pattern> {
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VFPLdStFrm, itin, opc, asm, "", pattern> {
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// TODO: Mark the instructions with the appropriate subtarget info.
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let Inst{27-24} = opcod1;
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let Inst{21-20} = opcod2;
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@ -1310,7 +1314,7 @@ class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
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InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
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VFPLdStFrm, itin, opc, asm, "", pattern> {
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VFPLdStFrm, itin, opc, asm, "", pattern> {
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// TODO: Mark the instructions with the appropriate subtarget info.
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let Inst{27-24} = opcod1;
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let Inst{21-20} = opcod2;
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@ -1321,7 +1325,7 @@ class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
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class AXDI5<dag oops, dag iops, IndexMode im, InstrItinClass itin,
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string asm, string cstr, list<dag> pattern>
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: VFPXI<oops, iops, AddrMode5, Size4Bytes, im,
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VFPLdStMulFrm, itin, asm, cstr, pattern> {
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VFPLdStMulFrm, itin, asm, cstr, pattern> {
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// TODO: Mark the instructions with the appropriate subtarget info.
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let Inst{27-25} = 0b110;
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let Inst{11-8} = 0b1011;
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@ -1333,7 +1337,7 @@ class AXDI5<dag oops, dag iops, IndexMode im, InstrItinClass itin,
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class AXSI5<dag oops, dag iops, IndexMode im, InstrItinClass itin,
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string asm, string cstr, list<dag> pattern>
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: VFPXI<oops, iops, AddrMode5, Size4Bytes, im,
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VFPLdStMulFrm, itin, asm, cstr, pattern> {
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VFPLdStMulFrm, itin, asm, cstr, pattern> {
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// TODO: Mark the instructions with the appropriate subtarget info.
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let Inst{27-25} = 0b110;
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let Inst{11-8} = 0b1010;
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@ -1354,7 +1358,8 @@ class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
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// Double precision, binary
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class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
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dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
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dag iops, InstrItinClass itin, string opc, string asm,
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list<dag> pattern>
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: VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
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let Inst{27-23} = opcod1;
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let Inst{21-20} = opcod2;
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@ -1400,7 +1405,8 @@ class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,
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// Single precision binary, if no NEON
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// Same as ASbI except not available if NEON is enabled
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class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
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dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern>
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dag iops, InstrItinClass itin, string opc, string asm,
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list<dag> pattern>
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: ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
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list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
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}
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@ -1420,8 +1426,8 @@ class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
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// VFP conversion between floating-point and fixed-point
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class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5,
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dag oops, dag iops, InstrItinClass itin, string opc, string asm,
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list<dag> pattern>
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dag oops, dag iops, InstrItinClass itin, string opc, string asm,
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list<dag> pattern>
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: AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> {
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// size (fixed-point number): sx == 0 ? 16 : 32
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let Inst{7} = op5; // sx
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@ -1449,7 +1455,7 @@ class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
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InstrItinClass itin, string opc, string asm, list<dag> pattern>
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: AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>;
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class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
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class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
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InstrItinClass itin, string opc, string asm, list<dag> pattern>
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: AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>;
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@ -1482,7 +1488,7 @@ class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
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// Same as NeonI except it does not have a "data type" specifier.
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class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, InstrItinClass itin,
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string opc, string asm, string cstr, list<dag> pattern>
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string opc, string asm, string cstr, list<dag> pattern>
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: InstARM<am, Size4Bytes, im, NEONFrm, NeonDomain, cstr, itin> {
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let OutOperandList = oops;
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let InOperandList = !con(iops, (ins pred:$p));
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@ -1494,7 +1500,7 @@ class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, InstrItinClass itin,
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class NI<dag oops, dag iops, InstrItinClass itin, string opc, string asm,
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list<dag> pattern>
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: NeonXI<oops, iops, AddrModeNone, IndexModeNone, itin, opc, asm, "",
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pattern> {
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pattern> {
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}
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class NI4<dag oops, dag iops, InstrItinClass itin, string opc,
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@ -1523,9 +1529,9 @@ class NDataI<dag oops, dag iops, Format f, InstrItinClass itin,
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}
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class NDataXI<dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, string cstr, list<dag> pattern>
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string opc, string asm, string cstr, list<dag> pattern>
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: NeonXI<oops, iops, AddrModeNone, IndexModeNone, itin, opc, asm,
|
||||
cstr, pattern> {
|
||||
cstr, pattern> {
|
||||
let Inst{31-25} = 0b1111001;
|
||||
}
|
||||
|
||||
@ -1533,7 +1539,8 @@ class NDataXI<dag oops, dag iops, InstrItinClass itin,
|
||||
class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6,
|
||||
bit op5, bit op4,
|
||||
dag oops, dag iops, InstrItinClass itin,
|
||||
string opc, string dt, string asm, string cstr, list<dag> pattern>
|
||||
string opc, string dt, string asm, string cstr,
|
||||
list<dag> pattern>
|
||||
: NDataI<oops, iops, NVdImmFrm, itin, opc, dt, asm, cstr, pattern> {
|
||||
let Inst{23} = op23;
|
||||
let Inst{21-19} = op21_19;
|
||||
@ -1561,9 +1568,9 @@ class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
|
||||
|
||||
// Same as N2V except it doesn't have a datatype suffix.
|
||||
class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
|
||||
bits<5> op11_7, bit op6, bit op4,
|
||||
dag oops, dag iops, InstrItinClass itin,
|
||||
string opc, string asm, string cstr, list<dag> pattern>
|
||||
bits<5> op11_7, bit op6, bit op4,
|
||||
dag oops, dag iops, InstrItinClass itin,
|
||||
string opc, string asm, string cstr, list<dag> pattern>
|
||||
: NDataXI<oops, iops, itin, opc, asm, cstr, pattern> {
|
||||
let Inst{24-23} = op24_23;
|
||||
let Inst{21-20} = op21_20;
|
||||
@ -1601,9 +1608,10 @@ class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
|
||||
}
|
||||
|
||||
// Same as N3VX except it doesn't have a data type suffix.
|
||||
class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
|
||||
dag oops, dag iops, InstrItinClass itin,
|
||||
string opc, string asm, string cstr, list<dag> pattern>
|
||||
class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
|
||||
bit op4,
|
||||
dag oops, dag iops, InstrItinClass itin,
|
||||
string opc, string asm, string cstr, list<dag> pattern>
|
||||
: NDataXI<oops, iops, itin, opc, asm, cstr, pattern> {
|
||||
let Inst{24} = op24;
|
||||
let Inst{23} = op23;
|
||||
@ -1618,7 +1626,7 @@ class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
|
||||
dag oops, dag iops, Format f, InstrItinClass itin,
|
||||
string opc, string dt, string asm, list<dag> pattern>
|
||||
: InstARM<AddrModeNone, Size4Bytes, IndexModeNone, f, GenericDomain,
|
||||
"", itin> {
|
||||
"", itin> {
|
||||
let Inst{27-20} = opcod1;
|
||||
let Inst{11-8} = opcod2;
|
||||
let Inst{6-5} = opcod3;
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user