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https://github.com/RPCS3/llvm-mirror.git
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DAG: Fold fneg into compare with constant into the constant
fcmp (fneg x), c, pred -> fcmp x, -c, (swap pred) InstCombine already does this. llvm-svn: 293512
This commit is contained in:
Matt Arsenault
parent
d087048e1f
commit
6748c8f28b
@ -2050,6 +2050,16 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
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if (Cond == ISD::SETO || Cond == ISD::SETUO)
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return DAG.getSetCC(dl, VT, N0, N0, Cond);
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// setcc (fneg x), C -> setcc swap(pred) x, -C
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if (N0.getOpcode() == ISD::FNEG) {
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ISD::CondCode SwapCond = ISD::getSetCCSwappedOperands(Cond);
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if (DCI.isBeforeLegalizeOps() ||
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isCondCodeLegal(SwapCond, N0.getSimpleValueType())) {
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SDValue NegN1 = DAG.getNode(ISD::FNEG, dl, N0.getValueType(), N1);
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return DAG.getSetCC(dl, VT, N0.getOperand(0), NegN1, SwapCond);
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}
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}
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// If the condition is not legal, see if we can find an equivalent one
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// which is legal.
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if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) {
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257
test/CodeGen/AMDGPU/setcc-fneg-constant.ll
Normal file
257
test/CodeGen/AMDGPU/setcc-fneg-constant.ll
Normal file
@ -0,0 +1,257 @@
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
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; Test fcmp pred (fneg x), c -> fcmp (swapped pred) x, -c combine.
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; GCN-LABEL: {{^}}multi_use_fneg_src:
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; GCN: buffer_load_dword [[A:v[0-9]+]]
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; GCN: buffer_load_dword [[B:v[0-9]+]]
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; GCN: buffer_load_dword [[C:v[0-9]+]]
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; GCN: v_mul_f32_e32 [[MUL:v[0-9]+]], [[B]], [[A]]
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; GCN: v_cmp_eq_f32_e32 vcc, -4.0, [[MUL]]
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; GCN: buffer_store_dword [[MUL]]
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define void @multi_use_fneg_src() #0 {
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%a = load volatile float, float addrspace(1)* undef
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%b = load volatile float, float addrspace(1)* undef
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%x = load volatile i32, i32 addrspace(1)* undef
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%y = load volatile i32, i32 addrspace(1)* undef
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%mul = fmul float %a, %b
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%neg.mul = fsub float -0.0, %mul
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%cmp = fcmp oeq float %neg.mul, 4.0
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%select = select i1 %cmp, i32 %x, i32 %y
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store volatile i32 %select, i32 addrspace(1)* undef
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store volatile float %mul, float addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}multi_foldable_use_fneg_src:
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; GCN: buffer_load_dword [[A:v[0-9]+]]
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; GCN: buffer_load_dword [[B:v[0-9]+]]
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; GCN: buffer_load_dword [[C:v[0-9]+]]
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; GCN: v_mul_f32_e32 [[MUL:v[0-9]+]], [[B]], [[A]]
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; GCN: v_cmp_eq_f32_e32 vcc, -4.0, [[A]]
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; GCN: v_mul_f32_e64 [[USE1:v[0-9]+]], [[MUL]], -[[MUL]]
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define void @multi_foldable_use_fneg_src() #0 {
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%a = load volatile float, float addrspace(1)* undef
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%b = load volatile float, float addrspace(1)* undef
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%x = load volatile i32, i32 addrspace(1)* undef
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%y = load volatile i32, i32 addrspace(1)* undef
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%mul = fmul float %a, %b
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%neg.mul = fsub float -0.0, %mul
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%use1 = fmul float %mul, %neg.mul
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%cmp = fcmp oeq float %neg.mul, 4.0
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%select = select i1 %cmp, i32 %x, i32 %y
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store volatile i32 %select, i32 addrspace(1)* undef
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store volatile float %use1, float addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}multi_use_fneg:
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; GCN: buffer_load_dword [[A:v[0-9]+]]
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; GCN: buffer_load_dword [[B:v[0-9]+]]
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; GCN: buffer_load_dword [[C:v[0-9]+]]
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; GCN: v_mul_f32_e32 [[MUL:v[0-9]+]], [[B]], [[A]]
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; GCN: v_cmp_eq_f32_e32 vcc, -4.0, [[MUL]]
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; GCN: buffer_store_dword [[MUL]]
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define void @multi_use_fneg() #0 {
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%a = load volatile float, float addrspace(1)* undef
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%b = load volatile float, float addrspace(1)* undef
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%x = load volatile i32, i32 addrspace(1)* undef
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%y = load volatile i32, i32 addrspace(1)* undef
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%mul = fmul float %a, %b
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%neg.mul = fsub float -0.0, %mul
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%cmp = fcmp oeq float %neg.mul, 4.0
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%select = select i1 %cmp, i32 %x, i32 %y
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store volatile i32 %select, i32 addrspace(1)* undef
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store volatile float %neg.mul, float addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}multi_foldable_use_fneg:
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; GCN: buffer_load_dword [[A:v[0-9]+]]
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; GCN: buffer_load_dword [[B:v[0-9]+]]
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; GCN: v_mul_f32_e32 [[MUL0:v[0-9]+]], [[B]], [[A]]
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; GCN: v_cmp_eq_f32_e32 vcc, -4.0, [[MUL0]]
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; GCN: v_mul_f32_e64 [[MUL1:v[0-9]+]], -[[MUL0]], [[MUL0]]
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; GCN: buffer_store_dword [[MUL1]]
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define void @multi_foldable_use_fneg() #0 {
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%a = load volatile float, float addrspace(1)* undef
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%b = load volatile float, float addrspace(1)* undef
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%x = load volatile i32, i32 addrspace(1)* undef
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%y = load volatile i32, i32 addrspace(1)* undef
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%z = load volatile i32, i32 addrspace(1)* undef
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%mul = fmul float %a, %b
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%neg.mul = fsub float -0.0, %mul
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%cmp = fcmp oeq float %neg.mul, 4.0
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%select = select i1 %cmp, i32 %x, i32 %y
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%use1 = fmul float %neg.mul, %mul
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store volatile i32 %select, i32 addrspace(1)* undef
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store volatile float %use1, float addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}test_setcc_fneg_oeq_posk_f32:
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; GCN: v_cmp_eq_f32_e32 vcc, -4.0, v{{[0-9]+}}
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define void @test_setcc_fneg_oeq_posk_f32() #0 {
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%a = load volatile float, float addrspace(1)* undef
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%x = load volatile i32, i32 addrspace(1)* undef
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%y = load volatile i32, i32 addrspace(1)* undef
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%neg.a = fsub float -0.0, %a
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%cmp = fcmp oeq float %neg.a, 4.0
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%select = select i1 %cmp, i32 %x, i32 %y
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store volatile i32 %select, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}test_setcc_fneg_ogt_posk_f32:
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; GCN: v_cmp_gt_f32_e32 vcc, -4.0, v{{[0-9]+}}
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define void @test_setcc_fneg_ogt_posk_f32() #0 {
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%a = load volatile float, float addrspace(1)* undef
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%x = load volatile i32, i32 addrspace(1)* undef
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%y = load volatile i32, i32 addrspace(1)* undef
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%neg.a = fsub float -0.0, %a
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%cmp = fcmp ogt float %neg.a, 4.0
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%select = select i1 %cmp, i32 %x, i32 %y
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store volatile i32 %select, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}test_setcc_fneg_oge_posk_f32:
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; GCN: v_cmp_ge_f32_e32 vcc, -4.0, v{{[0-9]+}}
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define void @test_setcc_fneg_oge_posk_f32() #0 {
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%a = load volatile float, float addrspace(1)* undef
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%x = load volatile i32, i32 addrspace(1)* undef
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%y = load volatile i32, i32 addrspace(1)* undef
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%neg.a = fsub float -0.0, %a
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%cmp = fcmp oge float %neg.a, 4.0
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%select = select i1 %cmp, i32 %x, i32 %y
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store volatile i32 %select, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}test_setcc_fneg_olt_posk_f32:
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; GCN: v_cmp_lt_f32_e32 vcc, -4.0, v{{[0-9]+}}
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define void @test_setcc_fneg_olt_posk_f32() #0 {
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%a = load volatile float, float addrspace(1)* undef
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%x = load volatile i32, i32 addrspace(1)* undef
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%y = load volatile i32, i32 addrspace(1)* undef
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%neg.a = fsub float -0.0, %a
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%cmp = fcmp olt float %neg.a, 4.0
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%select = select i1 %cmp, i32 %x, i32 %y
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store volatile i32 %select, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}test_setcc_fneg_ole_posk_f32:
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; GCN: v_cmp_le_f32_e32 vcc, -4.0, v{{[0-9]+}}
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define void @test_setcc_fneg_ole_posk_f32() #0 {
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%a = load volatile float, float addrspace(1)* undef
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%x = load volatile i32, i32 addrspace(1)* undef
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%y = load volatile i32, i32 addrspace(1)* undef
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%neg.a = fsub float -0.0, %a
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%cmp = fcmp ole float %neg.a, 4.0
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%select = select i1 %cmp, i32 %x, i32 %y
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store volatile i32 %select, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}test_setcc_fneg_one_posk_f32:
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; GCN: v_cmp_lg_f32_e32 vcc, -4.0, v{{[0-9]+}}
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define void @test_setcc_fneg_one_posk_f32() #0 {
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%a = load volatile float, float addrspace(1)* undef
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%x = load volatile i32, i32 addrspace(1)* undef
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%y = load volatile i32, i32 addrspace(1)* undef
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%neg.a = fsub float -0.0, %a
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%cmp = fcmp one float %neg.a, 4.0
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%select = select i1 %cmp, i32 %x, i32 %y
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store volatile i32 %select, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}test_setcc_fneg_ueq_posk_f32:
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; GCN: v_cmp_nlg_f32_e32 vcc, -4.0, v{{[0-9]+}}
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define void @test_setcc_fneg_ueq_posk_f32() #0 {
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%a = load volatile float, float addrspace(1)* undef
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%x = load volatile i32, i32 addrspace(1)* undef
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%y = load volatile i32, i32 addrspace(1)* undef
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%neg.a = fsub float -0.0, %a
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%cmp = fcmp ueq float %neg.a, 4.0
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%select = select i1 %cmp, i32 %x, i32 %y
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store volatile i32 %select, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}test_setcc_fneg_ugt_posk_f32:
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; GCN: v_cmp_nle_f32_e32 vcc, -4.0, v{{[0-9]+}}
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define void @test_setcc_fneg_ugt_posk_f32() #0 {
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%a = load volatile float, float addrspace(1)* undef
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%x = load volatile i32, i32 addrspace(1)* undef
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%y = load volatile i32, i32 addrspace(1)* undef
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%neg.a = fsub float -0.0, %a
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%cmp = fcmp ugt float %neg.a, 4.0
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%select = select i1 %cmp, i32 %x, i32 %y
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store volatile i32 %select, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}test_setcc_fneg_uge_posk_f32:
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; GCN: v_cmp_nlt_f32_e32 vcc, -4.0, v{{[0-9]+}}
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define void @test_setcc_fneg_uge_posk_f32() #0 {
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%a = load volatile float, float addrspace(1)* undef
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%x = load volatile i32, i32 addrspace(1)* undef
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%y = load volatile i32, i32 addrspace(1)* undef
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%neg.a = fsub float -0.0, %a
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%cmp = fcmp uge float %neg.a, 4.0
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%select = select i1 %cmp, i32 %x, i32 %y
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store volatile i32 %select, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}test_setcc_fneg_ult_posk_f32:
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; GCN: v_cmp_nge_f32_e32 vcc, -4.0, v{{[0-9]+}}
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define void @test_setcc_fneg_ult_posk_f32() #0 {
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%a = load volatile float, float addrspace(1)* undef
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%x = load volatile i32, i32 addrspace(1)* undef
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%y = load volatile i32, i32 addrspace(1)* undef
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%neg.a = fsub float -0.0, %a
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%cmp = fcmp ult float %neg.a, 4.0
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%select = select i1 %cmp, i32 %x, i32 %y
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store volatile i32 %select, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}test_setcc_fneg_ule_posk_f32:
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; GCN: v_cmp_ngt_f32_e32 vcc, -4.0, v{{[0-9]+}}
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define void @test_setcc_fneg_ule_posk_f32() #0 {
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%a = load volatile float, float addrspace(1)* undef
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%x = load volatile i32, i32 addrspace(1)* undef
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%y = load volatile i32, i32 addrspace(1)* undef
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%neg.a = fsub float -0.0, %a
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%cmp = fcmp ule float %neg.a, 4.0
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%select = select i1 %cmp, i32 %x, i32 %y
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store volatile i32 %select, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}test_setcc_fneg_une_posk_f32:
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; GCN: v_cmp_neq_f32_e32 vcc, -4.0, v{{[0-9]+}}
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define void @test_setcc_fneg_une_posk_f32() #0 {
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%a = load volatile float, float addrspace(1)* undef
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%x = load volatile i32, i32 addrspace(1)* undef
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%y = load volatile i32, i32 addrspace(1)* undef
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%neg.a = fsub float -0.0, %a
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%cmp = fcmp une float %neg.a, 4.0
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%select = select i1 %cmp, i32 %x, i32 %y
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store volatile i32 %select, i32 addrspace(1)* undef
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ret void
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}
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attributes #0 = { nounwind }
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@ -9,7 +9,7 @@
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; Test f32
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define float @f1(float %a, float %b, float %f) {
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; CHECK-LABEL: f1:
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; CHECK: lcebr
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; CHECK: ltebr
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; CHECK-NEXT: ber %r14
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%neg = fsub float -0.0, %f
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%cond = fcmp oeq float %neg, 0.0
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@ -20,7 +20,7 @@ define float @f1(float %a, float %b, float %f) {
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; Test f64
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define double @f2(double %a, double %b, double %f) {
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; CHECK-LABEL: f2:
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; CHECK: lcdbr
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; CHECK: ltdbr
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; CHECK-NEXT: ber %r14
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%neg = fsub double -0.0, %f
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%cond = fcmp oeq double %neg, 0.0
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@ -33,7 +33,7 @@ define double @f2(double %a, double %b, double %f) {
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declare float @llvm.fabs.f32(float %f)
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define float @f3(float %a, float %b, float %f) {
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; CHECK-LABEL: f3:
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; CHECK: lnebr
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; CHECK: lpebr
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; CHECK-NEXT: ber %r14
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%abs = call float @llvm.fabs.f32(float %f)
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%neg = fsub float -0.0, %abs
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@ -46,7 +46,7 @@ define float @f3(float %a, float %b, float %f) {
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declare double @llvm.fabs.f64(double %f)
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define double @f4(double %a, double %b, double %f) {
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; CHECK-LABEL: f4:
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; CHECK: lndbr
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; CHECK: lpdbr
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; CHECK-NEXT: ber %r14
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%abs = call double @llvm.fabs.f64(double %f)
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%neg = fsub double -0.0, %abs
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@ -1,9 +1,9 @@
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; RUN: llc < %s -march=xcore | FileCheck %s
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define i1 @test(double %F) nounwind {
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define i1 @test(double %F, double %G) nounwind {
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entry:
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; CHECK-LABEL: test:
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; CHECK: xor
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%0 = fsub double -0.000000e+00, %F
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%1 = fcmp olt double 0.000000e+00, %0
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%1 = fcmp olt double %G, %0
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ret i1 %1
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}
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