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R600/SI: Remove modifier operands from V_CNDMASK_B32_e64
Modifiers don't work for this instruction. llvm-svn: 218253
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@ -1317,9 +1317,8 @@ def V_CNDMASK_B32_e32 : VOP2 <0x00000000, (outs VReg_32:$dst),
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}
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def V_CNDMASK_B32_e64 : VOP3 <0x00000100, (outs VReg_32:$dst),
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(ins VSrc_32:$src0, VSrc_32:$src1, SSrc_64:$src2,
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InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg),
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"V_CNDMASK_B32_e64 $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg",
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(ins VSrc_32:$src0, VSrc_32:$src1, SSrc_64:$src2),
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"V_CNDMASK_B32_e64 $dst, $src0, $src1, $src2",
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[(set i32:$dst, (select i1:$src2, i32:$src1, i32:$src0))]
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> {
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let src0_modifiers = 0;
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@ -127,11 +127,7 @@ bool SILowerI1Copies::runOnMachineFunction(MachineFunction &MF) {
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.addOperand(MI.getOperand(0))
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.addImm(0)
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.addImm(-1)
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.addOperand(MI.getOperand(1))
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.addImm(0)
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.addImm(0)
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.addImm(0)
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.addImm(0);
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.addOperand(MI.getOperand(1));
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MI.eraseFromParent();
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} else if (TRI->getCommonSubClass(DstRC, &AMDGPU::SGPR_64RegClass) &&
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SrcRC == &AMDGPU::VReg_1RegClass) {
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