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[PowerPC-QPX] adjust operands order of qpx fma instructions.
convert %3 = QVFMADD %2, %0, %1, implicit $rm to %3 = QVFMADD %2, %1, %0, implicit $rm Reviewed By: hfinkel, steven.zhang Differential Revision: https://reviews.llvm.org/D78986
This commit is contained in:
Chen Zheng
parent
8ff874aead
commit
67a09d59fc
@ -167,48 +167,48 @@ let Uses = [RM] in {
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// Multiply-add instructions
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def QVFMADD : AForm_1<4, 29,
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(outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRB, qfrc:$FRC),
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(outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRC, qfrc:$FRB),
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"qvfmadd $FRT, $FRA, $FRC, $FRB", IIC_FPFused,
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[(set v4f64:$FRT, (fma v4f64:$FRA, v4f64:$FRC, v4f64:$FRB))]>;
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let isCodeGenOnly = 1 in
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def QVFMADDS : QPXA1_Int<0, 29, "qvfmadds", int_ppc_qpx_qvfmadds>;
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def QVFMADDSs : AForm_1<0, 29,
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(outs qsrc:$FRT), (ins qsrc:$FRA, qsrc:$FRB, qsrc:$FRC),
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(outs qsrc:$FRT), (ins qsrc:$FRA, qsrc:$FRC, qsrc:$FRB),
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"qvfmadds $FRT, $FRA, $FRC, $FRB", IIC_FPFused,
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[(set v4f32:$FRT, (fma v4f32:$FRA, v4f32:$FRC, v4f32:$FRB))]>;
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def QVFNMADD : AForm_1<4, 31,
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(outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRB, qfrc:$FRC),
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(outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRC, qfrc:$FRB),
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"qvfnmadd $FRT, $FRA, $FRC, $FRB", IIC_FPFused,
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[(set v4f64:$FRT, (fneg (fma v4f64:$FRA, v4f64:$FRC,
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v4f64:$FRB)))]>;
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let isCodeGenOnly = 1 in
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def QVFNMADDS : QPXA1_Int<0, 31, "qvfnmadds", int_ppc_qpx_qvfnmadds>;
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def QVFNMADDSs : AForm_1<0, 31,
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(outs qsrc:$FRT), (ins qsrc:$FRA, qsrc:$FRB, qsrc:$FRC),
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(outs qsrc:$FRT), (ins qsrc:$FRA, qsrc:$FRC, qsrc:$FRB),
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"qvfnmadds $FRT, $FRA, $FRC, $FRB", IIC_FPFused,
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[(set v4f32:$FRT, (fneg (fma v4f32:$FRA, v4f32:$FRC,
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v4f32:$FRB)))]>;
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def QVFMSUB : AForm_1<4, 28,
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(outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRB, qfrc:$FRC),
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(outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRC, qfrc:$FRB),
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"qvfmsub $FRT, $FRA, $FRC, $FRB", IIC_FPFused,
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[(set v4f64:$FRT, (fma v4f64:$FRA, v4f64:$FRC,
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(fneg v4f64:$FRB)))]>;
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let isCodeGenOnly = 1 in
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def QVFMSUBS : QPXA1_Int<0, 28, "qvfmsubs", int_ppc_qpx_qvfmsubs>;
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def QVFMSUBSs : AForm_1<0, 28,
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(outs qsrc:$FRT), (ins qsrc:$FRA, qsrc:$FRB, qsrc:$FRC),
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(outs qsrc:$FRT), (ins qsrc:$FRA, qsrc:$FRC, qsrc:$FRB),
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"qvfmsubs $FRT, $FRA, $FRC, $FRB", IIC_FPFused,
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[(set v4f32:$FRT, (fma v4f32:$FRA, v4f32:$FRC,
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(fneg v4f32:$FRB)))]>;
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def QVFNMSUB : AForm_1<4, 30,
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(outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRB, qfrc:$FRC),
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(outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRC, qfrc:$FRB),
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"qvfnmsub $FRT, $FRA, $FRC, $FRB", IIC_FPFused,
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[(set v4f64:$FRT, (fneg (fma v4f64:$FRA, v4f64:$FRC,
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(fneg v4f64:$FRB))))]>;
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let isCodeGenOnly = 1 in
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def QVFNMSUBS : QPXA1_Int<0, 30, "qvfnmsubs", int_ppc_qpx_qvfnmsubs>;
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def QVFNMSUBSs : AForm_1<0, 30,
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(outs qsrc:$FRT), (ins qsrc:$FRA, qsrc:$FRB, qsrc:$FRC),
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(outs qsrc:$FRT), (ins qsrc:$FRA, qsrc:$FRC, qsrc:$FRB),
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"qvfnmsubs $FRT, $FRA, $FRC, $FRB", IIC_FPFused,
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[(set v4f32:$FRT, (fneg (fma v4f32:$FRA, v4f32:$FRC,
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(fneg v4f32:$FRB))))]>;
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@ -899,13 +899,13 @@ def : Pat<(int_ppc_qpx_qvfmul v4f64:$A, v4f64:$B),
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// Additional QVFNMSUB patterns: -a*c + b == -(a*c - b)
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def : Pat<(fma (fneg v4f64:$A), v4f64:$C, v4f64:$B),
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(QVFNMSUB $A, $B, $C)>;
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(QVFNMSUB $A, $C, $B)>;
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def : Pat<(fma v4f64:$A, (fneg v4f64:$C), v4f64:$B),
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(QVFNMSUB $A, $B, $C)>;
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(QVFNMSUB $A, $C, $B)>;
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def : Pat<(fma (fneg v4f32:$A), v4f32:$C, v4f32:$B),
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(QVFNMSUBSs $A, $B, $C)>;
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(QVFNMSUBSs $A, $C, $B)>;
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def : Pat<(fma v4f32:$A, (fneg v4f32:$C), v4f32:$B),
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(QVFNMSUBSs $A, $B, $C)>;
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(QVFNMSUBSs $A, $C, $B)>;
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def : Pat<(int_ppc_qpx_qvfmadd v4f64:$A, v4f64:$B, v4f64:$C),
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(QVFMADD $A, $B, $C)>;
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@ -3,7 +3,7 @@ target triple = "powerpc64-bgq-linux"
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define <2 x double> @test_qvfmadd(<2 x double> %0, <2 x double> %1, <2 x double> %2) {
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; CHECK: test_qvfmadd
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; CHECK: QVFMADD %2, %0, %1, implicit $rm
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; CHECK: QVFMADD %2, %1, %0, implicit $rm
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;
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%4 = fmul reassoc nsz <2 x double> %2, %1
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%5 = fadd reassoc nsz <2 x double> %4, %0
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@ -12,7 +12,7 @@ define <2 x double> @test_qvfmadd(<2 x double> %0, <2 x double> %1, <2 x double>
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define <4 x float> @test_qvfmadds(<4 x float> %0, <4 x float> %1, <4 x float> %2) {
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; CHECK: test_qvfmadds
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; CHECK: QVFMADDSs %2, %0, %1, implicit $rm
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; CHECK: QVFMADDSs %2, %1, %0, implicit $rm
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;
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%4 = fmul reassoc nsz <4 x float> %2, %1
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%5 = fadd reassoc nsz <4 x float> %4, %0
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@ -21,7 +21,7 @@ define <4 x float> @test_qvfmadds(<4 x float> %0, <4 x float> %1, <4 x float> %2
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define <2 x double> @test_qvfnmadd(<2 x double> %0, <2 x double> %1, <2 x double> %2) {
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; CHECK: test_qvfnmadd
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; CHECK: QVFNMADD %2, %0, %1, implicit $rm
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; CHECK: QVFNMADD %2, %1, %0, implicit $rm
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;
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%4 = fmul reassoc nsz <2 x double> %2, %1
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%5 = fadd reassoc nsz <2 x double> %4, %0
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@ -31,7 +31,7 @@ define <2 x double> @test_qvfnmadd(<2 x double> %0, <2 x double> %1, <2 x double
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define <4 x float> @test_qvfnmadds(<4 x float> %0, <4 x float> %1, <4 x float> %2) {
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; CHECK: test_qvfnmadds
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; CHECK: QVFNMADDSs %2, %0, %1, implicit $rm
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; CHECK: QVFNMADDSs %2, %1, %0, implicit $rm
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;
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%4 = fmul reassoc nsz <4 x float> %2, %1
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%5 = fadd reassoc nsz <4 x float> %4, %0
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@ -41,7 +41,7 @@ define <4 x float> @test_qvfnmadds(<4 x float> %0, <4 x float> %1, <4 x float> %
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define <2 x double> @test_qvfmsub(<2 x double> %0, <2 x double> %1, <2 x double> %2) {
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; CHECK: test_qvfmsub
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; CHECK: QVFMSUB %2, %0, %1, implicit $rm
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; CHECK: QVFMSUB %2, %1, %0, implicit $rm
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;
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%4 = fmul reassoc nsz <2 x double> %2, %1
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%5 = fsub reassoc nsz <2 x double> %4, %0
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@ -50,7 +50,7 @@ define <2 x double> @test_qvfmsub(<2 x double> %0, <2 x double> %1, <2 x double>
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define <4 x float> @test_qvfmsubs(<4 x float> %0, <4 x float> %1, <4 x float> %2) {
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; CHECK: test_qvfmsubs
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; CHECK: QVFMSUBSs %2, %0, %1, implicit $rm
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; CHECK: QVFMSUBSs %2, %1, %0, implicit $rm
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;
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%4 = fmul reassoc nsz <4 x float> %2, %1
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%5 = fsub reassoc nsz <4 x float> %4, %0
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@ -59,7 +59,7 @@ define <4 x float> @test_qvfmsubs(<4 x float> %0, <4 x float> %1, <4 x float> %2
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define <2 x double> @test_qvfnmsub(<2 x double> %0, <2 x double> %1, <2 x double> %2) {
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; CHECK: test_qvfnmsub
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; CHECK: QVFNMSUB %2, %0, %1, implicit $rm
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; CHECK: QVFNMSUB %2, %1, %0, implicit $rm
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;
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%4 = fmul reassoc nsz <2 x double> %2, %1
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%5 = fsub reassoc nsz <2 x double> %4, %0
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@ -69,7 +69,7 @@ define <2 x double> @test_qvfnmsub(<2 x double> %0, <2 x double> %1, <2 x double
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define <4 x float> @test_qvfnmsubs(<4 x float> %0, <4 x float> %1, <4 x float> %2) {
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; CHECK: test_qvfnmsubs
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; CHECK: QVFNMSUBSs %2, %0, %1, implicit $rm
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; CHECK: QVFNMSUBSs %2, %1, %0, implicit $rm
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;
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%4 = fmul reassoc nsz <4 x float> %2, %1
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%5 = fsub reassoc nsz <4 x float> %4, %0
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