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[llvm] Use static_assert instead of assert (NFC)

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Identified with misc-static-assert.
This commit is contained in:
Kazu Hirata 2021-01-22 23:25:05 -08:00
parent 0069e576c3
commit 67c2d74113
6 changed files with 14 additions and 11 deletions
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4
include/llvm/IR/InstrTypes.h
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@ -802,8 +802,8 @@ public:
void setPredicate(Predicate P) { setSubclassData<PredicateField>(P); }
static bool isFPPredicate(Predicate P) {
assert(FIRST_FCMP_PREDICATE == 0 &&
"FIRST_FCMP_PREDICATE is required to be 0");
static_assert(FIRST_FCMP_PREDICATE == 0,
"FIRST_FCMP_PREDICATE is required to be 0");
return P <= LAST_FCMP_PREDICATE;
}

3
lib/Object/XCOFFObjectFile.cpp
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@ -655,7 +655,8 @@ XCOFFObjectFile::relocations(const XCOFFSectionHeader32 &Sec) const {
uint32_t NumRelocEntries = NumRelocEntriesOrErr.get();
assert(sizeof(XCOFFRelocation32) == XCOFF::RelocationSerializationSize32);
static_assert(
sizeof(XCOFFRelocation32) == XCOFF::RelocationSerializationSize32, "");
auto RelocationOrErr =
getObject<XCOFFRelocation32>(Data, reinterpret_cast<void *>(RelocAddr),
NumRelocEntries * sizeof(XCOFFRelocation32));

2
lib/Support/SHA1.cpp
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@ -225,7 +225,7 @@ void SHA1::update(ArrayRef<uint8_t> Data) {
// Fast buffer filling for large inputs.
while (Data.size() >= BLOCK_LENGTH) {
assert(InternalState.BufferOffset == 0);
assert(BLOCK_LENGTH % 4 == 0);
static_assert(BLOCK_LENGTH % 4 == 0, "");
constexpr size_t BLOCK_LENGTH_32 = BLOCK_LENGTH / 4;
for (size_t I = 0; I < BLOCK_LENGTH_32; ++I)
InternalState.Buffer.L[I] = support::endian::read32be(&Data[I * 4]);

6
lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
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@ -1015,7 +1015,8 @@ MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) c
: getVgprClassId(Width), Val - VGPR_MIN);
}
if (Val <= SGPR_MAX) {
assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning.
// "SGPR_MIN <= Val" is always true and causes compilation warning.
static_assert(SGPR_MIN == 0, "");
return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN);
}
@ -1052,7 +1053,8 @@ MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) c
assert(Width == OPW256 || Width == OPW512);
if (Val <= SGPR_MAX) {
assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning.
// "SGPR_MIN <= Val" is always true and causes compilation warning.
static_assert(SGPR_MIN == 0, "");
return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN);
}

8
lib/Target/X86/X86InsertPrefetch.cpp
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@ -214,10 +214,10 @@ bool X86InsertPrefetch::runOnMachineFunction(MachineFunction &MF) {
MF.CreateMachineInstr(Desc, Current->getDebugLoc(), true);
MachineInstrBuilder MIB(MF, PFetch);
assert(X86::AddrBaseReg == 0 && X86::AddrScaleAmt == 1 &&
X86::AddrIndexReg == 2 && X86::AddrDisp == 3 &&
X86::AddrSegmentReg == 4 &&
"Unexpected change in X86 operand offset order.");
static_assert(X86::AddrBaseReg == 0 && X86::AddrScaleAmt == 1 &&
X86::AddrIndexReg == 2 && X86::AddrDisp == 3 &&
X86::AddrSegmentReg == 4,
"Unexpected change in X86 operand offset order.");
// This assumes X86::AddBaseReg = 0, {...}ScaleAmt = 1, etc.
// FIXME(mtrofin): consider adding a:

2
utils/TableGen/X86DisassemblerTables.cpp
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@ -763,7 +763,7 @@ void DisassemblerTables::emitOpcodeDecision(raw_ostream &o1, raw_ostream &o2,
}
if (index == 256) {
// If all 256 entries are MODRM_ONEENTRY, omit output.
assert(MODRM_ONEENTRY == 0);
static_assert(MODRM_ONEENTRY == 0, "");
--i2;
o2 << "},\n";
} else {