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[msan] Instrument x86.pclmulqdq* intrinsics.
Summary: These instructions ignore parts of the input vectors which makes the default MSan handling too strict and causes false positive reports. Reviewers: vitalybuka, RKSimon, thakis Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D73374
This commit is contained in:
Evgenii Stepanov
parent
3ef629d443
commit
67d6f58389
@ -3000,6 +3000,43 @@ struct MemorySanitizerVisitor : public InstVisitor<MemorySanitizerVisitor> {
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setOriginForNaryOp(I);
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}
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Constant *getPclmulMask(IRBuilder<> &IRB, unsigned Width, bool OddElements) {
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SmallVector<Constant *, 8> Mask;
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for (unsigned X = OddElements ? 1 : 0; X < Width; X += 2) {
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Constant *C = ConstantInt::get(IRB.getInt32Ty(), X);
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Mask.push_back(C);
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Mask.push_back(C);
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}
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return ConstantVector::get(Mask);
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}
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// Instrument pclmul intrinsics.
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// These intrinsics operate either on odd or on even elements of the input
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// vectors, depending on the constant in the 3rd argument, ignoring the rest.
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// Replace the unused elements with copies of the used ones, ex:
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// (0, 1, 2, 3) -> (0, 0, 2, 2) (even case)
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// or
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// (0, 1, 2, 3) -> (1, 1, 3, 3) (odd case)
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// and then apply the usual shadow combining logic.
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void handlePclmulIntrinsic(IntrinsicInst &I) {
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IRBuilder<> IRB(&I);
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Type *ShadowTy = getShadowTy(&I);
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unsigned Width = I.getArgOperand(0)->getType()->getVectorNumElements();
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assert(isa<ConstantInt>(I.getArgOperand(2)) &&
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"pclmul 3rd operand must be a constant");
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unsigned Imm = cast<ConstantInt>(I.getArgOperand(2))->getZExtValue();
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Value *Shuf0 =
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IRB.CreateShuffleVector(getShadow(&I, 0), UndefValue::get(ShadowTy),
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getPclmulMask(IRB, Width, Imm & 0x01));
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Value *Shuf1 =
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IRB.CreateShuffleVector(getShadow(&I, 1), UndefValue::get(ShadowTy),
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getPclmulMask(IRB, Width, Imm & 0x10));
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ShadowAndOriginCombiner SOC(this, IRB);
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SOC.Add(Shuf0, getOrigin(&I, 0));
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SOC.Add(Shuf1, getOrigin(&I, 1));
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SOC.Done(&I);
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}
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void visitIntrinsicInst(IntrinsicInst &I) {
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switch (I.getIntrinsicID()) {
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case Intrinsic::lifetime_start:
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@ -3233,6 +3270,12 @@ struct MemorySanitizerVisitor : public InstVisitor<MemorySanitizerVisitor> {
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handleBmiIntrinsic(I);
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break;
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case Intrinsic::x86_pclmulqdq:
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case Intrinsic::x86_pclmulqdq_256:
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case Intrinsic::x86_pclmulqdq_512:
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handlePclmulIntrinsic(I);
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break;
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case Intrinsic::is_constant:
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// The result of llvm.is.constant() is always defined.
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setShadow(&I, getCleanShadow(&I));
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72
test/Instrumentation/MemorySanitizer/clmul.ll
Normal file
72
test/Instrumentation/MemorySanitizer/clmul.ll
Normal file
@ -0,0 +1,72 @@
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; RUN: opt < %s -msan-check-access-address=0 -S -passes=msan 2>&1 | FileCheck \
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; RUN: %s
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; RUN: opt < %s -msan -msan-check-access-address=0 -S | FileCheck %s
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; RUN: opt < %s -msan -msan-check-access-address=0 -msan-track-origins=1 -S | FileCheck %s --check-prefixes=CHECK,ORIGIN
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; REQUIRES: x86-registered-target
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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declare <2 x i64> @llvm.x86.pclmulqdq(<2 x i64>, <2 x i64>, i8 immarg) nounwind readnone
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declare <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64>, <4 x i64>, i8 immarg) nounwind readnone
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declare <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64>, <8 x i64>, i8 immarg) nounwind readnone
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define <2 x i64> @clmul00(<2 x i64> %a, <2 x i64> %b) sanitize_memory {
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entry:
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%0 = tail call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %a, <2 x i64> %b, i8 0)
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ret <2 x i64> %0
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}
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; CHECK-LABEL: @clmul00
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; CHECK: %[[S0:.*]] = load <2 x i64>, <2 x i64>* {{.*}}@__msan_param_tls
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; CHECK: %[[S1:.*]] = load <2 x i64>, <2 x i64>* {{.*}}@__msan_param_tls
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; CHECK: %[[SHUF1:.*]] = shufflevector <2 x i64> %[[S1]], <2 x i64> undef, <2 x i32> zeroinitializer
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; CHECK: %[[SHUF0:.*]] = shufflevector <2 x i64> %[[S0]], <2 x i64> undef, <2 x i32> zeroinitializer
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; CHECK: %[[SRET:.*]] = or <2 x i64> %[[SHUF1]], %[[SHUF0]]
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; CHECK: store <2 x i64> %[[SRET]], <2 x i64>* {{.*}}@__msan_retval_tls
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define <2 x i64> @clmul10(<2 x i64> %a, <2 x i64> %b) sanitize_memory {
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entry:
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%0 = tail call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %a, <2 x i64> %b, i8 16)
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ret <2 x i64> %0
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}
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; CHECK-LABEL: @clmul10
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; CHECK: %[[S0:.*]] = load <2 x i64>, <2 x i64>* {{.*}}@__msan_param_tls
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; CHECK: %[[S1:.*]] = load <2 x i64>, <2 x i64>* {{.*}}@__msan_param_tls
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; CHECK: %[[SHUF1:.*]] = shufflevector <2 x i64> %[[S1]], <2 x i64> undef, <2 x i32> zeroinitializer
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; CHECK: %[[SHUF0:.*]] = shufflevector <2 x i64> %[[S0]], <2 x i64> undef, <2 x i32> <i32 1, i32 1>
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; CHECK: %[[SRET:.*]] = or <2 x i64> %[[SHUF1]], %[[SHUF0]]
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; CHECK: store <2 x i64> %[[SRET]], <2 x i64>* {{.*}}@__msan_retval_tls
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define <4 x i64> @clmul11_256(<4 x i64> %a, <4 x i64> %b) sanitize_memory {
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entry:
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%0 = tail call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> %a, <4 x i64> %b, i8 17)
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ret <4 x i64> %0
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}
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; CHECK-LABEL: @clmul11_256
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; CHECK: %[[S0:.*]] = load <4 x i64>, <4 x i64>* {{.*}}@__msan_param_tls
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; CHECK: %[[S1:.*]] = load <4 x i64>, <4 x i64>* {{.*}}@__msan_param_tls
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; CHECK: %[[SHUF1:.*]] = shufflevector <4 x i64> %[[S1]], <4 x i64> undef, <4 x i32> <i32 1, i32 1, i32 3, i32 3>
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; CHECK: %[[SHUF0:.*]] = shufflevector <4 x i64> %[[S0]], <4 x i64> undef, <4 x i32> <i32 1, i32 1, i32 3, i32 3>
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; CHECK: %[[SRET:.*]] = or <4 x i64> %[[SHUF1]], %[[SHUF0]]
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; CHECK: store <4 x i64> %[[SRET]], <4 x i64>* {{.*}}@__msan_retval_tls
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define <8 x i64> @clmul01_512(<8 x i64> %a, <8 x i64> %b) sanitize_memory {
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entry:
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%0 = tail call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> %a, <8 x i64> %b, i8 16)
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ret <8 x i64> %0
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}
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; CHECK-LABEL: @clmul01_512
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; CHECK: %[[S0:.*]] = load <8 x i64>, <8 x i64>* {{.*}}@__msan_param_tls
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; CHECK: %[[S1:.*]] = load <8 x i64>, <8 x i64>* {{.*}}@__msan_param_tls
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; CHECK: %[[SHUF1:.*]] = shufflevector <8 x i64> %[[S1]], <8 x i64> undef, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6>
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; CHECK: %[[SHUF0:.*]] = shufflevector <8 x i64> %[[S0]], <8 x i64> undef, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7>
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; CHECK: %[[SRET:.*]] = or <8 x i64> %[[SHUF1]], %[[SHUF0]]
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; ORIGIN: %[[FLAT:.*]] = bitcast <8 x i64> %[[SHUF0]] to i512
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; ORIGIN: %[[I:.*]] = icmp ne i512 %[[FLAT]], 0
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; ORIGIN: %[[O:.*]] = select i1 %[[I]],
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; CHECK: store <8 x i64> %[[SRET]], <8 x i64>* {{.*}}@__msan_retval_tls
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; ORIGIN: store i32 %[[O]], i32* @__msan_retval_origin_tls
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