diff --git a/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 6e65e925062..1dfae8d0ba7 100644
--- a/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -291,6 +291,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
                                  {p0, p0, 64, 8},
                                  {s128, p0, 128, 8},
                                  {v16s8, p0, 128, 8},
+                                 {v8s8, p0, 64, 8},
                                  {v4s16, p0, 64, 8},
                                  {v8s16, p0, 128, 8},
                                  {v2s32, p0, 64, 8},
diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir b/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
index 504fb1a12b5..61104c6e432 100644
--- a/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
+++ b/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
@@ -1,59 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
-
---- |
-  target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
-  target triple = "aarch64"
-
-  define void @test_load() { ret void }
-  define void @test_store() { ret void }
-
-  define void @store_4xi16(<4 x i16> %v, <4 x i16>* %ptr) {
-    store <4 x i16> %v, <4 x i16>* %ptr
-    ret void
-  }
-
-  define void @store_4xi32(<4 x i32> %v, <4 x i32>* %ptr) {
-    store <4 x i32> %v, <4 x i32>* %ptr
-    ret void
-  }
-
-  define void @store_8xi16(<8 x i16> %v, <8 x i16>* %ptr) {
-    store <8 x i16> %v, <8 x i16>* %ptr
-    ret void
-  }
-
-  define void @store_16xi8(<16 x i8> %v, <16 x i8>* %ptr) {
-    store <16 x i8> %v, <16 x i8>* %ptr
-    ret void
-  }
-
-  define <4 x i16> @load_4xi16(<4 x i16>* %ptr) {
-    %res = load <4 x i16>, <4 x i16>* %ptr
-    ret <4 x i16> %res
-  }
-
-  define <4 x i32> @load_4xi32(<4 x i32>* %ptr) {
-    %res = load <4 x i32>, <4 x i32>* %ptr
-    ret <4 x i32> %res
-  }
-
-  define <8 x i16> @load_8xi16(<8 x i16>* %ptr) {
-    %res = load <8 x i16>, <8 x i16>* %ptr
-    ret <8 x i16> %res
-  }
-
-  define <16 x i8> @load_16xi8(<16 x i8>* %ptr) {
-    %res = load <16 x i8>, <16 x i8>* %ptr
-    ret <16 x i8> %res
-  }
-
-  define <8 x i8> @load_8xi8(<8 x i8>* %ptr) {
-    %res = load <8 x i8>, <8 x i8>* %ptr
-    ret <8 x i8> %res
-  }
-
-...
+# RUN: llc -O0 -march=aarch64 -run-pass=legalizer -global-isel-abort=1 %s -o - | FileCheck %s
 ---
 name:            test_load
 body: |
@@ -155,18 +101,18 @@ alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
-  bb.1 (%ir-block.0):
+  bb.1:
     liveins: $d0, $x0
 
     ; CHECK-LABEL: name: store_4xi16
     ; CHECK: liveins: $d0, $x0
     ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
     ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x0
-    ; CHECK: G_STORE [[COPY]](<4 x s16>), [[COPY1]](p0) :: (store 8 into %ir.ptr)
+    ; CHECK: G_STORE [[COPY]](<4 x s16>), [[COPY1]](p0) :: (store 8)
     ; CHECK: RET_ReallyLR
     %0:_(<4 x s16>) = COPY $d0
     %1:_(p0) = COPY $x0
-    G_STORE %0(<4 x s16>), %1(p0) :: (store 8 into %ir.ptr)
+    G_STORE %0(<4 x s16>), %1(p0) :: (store 8)
     RET_ReallyLR
 
 ...
@@ -176,18 +122,18 @@ alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
-  bb.1 (%ir-block.0):
+  bb.1:
     liveins: $q0, $x0
 
     ; CHECK-LABEL: name: store_4xi32
     ; CHECK: liveins: $q0, $x0
     ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
     ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x0
-    ; CHECK: G_STORE [[COPY]](<4 x s32>), [[COPY1]](p0) :: (store 16 into %ir.ptr)
+    ; CHECK: G_STORE [[COPY]](<4 x s32>), [[COPY1]](p0) :: (store 16)
     ; CHECK: RET_ReallyLR
     %0:_(<4 x s32>) = COPY $q0
     %1:_(p0) = COPY $x0
-    G_STORE %0(<4 x s32>), %1(p0) :: (store 16 into %ir.ptr)
+    G_STORE %0(<4 x s32>), %1(p0) :: (store 16)
     RET_ReallyLR
 
 ...
@@ -197,18 +143,18 @@ alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
-  bb.1 (%ir-block.0):
+  bb.1:
     liveins: $q0, $x0
 
     ; CHECK-LABEL: name: store_8xi16
     ; CHECK: liveins: $q0, $x0
     ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
     ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x0
-    ; CHECK: G_STORE [[COPY]](<8 x s16>), [[COPY1]](p0) :: (store 16 into %ir.ptr)
+    ; CHECK: G_STORE [[COPY]](<8 x s16>), [[COPY1]](p0) :: (store 16)
     ; CHECK: RET_ReallyLR
     %0:_(<8 x s16>) = COPY $q0
     %1:_(p0) = COPY $x0
-    G_STORE %0(<8 x s16>), %1(p0) :: (store 16 into %ir.ptr)
+    G_STORE %0(<8 x s16>), %1(p0) :: (store 16)
     RET_ReallyLR
 
 ...
@@ -218,18 +164,18 @@ alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
-  bb.1 (%ir-block.0):
+  bb.1:
     liveins: $q0, $x0
 
     ; CHECK-LABEL: name: store_16xi8
     ; CHECK: liveins: $q0, $x0
     ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
     ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x0
-    ; CHECK: G_STORE [[COPY]](<16 x s8>), [[COPY1]](p0) :: (store 16 into %ir.ptr)
+    ; CHECK: G_STORE [[COPY]](<16 x s8>), [[COPY1]](p0) :: (store 16)
     ; CHECK: RET_ReallyLR
     %0:_(<16 x s8>) = COPY $q0
     %1:_(p0) = COPY $x0
-    G_STORE %0(<16 x s8>), %1(p0) :: (store 16 into %ir.ptr)
+    G_STORE %0(<16 x s8>), %1(p0) :: (store 16)
     RET_ReallyLR
 
 ...
@@ -239,17 +185,17 @@ alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
-  bb.1 (%ir-block.0):
+  bb.1:
     liveins: $x0
 
     ; CHECK-LABEL: name: load_4xi16
     ; CHECK: liveins: $x0
     ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
-    ; CHECK: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[COPY]](p0) :: (load 8 from %ir.ptr)
+    ; CHECK: [[LOAD:%[0-9]+]]:_(<4 x s16>) = G_LOAD [[COPY]](p0) :: (load 8)
     ; CHECK: $d0 = COPY [[LOAD]](<4 x s16>)
     ; CHECK: RET_ReallyLR implicit $d0
     %0:_(p0) = COPY $x0
-    %1:_(<4 x s16>) = G_LOAD %0(p0) :: (load 8 from %ir.ptr)
+    %1:_(<4 x s16>) = G_LOAD %0(p0) :: (load 8)
     $d0 = COPY %1(<4 x s16>)
     RET_ReallyLR implicit $d0
 
@@ -260,17 +206,17 @@ alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
-  bb.1 (%ir-block.0):
+  bb.1:
     liveins: $x0
 
     ; CHECK-LABEL: name: load_4xi32
     ; CHECK: liveins: $x0
     ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
-    ; CHECK: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.ptr)
+    ; CHECK: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16)
     ; CHECK: $q0 = COPY [[LOAD]](<4 x s32>)
     ; CHECK: RET_ReallyLR implicit $q0
     %0:_(p0) = COPY $x0
-    %1:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.ptr)
+    %1:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16)
     $q0 = COPY %1(<4 x s32>)
     RET_ReallyLR implicit $q0
 
@@ -281,17 +227,17 @@ alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
-  bb.1 (%ir-block.0):
+  bb.1:
     liveins: $x0
 
     ; CHECK-LABEL: name: load_8xi16
     ; CHECK: liveins: $x0
     ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
-    ; CHECK: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.ptr)
+    ; CHECK: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load 16)
     ; CHECK: $q0 = COPY [[LOAD]](<8 x s16>)
     ; CHECK: RET_ReallyLR implicit $q0
     %0:_(p0) = COPY $x0
-    %1:_(<8 x s16>) = G_LOAD %0(p0) :: (load 16 from %ir.ptr)
+    %1:_(<8 x s16>) = G_LOAD %0(p0) :: (load 16)
     $q0 = COPY %1(<8 x s16>)
     RET_ReallyLR implicit $q0
 
@@ -302,17 +248,17 @@ alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
-  bb.1 (%ir-block.0):
+  bb.1:
     liveins: $x0
 
     ; CHECK-LABEL: name: load_16xi8
     ; CHECK: liveins: $x0
     ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
-    ; CHECK: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16 from %ir.ptr)
+    ; CHECK: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16)
     ; CHECK: $q0 = COPY [[LOAD]](<16 x s8>)
     ; CHECK: RET_ReallyLR implicit $q0
     %0:_(p0) = COPY $x0
-    %1:_(<16 x s8>) = G_LOAD %0(p0) :: (load 16 from %ir.ptr)
+    %1:_(<16 x s8>) = G_LOAD %0(p0) :: (load 16)
     $q0 = COPY %1(<16 x s8>)
     RET_ReallyLR implicit $q0
 
@@ -323,17 +269,36 @@ alignment:       4
 tracksRegLiveness: true
 machineFunctionInfo: {}
 body:             |
-  bb.1 (%ir-block.0):
+  bb.1:
     liveins: $x0
     ; CHECK-LABEL: name: load_8xi8
     ; CHECK: liveins: $x0
     ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
-    ; CHECK: [[LOAD:%[0-9]+]]:_(<8 x s8>) = G_LOAD [[COPY]](p0) :: (load 8 from %ir.ptr)
+    ; CHECK: [[LOAD:%[0-9]+]]:_(<8 x s8>) = G_LOAD [[COPY]](p0) :: (load 8)
     ; CHECK: $d0 = COPY [[LOAD]](<8 x s8>)
     ; CHECK: RET_ReallyLR implicit $d0
     %0:_(p0) = COPY $x0
-    %1:_(<8 x s8>) = G_LOAD %0(p0) :: (load 8 from %ir.ptr)
+    %1:_(<8 x s8>) = G_LOAD %0(p0) :: (load 8)
     $d0 = COPY %1(<8 x s8>)
     RET_ReallyLR implicit $d0
 
 ...
+---
+name:            store_8xi8
+alignment:       4
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body:             |
+  bb.1:
+    liveins: $x0, $d0
+    ; CHECK-LABEL: name: store_8xi8
+    ; CHECK: liveins: $x0, $d0
+    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+    ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d0
+    ; CHECK: G_STORE [[COPY1]](<8 x s8>), [[COPY]](p0) :: (store 8)
+    ; CHECK: RET_ReallyLR
+    %0:_(p0) = COPY $x0
+    %1:_(<8 x s8>) = COPY $d0
+    G_STORE %1(<8 x s8>), %0(p0) :: (store 8)
+    RET_ReallyLR
+...