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Handle perfect shuffle case that generates a vrev for vectors of floats.

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Add test case.

llvm-svn: 131582
This commit is contained in:
Tanya Lattner 2011-05-18 21:44:54 +00:00
parent e1ee02ff3d
commit 6814933ea6
2 changed files with 17 additions and 1 deletions
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3
lib/Target/ARM/ARMISelLowering.cpp
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@ -4184,7 +4184,8 @@ static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
default: llvm_unreachable("Unknown shuffle opcode!");
case OP_VREV:
// VREV divides the vector in half and swaps within the half.
if (VT.getVectorElementType() == MVT::i32)
if (VT.getVectorElementType() == MVT::i32 ||
VT.getVectorElementType() == MVT::f32)
return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
// vrev <4 x i16> -> VREV32
if (VT.getVectorElementType() == MVT::i16)

15
test/CodeGen/ARM/vrev.ll
View File

@ -163,3 +163,18 @@ entry:
store <2 x i16> %tmp11, <2 x i16>* %dst, align 4
ret void
}
; Test vrev of float4
define void @float_vrev64(float* nocapture %source, <4 x float>* nocapture %dest) nounwind noinline ssp {
; CHECK: float_vrev64
; CHECK: vext.32
; CHECK: vrev64.32
entry:
%0 = bitcast float* %source to <4 x float>*
%tmp2 = load <4 x float>* %0, align 4
%tmp5 = shufflevector <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <4 x float> %tmp2, <4 x i32> <i32 0, i32 7, i32 0, i32 0>
%arrayidx8 = getelementptr inbounds <4 x float>* %dest, i32 11
store <4 x float> %tmp5, <4 x float>* %arrayidx8, align 4
ret void
}