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[SystemZ] Ensure -mno-vx disables any use of vector features

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When passing the -vector feature to LLVM (or equivalently the
-mno-vx command line argument to clang), the intent is that
generated code must not use any vector features (in particular,
no vector registers must be used).

However, there are some cases where we still could generate
such uses; these are all related to some of the additional
vector features (like +vector-enhancements-1).  Since none
of those features are actually usable with -vector, just make
sure we disable them all if -vector is given.
This commit is contained in:
Ulrich Weigand 2020-07-23 15:31:15 +02:00
parent 9ecafd1d42
commit 683cc0a5b0
2 changed files with 41 additions and 0 deletions
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8
lib/Target/SystemZ/SystemZSubtarget.cpp
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@ -39,6 +39,14 @@ SystemZSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
if (HasSoftFloat)
HasVector = false;
// -mno-vx implicitly disables all vector-related features.
if (!HasVector) {
HasVectorEnhancements1 = false;
HasVectorEnhancements2 = false;
HasVectorPackedDecimal = false;
HasVectorPackedDecimalEnhancement = false;
}
return *this;
}

33
test/CodeGen/SystemZ/no-vx.ll Normal file
View File

@ -0,0 +1,33 @@
; RUN: llc < %s -mtriple=s390x-linux-gnu -o - | FileCheck %s
; This test verifies that passing the "-vector" feature disables *any*
; use of vector instructions, even if +vector-enhancements-1 if given.
; Function Attrs: noinline nounwind optnone
define dso_local signext i32 @foo(fp128* %0, fp128* %1) #0 {
; CHECK-LABEL: @foo
; CHECK-NOT: vl
; CHECK-NOT: vst
; CHECK: br %r14
entry:
%arg1.addr = alloca fp128, align 8
%arg2.addr = alloca fp128, align 8
%indirect-arg-temp = alloca fp128, align 8
%indirect-arg-temp1 = alloca fp128, align 8
%arg1 = load fp128, fp128* %0, align 8
%arg2 = load fp128, fp128* %1, align 8
store fp128 %arg1, fp128* %arg1.addr, align 8
store fp128 %arg2, fp128* %arg2.addr, align 8
%2 = load fp128, fp128* %arg1.addr, align 8
%3 = load fp128, fp128* %arg2.addr, align 8
store fp128 %2, fp128* %indirect-arg-temp, align 8
store fp128 %3, fp128* %indirect-arg-temp1, align 8
%call = call signext i32 @bar(i32 signext 2, fp128* %indirect-arg-temp, fp128* %indirect-arg-temp1)
ret i32 %call
}
declare dso_local signext i32 @bar(i32 signext, fp128*, fp128*) #1
attributes #0 = { noinline nounwind optnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="z14" "target-features"="+transactional-execution,+vector-enhancements-1,-vector" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="z14" "target-features"="+transactional-execution,+vector-enhancements-1,-vector" "unsafe-fp-math"="false" "use-soft-float"="false" }