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[Hexagon] Avoid infinite loops in type legalization when lowering SETCC

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Only widen SETCC if the operands can be widened. Not checking that caused
infinite widen-split loops in legalization.
This commit is contained in:
Krzysztof Parzyszek 2021-04-15 13:28:09 -05:00
parent 3583af245c
commit 685c4cfa64
2 changed files with 22 additions and 0 deletions
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2
lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
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@ -1954,6 +1954,8 @@ HexagonTargetLowering::WidenHvxSetCC(SDValue Op, SelectionDAG &DAG) const {
unsigned WideOpLen = (8 * HwLen) / ElemTy.getSizeInBits();
assert(WideOpLen * ElemTy.getSizeInBits() == 8 * HwLen);
MVT WideOpTy = MVT::getVectorVT(ElemTy, WideOpLen);
if (!Subtarget.isHVXVectorType(WideOpTy, true))
return SDValue();
SDValue WideOp0 = appendUndef(Op0, WideOpTy, DAG);
SDValue WideOp1 = appendUndef(Op1, WideOpTy, DAG);

20
test/CodeGen/Hexagon/isel-setcc-legalize-loop.ll Normal file
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@ -0,0 +1,20 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; Check that we scalarize the comparison. This testcase used to loop forever
; due to the repeated split-widen operations in legalizing SETCC.
; CHECK: fred:
; CHECK: sfcmp.gt
; CHECK: vinsert
define <32 x i32> @fred(<32 x i32> %a0, <32 x i32> %a1) #0 {
b0:
%v0 = bitcast <32 x i32> %a0 to <32 x float>
%v1 = bitcast <32 x i32> %a1 to <32 x float>
%v2 = fcmp ogt <32 x float> %v0, %v1
%v3 = select <32 x i1> %v2, <32 x float> zeroinitializer, <32 x float> %v0
%v4 = bitcast <32 x float> %v3 to <32 x i32>
ret <32 x i32> %v4
}
attributes #0 = { nounwind "target-cpu"="hexagonv66" "target-features"="+hvxv66,+hvx-length128b" }