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Fix for PR18921, "vmov" part.
Added support for bytes replication feature, so it could be GAS compatible.
E.g. instructions below:
"vmov.i32 d0, 0xffffffff"
"vmvn.i32 d0, 0xabababab"
"vmov.i32 d0, 0xabababab"
"vmov.i16 d0, 0xabab"
are incorrect, but we could deal with such cases.
For first one we should emit:
"vmov.i8 d0, 0xff"
For second one ("vmvn"):
"vmov.i8 d0, 0x54"
For last two instructions it should emit:
"vmov.i8 d0, 0xab"
P.S.: In ARMAsmParser.cpp I have also fixed few nearby style issues in old code.
Just for keeping method bodies in harmony with themselves.
llvm-svn: 207080
This commit is contained in:
Stepan Dyatkovskiy
parent
30919c406c
commit
686d334b05
@ -39,6 +39,49 @@ def nImmVMOVI32 : Operand<i32> {
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let PrintMethod = "printNEONModImmOperand";
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let ParserMatchClass = nImmVMOVI32AsmOperand;
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}
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def nImmVMOVI16AsmOperandByteReplicate :
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AsmOperandClass {
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let Name = "NEONi16vmovByteReplicate";
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let PredicateMethod = "isNEONi16ByteReplicate";
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let RenderMethod = "addNEONvmovByteReplicateOperands";
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}
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def nImmVMOVI32AsmOperandByteReplicate :
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AsmOperandClass {
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let Name = "NEONi32vmovByteReplicate";
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let PredicateMethod = "isNEONi32ByteReplicate";
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let RenderMethod = "addNEONvmovByteReplicateOperands";
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}
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def nImmVMVNI16AsmOperandByteReplicate :
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AsmOperandClass {
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let Name = "NEONi16invByteReplicate";
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let PredicateMethod = "isNEONi16ByteReplicate";
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let RenderMethod = "addNEONinvByteReplicateOperands";
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}
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def nImmVMVNI32AsmOperandByteReplicate :
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AsmOperandClass {
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let Name = "NEONi32invByteReplicate";
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let PredicateMethod = "isNEONi32ByteReplicate";
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let RenderMethod = "addNEONinvByteReplicateOperands";
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}
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def nImmVMOVI16ByteReplicate : Operand<i32> {
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let PrintMethod = "printNEONModImmOperand";
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let ParserMatchClass = nImmVMOVI16AsmOperandByteReplicate;
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}
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def nImmVMOVI32ByteReplicate : Operand<i32> {
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let PrintMethod = "printNEONModImmOperand";
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let ParserMatchClass = nImmVMOVI32AsmOperandByteReplicate;
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}
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def nImmVMVNI16ByteReplicate : Operand<i32> {
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let PrintMethod = "printNEONModImmOperand";
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let ParserMatchClass = nImmVMVNI16AsmOperandByteReplicate;
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}
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def nImmVMVNI32ByteReplicate : Operand<i32> {
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let PrintMethod = "printNEONModImmOperand";
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let ParserMatchClass = nImmVMVNI32AsmOperandByteReplicate;
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}
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def nImmVMOVI32NegAsmOperand : AsmOperandClass { let Name = "NEONi32vmovNeg"; }
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def nImmVMOVI32Neg : Operand<i32> {
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let PrintMethod = "printNEONModImmOperand";
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@ -5301,6 +5344,35 @@ def VMOVv4f32 : N1ModImm<1, 0b000, 0b1111, 0, 1, 0, 1, (outs QPR:$Vd),
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[(set QPR:$Vd, (v4f32 (NEONvmovFPImm timm:$SIMM)))]>;
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} // isReMaterializable
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// Add support for bytes replication feature, so it could be GAS compatible.
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// E.g. instructions below:
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// "vmov.i32 d0, 0xffffffff"
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// "vmov.i32 d0, 0xabababab"
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// "vmov.i16 d0, 0xabab"
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// are incorrect, but we could deal with such cases.
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// For last two instructions, for example, it should emit:
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// "vmov.i8 d0, 0xab"
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def : NEONInstAlias<"vmov${p}.i16 $Vd, $Vm",
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(VMOVv8i8 DPR:$Vd, nImmVMOVI16ByteReplicate:$Vm, pred:$p)>;
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def : NEONInstAlias<"vmov${p}.i32 $Vd, $Vm",
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(VMOVv8i8 DPR:$Vd, nImmVMOVI32ByteReplicate:$Vm, pred:$p)>;
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def : NEONInstAlias<"vmov${p}.i16 $Vd, $Vm",
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(VMOVv16i8 QPR:$Vd, nImmVMOVI16ByteReplicate:$Vm, pred:$p)>;
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def : NEONInstAlias<"vmov${p}.i32 $Vd, $Vm",
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(VMOVv16i8 QPR:$Vd, nImmVMOVI32ByteReplicate:$Vm, pred:$p)>;
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// Also add same support for VMVN instructions. So instruction:
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// "vmvn.i32 d0, 0xabababab"
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// actually means:
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// "vmov.i8 d0, 0x54"
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def : NEONInstAlias<"vmvn${p}.i16 $Vd, $Vm",
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(VMOVv8i8 DPR:$Vd, nImmVMVNI16ByteReplicate:$Vm, pred:$p)>;
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def : NEONInstAlias<"vmvn${p}.i32 $Vd, $Vm",
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(VMOVv8i8 DPR:$Vd, nImmVMVNI32ByteReplicate:$Vm, pred:$p)>;
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def : NEONInstAlias<"vmvn${p}.i16 $Vd, $Vm",
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(VMOVv16i8 QPR:$Vd, nImmVMVNI16ByteReplicate:$Vm, pred:$p)>;
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def : NEONInstAlias<"vmvn${p}.i32 $Vd, $Vm",
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(VMOVv16i8 QPR:$Vd, nImmVMVNI32ByteReplicate:$Vm, pred:$p)>;
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// On some CPUs the two instructions "vmov.i32 dD, #0" and "vmov.i32 qD, #0"
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// require zero cycles to execute so they should be used wherever possible for
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@ -1610,7 +1610,10 @@ public:
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}
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bool isNEONi16splat() const {
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if (!isImm()) return false;
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if (isNEONByteReplicate(2))
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return false; // Leave that for bytes replication and forbid by default.
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if (!isImm())
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return false;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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// Must be a constant.
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if (!CE) return false;
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@ -1620,7 +1623,10 @@ public:
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}
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bool isNEONi32splat() const {
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if (!isImm()) return false;
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if (isNEONByteReplicate(4))
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return false; // Leave that for bytes replication and forbid by default.
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if (!isImm())
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return false;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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// Must be a constant.
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if (!CE) return false;
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@ -1632,11 +1638,36 @@ public:
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(Value >= 0x01000000 && Value <= 0xff000000);
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}
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bool isNEONi32vmov() const {
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if (!isImm()) return false;
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bool isNEONByteReplicate(unsigned NumBytes) const {
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if (!isImm())
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return false;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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// Must be a constant.
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if (!CE) return false;
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if (!CE)
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return false;
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int64_t Value = CE->getValue();
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if (!Value)
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return false; // Don't bother with zero.
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unsigned char B = Value & 0xff;
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for (unsigned i = 1; i < NumBytes; ++i) {
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Value >>= 8;
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if ((Value & 0xff) != B)
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return false;
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}
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return true;
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}
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bool isNEONi16ByteReplicate() const { return isNEONByteReplicate(2); }
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bool isNEONi32ByteReplicate() const { return isNEONByteReplicate(4); }
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bool isNEONi32vmov() const {
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if (isNEONByteReplicate(4))
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return false; // Let it to be classified as byte-replicate case.
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if (!isImm())
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return false;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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// Must be a constant.
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if (!CE)
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return false;
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int64_t Value = CE->getValue();
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// i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
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// for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
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@ -2384,6 +2415,19 @@ public:
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Inst.addOperand(MCOperand::CreateImm(Value));
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}
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void addNEONinvByteReplicateOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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// The immediate encodes the type of constant as well as the value.
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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unsigned Value = CE->getValue();
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assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
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Inst.getOpcode() == ARM::VMOVv16i8) &&
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"All vmvn instructions that wants to replicate non-zero byte "
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"always must be replaced with VMOVv8i8 or VMOVv16i8.");
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unsigned B = ((~Value) & 0xff);
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B |= 0xe00; // cmode = 0b1110
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Inst.addOperand(MCOperand::CreateImm(B));
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}
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void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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// The immediate encodes the type of constant as well as the value.
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@ -2398,6 +2442,19 @@ public:
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Inst.addOperand(MCOperand::CreateImm(Value));
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}
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void addNEONvmovByteReplicateOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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// The immediate encodes the type of constant as well as the value.
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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unsigned Value = CE->getValue();
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assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
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Inst.getOpcode() == ARM::VMOVv16i8) &&
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"All instructions that wants to replicate non-zero byte "
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"always must be replaced with VMOVv8i8 or VMOVv16i8.");
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unsigned B = Value & 0xff;
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B |= 0xe00; // cmode = 0b1110
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Inst.addOperand(MCOperand::CreateImm(B));
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}
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void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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// The immediate encodes the type of constant as well as the value.
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31
test/MC/ARM/vmov-vmvn-byte-replicate.s
Normal file
31
test/MC/ARM/vmov-vmvn-byte-replicate.s
Normal file
@ -0,0 +1,31 @@
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@ PR18921, "vmov" part.
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@ RUN: llvm-mc -triple=armv7-linux-gnueabi -show-encoding < %s | FileCheck %s
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.text
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@ CHECK: vmov.i8 d2, #0xff @ encoding: [0x1f,0x2e,0x87,0xf3]
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@ CHECK: vmov.i8 q2, #0xff @ encoding: [0x5f,0x4e,0x87,0xf3]
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@ CHECK: vmov.i8 d2, #0xab @ encoding: [0x1b,0x2e,0x82,0xf3]
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@ CHECK: vmov.i8 q2, #0xab @ encoding: [0x5b,0x4e,0x82,0xf3]
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@ CHECK: vmov.i8 q2, #0xab @ encoding: [0x5b,0x4e,0x82,0xf3]
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@ CHECK: vmov.i8 q2, #0xab @ encoding: [0x5b,0x4e,0x82,0xf3]
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@ CHECK: vmov.i8 d2, #0x0 @ encoding: [0x10,0x2e,0x80,0xf2]
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@ CHECK: vmov.i8 q2, #0x0 @ encoding: [0x50,0x4e,0x80,0xf2]
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@ CHECK: vmov.i8 d2, #0x54 @ encoding: [0x14,0x2e,0x85,0xf2]
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@ CHECK: vmov.i8 q2, #0x54 @ encoding: [0x54,0x4e,0x85,0xf2]
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@ CHECK: vmov.i8 d2, #0x54 @ encoding: [0x14,0x2e,0x85,0xf2]
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@ CHECK: vmov.i8 q2, #0x54 @ encoding: [0x54,0x4e,0x85,0xf2]
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vmov.i32 d2, #0xffffffff
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vmov.i32 q2, #0xffffffff
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vmov.i32 d2, #0xabababab
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vmov.i32 q2, #0xabababab
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vmov.i16 q2, #0xabab
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vmov.i16 q2, #0xabab
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vmvn.i32 d2, #0xffffffff
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vmvn.i32 q2, #0xffffffff
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vmvn.i32 d2, #0xabababab
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vmvn.i32 q2, #0xabababab
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vmvn.i16 d2, #0xabab
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vmvn.i16 q2, #0xabab
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30
test/MC/ARM/vmov-vmvn-illegal-cases.s
Normal file
30
test/MC/ARM/vmov-vmvn-illegal-cases.s
Normal file
@ -0,0 +1,30 @@
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@ RUN: not llvm-mc -triple=armv7-linux-gnueabi %s 2>&1 | FileCheck %s
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.text
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@ CHECK: error: invalid operand for instruction
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@ CHECK: vmov.i32 d2, #0xffffffab
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@ CHECK: error: invalid operand for instruction
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@ CHECK: vmov.i32 q2, #0xffffffab
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@ CHECK: error: invalid operand for instruction
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@ CHECK: vmov.i16 q2, #0xffab
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@ CHECK: error: invalid operand for instruction
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@ CHECK: vmov.i16 q2, #0xffab
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@ CHECK: error: invalid operand for instruction
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@ CHECK: vmvn.i32 d2, #0xffffffab
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@ CHECK: error: invalid operand for instruction
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@ CHECK: vmvn.i32 q2, #0xffffffab
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@ CHECK: error: invalid operand for instruction
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@ CHECK: vmvn.i16 q2, #0xffab
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@ CHECK: error: invalid operand for instruction
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@ CHECK: vmvn.i16 q2, #0xffab
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vmov.i32 d2, #0xffffffab
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vmov.i32 q2, #0xffffffab
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vmov.i16 q2, #0xffab
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vmov.i16 q2, #0xffab
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vmvn.i32 d2, #0xffffffab
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vmvn.i32 q2, #0xffffffab
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vmvn.i16 q2, #0xffab
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vmvn.i16 q2, #0xffab
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42
test/MC/ARM/vorr-vbic-illegal-cases.s
Normal file
42
test/MC/ARM/vorr-vbic-illegal-cases.s
Normal file
@ -0,0 +1,42 @@
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@ RUN: not llvm-mc -triple=armv7-linux-gnueabi %s 2>&1 | FileCheck %s
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.text
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@ CHECK: error: invalid operand for instruction
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@ CHECK: vorr.i32 d2, #0xffffffff
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@ CHECK: error: invalid operand for instruction
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@ CHECK: vorr.i32 q2, #0xffffffff
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@ CHECK: error: invalid operand for instruction
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@ CHECK: vorr.i32 d2, #0xabababab
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@ CHECK: error: invalid operand for instruction
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@ CHECK: vorr.i32 q2, #0xabababab
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@ CHECK: error: invalid operand for instruction
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@ CHECK: vorr.i16 q2, #0xabab
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@ CHECK: error: invalid operand for instruction
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@ CHECK: vorr.i16 q2, #0xabab
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@ CHECK: error: invalid operand for instruction
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@ CHECK: vbic.i32 d2, #0xffffffff
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@ CHECK: error: invalid operand for instruction
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@ CHECK: vbic.i32 q2, #0xffffffff
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@ CHECK: error: invalid operand for instruction
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@ CHECK: vbic.i32 d2, #0xabababab
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@ CHECK: error: invalid operand for instruction
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@ CHECK: vbic.i32 q2, #0xabababab
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@ CHECK: error: invalid operand for instruction
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@ CHECK: vbic.i16 d2, #0xabab
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@ CHECK: error: invalid operand for instruction
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@ CHECK: vbic.i16 q2, #0xabab
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vorr.i32 d2, #0xffffffff
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vorr.i32 q2, #0xffffffff
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vorr.i32 d2, #0xabababab
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vorr.i32 q2, #0xabababab
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vorr.i16 q2, #0xabab
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vorr.i16 q2, #0xabab
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vbic.i32 d2, #0xffffffff
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vbic.i32 q2, #0xffffffff
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vbic.i32 d2, #0xabababab
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vbic.i32 q2, #0xabababab
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vbic.i16 d2, #0xabab
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vbic.i16 q2, #0xabab
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