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- add tokens to PPCInstrInfo.td and PPCInstr64Bit.td to resolve
"Instruction 'foo' has no tokens" errors during llvm-tblgen -gen-asm-matcher attempts. At this time, the added tokens are "#comment" style rather than the actual mnemonic. This will be revisited once the rest of the base asmparser bits get straightened out for ppc64-elf-linux. llvm-svn: 165237
This commit is contained in:
Will Schmidt
parent
f49beef26f
commit
686f66629c
@ -63,7 +63,7 @@ def HI48_64 : SDNodeXForm<imm, [{
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//
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let Defs = [LR8] in
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def MovePCtoLR8 : Pseudo<(outs), (ins), "", []>,
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def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>,
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PPC970_Unit_BRU;
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// Darwin ABI Calls.
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@ -141,31 +141,31 @@ def : Pat<(PPCnop),
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let usesCustomInserter = 1 in {
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let Defs = [CR0] in {
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def ATOMIC_LOAD_ADD_I64 : Pseudo<
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(outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "",
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(outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_ADD_I64",
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[(set G8RC:$dst, (atomic_load_add_64 xoaddr:$ptr, G8RC:$incr))]>;
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def ATOMIC_LOAD_SUB_I64 : Pseudo<
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(outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "",
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(outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_SUB_I64",
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[(set G8RC:$dst, (atomic_load_sub_64 xoaddr:$ptr, G8RC:$incr))]>;
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def ATOMIC_LOAD_OR_I64 : Pseudo<
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(outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "",
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(outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_OR_I64",
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[(set G8RC:$dst, (atomic_load_or_64 xoaddr:$ptr, G8RC:$incr))]>;
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def ATOMIC_LOAD_XOR_I64 : Pseudo<
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(outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "",
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(outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_XOR_I64",
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[(set G8RC:$dst, (atomic_load_xor_64 xoaddr:$ptr, G8RC:$incr))]>;
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def ATOMIC_LOAD_AND_I64 : Pseudo<
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(outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "",
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(outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_AND_i64",
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[(set G8RC:$dst, (atomic_load_and_64 xoaddr:$ptr, G8RC:$incr))]>;
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def ATOMIC_LOAD_NAND_I64 : Pseudo<
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(outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "",
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(outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_NAND_I64",
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[(set G8RC:$dst, (atomic_load_nand_64 xoaddr:$ptr, G8RC:$incr))]>;
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def ATOMIC_CMP_SWAP_I64 : Pseudo<
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(outs G8RC:$dst), (ins memrr:$ptr, G8RC:$old, G8RC:$new), "",
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(outs G8RC:$dst), (ins memrr:$ptr, G8RC:$old, G8RC:$new), "#ATOMIC_CMP_SWAP_I64",
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[(set G8RC:$dst,
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(atomic_cmp_swap_64 xoaddr:$ptr, G8RC:$old, G8RC:$new))]>;
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def ATOMIC_SWAP_I64 : Pseudo<
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(outs G8RC:$dst), (ins memrr:$ptr, G8RC:$new), "",
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(outs G8RC:$dst), (ins memrr:$ptr, G8RC:$new), "#ATOMIC_SWAP_I64",
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[(set G8RC:$dst, (atomic_swap_64 xoaddr:$ptr, G8RC:$new))]>;
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}
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}
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@ -247,7 +247,7 @@ def MTCRF8 : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins G8RC:$rS),
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PPC970_MicroCode, PPC970_Unit_CRU;
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def MFCR8pseud: XFXForm_3<31, 19, (outs G8RC:$rT), (ins crbitm:$FXM),
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"", SprMFCR>,
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"#MFCR8pseud", SprMFCR>,
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PPC970_MicroCode, PPC970_Unit_CRU;
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def MFCR8 : XFXForm_3<31, 19, (outs G8RC:$rT), (ins),
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@ -278,7 +278,7 @@ def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs G8RC:$rT), (ins),
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// the POWER3.
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let Defs = [X1], Uses = [X1] in
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def DYNALLOC8 : Pseudo<(outs G8RC:$result), (ins G8RC:$negsize, memri:$fpsi),"",
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def DYNALLOC8 : Pseudo<(outs G8RC:$result), (ins G8RC:$negsize, memri:$fpsi),"#DYNALLOC8",
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[(set G8RC:$result,
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(PPCdynalloc G8RC:$negsize, iaddr:$fpsi))]>;
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@ -626,15 +626,15 @@ def LD : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrix:$src),
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"ld $rD, $src", LdStLD,
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[(set G8RC:$rD, (load ixaddr:$src))]>, isPPC64;
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def LDtoc: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
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"",
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"#LDtoc",
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[(set G8RC:$rD,
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(PPCtoc_entry tglobaladdr:$disp, G8RC:$reg))]>, isPPC64;
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def LDtocJTI: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
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"",
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"#LDtocJTI",
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[(set G8RC:$rD,
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(PPCtoc_entry tjumptable:$disp, G8RC:$reg))]>, isPPC64;
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def LDtocCPT: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
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"",
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"#LDtocCPT",
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[(set G8RC:$rD,
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(PPCtoc_entry tconstpool:$disp, G8RC:$reg))]>, isPPC64;
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@ -369,9 +369,9 @@ def IsBookE : Predicate<"PPCSubTarget.isBookE()">;
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let hasCtrlDep = 1 in {
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let Defs = [R1], Uses = [R1] in {
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def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "",
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def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
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[(callseq_start timm:$amt)]>;
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def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "",
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def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
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[(callseq_end timm:$amt1, timm:$amt2)]>;
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}
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@ -380,7 +380,7 @@ def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS),
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}
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let Defs = [R1], Uses = [R1] in
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def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi), "",
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def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi), "#DYNALLOC",
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[(set GPRC:$result,
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(PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>;
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@ -389,19 +389,19 @@ def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi), "",
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let usesCustomInserter = 1, // Expanded after instruction selection.
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PPC970_Single = 1 in {
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def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F,
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i32imm:$BROPC), "",
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i32imm:$BROPC), "#SELECT_CC_I4",
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[]>;
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def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F,
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i32imm:$BROPC), "",
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i32imm:$BROPC), "#SELECT_CC_I8",
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[]>;
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def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F,
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i32imm:$BROPC), "",
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i32imm:$BROPC), "#SELECT_CC_F4",
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[]>;
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def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F,
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i32imm:$BROPC), "",
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i32imm:$BROPC), "#SELECT_CC_F8",
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[]>;
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def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F,
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i32imm:$BROPC), "",
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i32imm:$BROPC), "#SELECT_CC_VRRC",
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[]>;
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}
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@ -409,13 +409,13 @@ let usesCustomInserter = 1, // Expanded after instruction selection.
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// scavenge a register for it.
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let mayStore = 1 in
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def SPILL_CR : Pseudo<(outs), (ins CRRC:$cond, memri:$F),
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"", []>;
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"#SPILL_CR", []>;
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// RESTORE_CR - Indicate that we're restoring the CR register (previously
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// spilled), so we'll need to scavenge a register for it.
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let mayLoad = 1 in
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def RESTORE_CR : Pseudo<(outs CRRC:$cond), (ins memri:$F),
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"", []>;
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"#RESTORE_CR", []>;
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let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
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let isReturn = 1, Uses = [LR, RM] in
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@ -427,7 +427,7 @@ let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
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}
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let Defs = [LR] in
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def MovePCtoLR : Pseudo<(outs), (ins), "", []>,
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def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,
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PPC970_Unit_BRU;
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let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
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@ -564,81 +564,81 @@ def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
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let usesCustomInserter = 1 in {
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let Defs = [CR0] in {
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def ATOMIC_LOAD_ADD_I8 : Pseudo<
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I8",
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[(set GPRC:$dst, (atomic_load_add_8 xoaddr:$ptr, GPRC:$incr))]>;
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def ATOMIC_LOAD_SUB_I8 : Pseudo<
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I8",
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[(set GPRC:$dst, (atomic_load_sub_8 xoaddr:$ptr, GPRC:$incr))]>;
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def ATOMIC_LOAD_AND_I8 : Pseudo<
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I8",
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[(set GPRC:$dst, (atomic_load_and_8 xoaddr:$ptr, GPRC:$incr))]>;
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def ATOMIC_LOAD_OR_I8 : Pseudo<
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I8",
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[(set GPRC:$dst, (atomic_load_or_8 xoaddr:$ptr, GPRC:$incr))]>;
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def ATOMIC_LOAD_XOR_I8 : Pseudo<
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "ATOMIC_LOAD_XOR_I8",
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[(set GPRC:$dst, (atomic_load_xor_8 xoaddr:$ptr, GPRC:$incr))]>;
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def ATOMIC_LOAD_NAND_I8 : Pseudo<
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I8",
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[(set GPRC:$dst, (atomic_load_nand_8 xoaddr:$ptr, GPRC:$incr))]>;
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def ATOMIC_LOAD_ADD_I16 : Pseudo<
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I16",
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[(set GPRC:$dst, (atomic_load_add_16 xoaddr:$ptr, GPRC:$incr))]>;
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def ATOMIC_LOAD_SUB_I16 : Pseudo<
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I16",
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[(set GPRC:$dst, (atomic_load_sub_16 xoaddr:$ptr, GPRC:$incr))]>;
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def ATOMIC_LOAD_AND_I16 : Pseudo<
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I16",
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[(set GPRC:$dst, (atomic_load_and_16 xoaddr:$ptr, GPRC:$incr))]>;
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def ATOMIC_LOAD_OR_I16 : Pseudo<
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I16",
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[(set GPRC:$dst, (atomic_load_or_16 xoaddr:$ptr, GPRC:$incr))]>;
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def ATOMIC_LOAD_XOR_I16 : Pseudo<
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_XOR_I16",
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[(set GPRC:$dst, (atomic_load_xor_16 xoaddr:$ptr, GPRC:$incr))]>;
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def ATOMIC_LOAD_NAND_I16 : Pseudo<
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I16",
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[(set GPRC:$dst, (atomic_load_nand_16 xoaddr:$ptr, GPRC:$incr))]>;
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def ATOMIC_LOAD_ADD_I32 : Pseudo<
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_ADD_I32",
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[(set GPRC:$dst, (atomic_load_add_32 xoaddr:$ptr, GPRC:$incr))]>;
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def ATOMIC_LOAD_SUB_I32 : Pseudo<
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_SUB_I32",
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[(set GPRC:$dst, (atomic_load_sub_32 xoaddr:$ptr, GPRC:$incr))]>;
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def ATOMIC_LOAD_AND_I32 : Pseudo<
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_AND_I32",
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[(set GPRC:$dst, (atomic_load_and_32 xoaddr:$ptr, GPRC:$incr))]>;
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def ATOMIC_LOAD_OR_I32 : Pseudo<
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_OR_I32",
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[(set GPRC:$dst, (atomic_load_or_32 xoaddr:$ptr, GPRC:$incr))]>;
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def ATOMIC_LOAD_XOR_I32 : Pseudo<
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_XOR_I32",
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[(set GPRC:$dst, (atomic_load_xor_32 xoaddr:$ptr, GPRC:$incr))]>;
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def ATOMIC_LOAD_NAND_I32 : Pseudo<
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "#ATOMIC_LOAD_NAND_I32",
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[(set GPRC:$dst, (atomic_load_nand_32 xoaddr:$ptr, GPRC:$incr))]>;
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def ATOMIC_CMP_SWAP_I8 : Pseudo<
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "",
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I8",
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[(set GPRC:$dst,
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(atomic_cmp_swap_8 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
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def ATOMIC_CMP_SWAP_I16 : Pseudo<
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "",
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new",
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[(set GPRC:$dst,
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(atomic_cmp_swap_16 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
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def ATOMIC_CMP_SWAP_I32 : Pseudo<
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "",
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$old, GPRC:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new",
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[(set GPRC:$dst,
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(atomic_cmp_swap_32 xoaddr:$ptr, GPRC:$old, GPRC:$new))]>;
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def ATOMIC_SWAP_I8 : Pseudo<
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "",
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_i8",
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[(set GPRC:$dst, (atomic_swap_8 xoaddr:$ptr, GPRC:$new))]>;
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def ATOMIC_SWAP_I16 : Pseudo<
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "",
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_I16",
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[(set GPRC:$dst, (atomic_swap_16 xoaddr:$ptr, GPRC:$new))]>;
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def ATOMIC_SWAP_I32 : Pseudo<
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "",
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(outs GPRC:$dst), (ins memrr:$ptr, GPRC:$new), "#ATOMIC_SWAP_I32",
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[(set GPRC:$dst, (atomic_swap_32 xoaddr:$ptr, GPRC:$new))]>;
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}
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}
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@ -1207,7 +1207,7 @@ def MTCRF : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins GPRC:$rS),
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//
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// FIXME: Make this a real Pseudo instruction when the JIT switches to MC.
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def MFCRpseud: XFXForm_3<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
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"", SprMFCR>,
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"#MFCRpseud", SprMFCR>,
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PPC970_MicroCode, PPC970_Unit_CRU;
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def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins),
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