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[TargetParser] Add missing armv8l ARMv8 variant.

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This change adds the missing armv8l variant as an alias of armv8 architecture.
The issue was observed with several regressions in validation on armv8l
hardware (for instance ExecutionEngine/frem.ll failed due to lack of neon fpu).

Tested with regression testsuite passed without regression on ARM and x86_64.

Patch by Yvan Roux.

Reviewers: rengolin, rogfer01, olista01, fhahn

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D41859

llvm-svn: 322098
This commit is contained in:
Florian Hahn 2018-01-09 17:49:25 +00:00
parent 637037fa50
commit 687480985c
2 changed files with 19 additions and 18 deletions
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2
lib/Support/TargetParser.cpp
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@ -581,7 +581,7 @@ static StringRef getArchSynonym(StringRef Arch) {
.Case("v7r", "v7-r")
.Case("v7m", "v7-m")
.Case("v7em", "v7e-m")
.Cases("v8", "v8a", "aarch64", "arm64", "v8-a")
.Cases("v8", "v8a", "v8l", "aarch64", "arm64", "v8-a")
.Case("v8.1a", "v8.1-a")
.Case("v8.2a", "v8.2-a")
.Case("v8.3a", "v8.3-a")

35
unittests/Support/TargetParserTest.cpp
View File

@ -17,17 +17,18 @@ using namespace llvm;
namespace {
const char *ARMArch[] = {
"armv2", "armv2a", "armv3", "armv3m", "armv4",
"armv4t", "armv5", "armv5t", "armv5e", "armv5te",
"armv5tej", "armv6", "armv6j", "armv6k", "armv6hl",
"armv6t2", "armv6kz", "armv6z", "armv6zk", "armv6-m",
"armv6m", "armv6sm", "armv6s-m", "armv7-a", "armv7",
"armv7a", "armv7ve", "armv7hl", "armv7l", "armv7-r",
"armv7r", "armv7-m", "armv7m", "armv7k", "armv7s",
"armv7e-m", "armv7em", "armv8-a", "armv8", "armv8a",
"armv8.1-a", "armv8.1a", "armv8.2-a", "armv8.2a", "armv8.3-a",
"armv8.3a", "armv8-r", "armv8r", "armv8-m.base", "armv8m.base",
"armv8-m.main", "armv8m.main", "iwmmxt", "iwmmxt2", "xscale"};
"armv2", "armv2a", "armv3", "armv3m", "armv4",
"armv4t", "armv5", "armv5t", "armv5e", "armv5te",
"armv5tej", "armv6", "armv6j", "armv6k", "armv6hl",
"armv6t2", "armv6kz", "armv6z", "armv6zk", "armv6-m",
"armv6m", "armv6sm", "armv6s-m", "armv7-a", "armv7",
"armv7a", "armv7ve", "armv7hl", "armv7l", "armv7-r",
"armv7r", "armv7-m", "armv7m", "armv7k", "armv7s",
"armv7e-m", "armv7em", "armv8-a", "armv8", "armv8a",
"armv8l", "armv8.1-a", "armv8.1a", "armv8.2-a", "armv8.2a",
"armv8.3-a", "armv8.3a", "armv8-r", "armv8r", "armv8-m.base",
"armv8m.base", "armv8-m.main", "armv8m.main", "iwmmxt", "iwmmxt2",
"xscale"};
bool testARMCPU(StringRef CPUName, StringRef ExpectedArch,
StringRef ExpectedFPU, unsigned ExpectedFlags,
@ -558,12 +559,12 @@ TEST(TargetParserTest, ARMparseHWDiv) {
TEST(TargetParserTest, ARMparseArchEndianAndISA) {
const char *Arch[] = {
"v2", "v2a", "v3", "v3m", "v4", "v4t", "v5", "v5t",
"v5e", "v5te", "v5tej", "v6", "v6j", "v6k", "v6hl", "v6t2",
"v6kz", "v6z", "v6zk", "v6-m", "v6m", "v6sm", "v6s-m", "v7-a",
"v7", "v7a", "v7ve", "v7hl", "v7l", "v7-r", "v7r", "v7-m",
"v7m", "v7k", "v7s", "v7e-m", "v7em", "v8-a", "v8", "v8a",
"v8.1-a", "v8.1a", "v8.2-a", "v8.2a", "v8.3-a", "v8.3a", "v8-r"};
"v2", "v2a", "v3", "v3m", "v4", "v4t", "v5", "v5t",
"v5e", "v5te", "v5tej", "v6", "v6j", "v6k", "v6hl", "v6t2",
"v6kz", "v6z", "v6zk", "v6-m", "v6m", "v6sm", "v6s-m", "v7-a",
"v7", "v7a", "v7ve", "v7hl", "v7l", "v7-r", "v7r", "v7-m",
"v7m", "v7k", "v7s", "v7e-m", "v7em", "v8-a", "v8", "v8a",
"v8l", "v8.1-a", "v8.1a", "v8.2-a", "v8.2a", "v8.3-a", "v8.3a", "v8-r"};
for (unsigned i = 0; i < array_lengthof(Arch); i++) {
std::string arm_1 = "armeb" + (std::string)(Arch[i]);