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ATT asm printer just print register AsmName's instead of calling tolower on each charater of Name. This speeds it up by 10%.
llvm-svn: 53208
This commit is contained in:
Evan Cheng
parent
c8c4503279
commit
688a8070f4
@ -328,8 +328,7 @@ void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
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((strcmp(Modifier+6,"16") == 0) ? MVT::i16 : MVT::i8));
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Reg = getX86SubSuperRegister(Reg, VT);
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}
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for (const char *Name = TRI->getAsmName(Reg); *Name; ++Name)
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O << (char)tolower(*Name);
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O << TRI->getAsmName(Reg);
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return;
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}
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@ -680,9 +679,7 @@ bool X86ATTAsmPrinter::printAsmMRegister(const MachineOperand &MO,
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break;
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}
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O << '%';
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for (const char *Name = TRI->getAsmName(Reg); *Name; ++Name)
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O << (char)tolower(*Name);
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O << '%'<< TRI->getAsmName(Reg);
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return false;
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}
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@ -214,7 +214,7 @@ void X86IntelAsmPrinter::printOp(const MachineOperand &MO,
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((strcmp(Modifier,"subreg16") == 0) ? MVT::i16 :MVT::i8));
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Reg = getX86SubSuperRegister(Reg, VT);
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}
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O << TRI->getAsmName(Reg);
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O << TRI->getName(Reg);
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} else
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O << "reg" << MO.getReg();
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return;
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@ -359,7 +359,7 @@ bool X86IntelAsmPrinter::printAsmMRegister(const MachineOperand &MO,
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break;
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}
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O << '%' << TRI->getAsmName(Reg);
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O << '%' << TRI->getName(Reg);
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return false;
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}
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@ -46,7 +46,7 @@ struct VISIBILITY_HIDDEN X86IntelAsmPrinter : public AsmPrinter {
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if (MO.isRegister()) {
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assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
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"Not physreg??");
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O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
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O << TM.getRegisterInfo()->get(MO.getReg()).Name; // Capitalized names
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} else {
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printOp(MO, Modifier);
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}
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@ -30,144 +30,144 @@ let Namespace = "X86" in {
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// 8-bit registers
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// Low registers
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def AL : Register<"AL">, DwarfRegNum<[0, 0, 0]>;
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def DL : Register<"DL">, DwarfRegNum<[1, 2, 2]>;
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def CL : Register<"CL">, DwarfRegNum<[2, 1, 1]>;
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def BL : Register<"BL">, DwarfRegNum<[3, 3, 3]>;
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def AL : Register<"al">, DwarfRegNum<[0, 0, 0]>;
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def DL : Register<"dl">, DwarfRegNum<[1, 2, 2]>;
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def CL : Register<"cl">, DwarfRegNum<[2, 1, 1]>;
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def BL : Register<"bl">, DwarfRegNum<[3, 3, 3]>;
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// X86-64 only
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def SIL : Register<"SIL">, DwarfRegNum<[4, 6, 6]>;
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def DIL : Register<"DIL">, DwarfRegNum<[5, 7, 7]>;
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def BPL : Register<"BPL">, DwarfRegNum<[6, 4, 5]>;
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def SPL : Register<"SPL">, DwarfRegNum<[7, 5, 4]>;
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def R8B : Register<"R8B">, DwarfRegNum<[8, -2, -2]>;
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def R9B : Register<"R9B">, DwarfRegNum<[9, -2, -2]>;
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def R10B : Register<"R10B">, DwarfRegNum<[10, -2, -2]>;
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def R11B : Register<"R11B">, DwarfRegNum<[11, -2, -2]>;
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def R12B : Register<"R12B">, DwarfRegNum<[12, -2, -2]>;
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def R13B : Register<"R13B">, DwarfRegNum<[13, -2, -2]>;
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def R14B : Register<"R14B">, DwarfRegNum<[14, -2, -2]>;
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def R15B : Register<"R15B">, DwarfRegNum<[15, -2, -2]>;
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def SIL : Register<"sil">, DwarfRegNum<[4, 6, 6]>;
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def DIL : Register<"dil">, DwarfRegNum<[5, 7, 7]>;
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def BPL : Register<"bpl">, DwarfRegNum<[6, 4, 5]>;
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def SPL : Register<"spl">, DwarfRegNum<[7, 5, 4]>;
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def R8B : Register<"r8b">, DwarfRegNum<[8, -2, -2]>;
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def R9B : Register<"r9b">, DwarfRegNum<[9, -2, -2]>;
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def R10B : Register<"r10b">, DwarfRegNum<[10, -2, -2]>;
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def R11B : Register<"r11b">, DwarfRegNum<[11, -2, -2]>;
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def R12B : Register<"r12b">, DwarfRegNum<[12, -2, -2]>;
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def R13B : Register<"r13b">, DwarfRegNum<[13, -2, -2]>;
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def R14B : Register<"r14b">, DwarfRegNum<[14, -2, -2]>;
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def R15B : Register<"r15b">, DwarfRegNum<[15, -2, -2]>;
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// High registers X86-32 only
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def AH : Register<"AH">, DwarfRegNum<[0, 0, 0]>;
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def DH : Register<"DH">, DwarfRegNum<[1, 2, 2]>;
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def CH : Register<"CH">, DwarfRegNum<[2, 1, 1]>;
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def BH : Register<"BH">, DwarfRegNum<[3, 3, 3]>;
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def AH : Register<"ah">, DwarfRegNum<[0, 0, 0]>;
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def DH : Register<"dh">, DwarfRegNum<[1, 2, 2]>;
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def CH : Register<"ch">, DwarfRegNum<[2, 1, 1]>;
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def BH : Register<"bh">, DwarfRegNum<[3, 3, 3]>;
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// 16-bit registers
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def AX : RegisterWithSubRegs<"AX", [AH,AL]>, DwarfRegNum<[0, 0, 0]>;
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def DX : RegisterWithSubRegs<"DX", [DH,DL]>, DwarfRegNum<[1, 2, 2]>;
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def CX : RegisterWithSubRegs<"CX", [CH,CL]>, DwarfRegNum<[2, 1, 1]>;
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def BX : RegisterWithSubRegs<"BX", [BH,BL]>, DwarfRegNum<[3, 3, 3]>;
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def SI : RegisterWithSubRegs<"SI", [SIL]>, DwarfRegNum<[4, 6, 6]>;
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def DI : RegisterWithSubRegs<"DI", [DIL]>, DwarfRegNum<[5, 7, 7]>;
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def BP : RegisterWithSubRegs<"BP", [BPL]>, DwarfRegNum<[6, 4, 5]>;
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def SP : RegisterWithSubRegs<"SP", [SPL]>, DwarfRegNum<[7, 5, 4]>;
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def IP : Register<"IP">, DwarfRegNum<[16]>;
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def AX : RegisterWithSubRegs<"ax", [AH,AL]>, DwarfRegNum<[0, 0, 0]>;
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def DX : RegisterWithSubRegs<"dx", [DH,DL]>, DwarfRegNum<[1, 2, 2]>;
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def CX : RegisterWithSubRegs<"cx", [CH,CL]>, DwarfRegNum<[2, 1, 1]>;
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def BX : RegisterWithSubRegs<"bx", [BH,BL]>, DwarfRegNum<[3, 3, 3]>;
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def SI : RegisterWithSubRegs<"si", [SIL]>, DwarfRegNum<[4, 6, 6]>;
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def DI : RegisterWithSubRegs<"di", [DIL]>, DwarfRegNum<[5, 7, 7]>;
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def BP : RegisterWithSubRegs<"bp", [BPL]>, DwarfRegNum<[6, 4, 5]>;
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def SP : RegisterWithSubRegs<"sp", [SPL]>, DwarfRegNum<[7, 5, 4]>;
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def IP : Register<"ip">, DwarfRegNum<[16]>;
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// X86-64 only
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def R8W : RegisterWithSubRegs<"R8W", [R8B]>, DwarfRegNum<[8, -2, -2]>;
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def R9W : RegisterWithSubRegs<"R9W", [R9B]>, DwarfRegNum<[9, -2, -2]>;
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def R10W : RegisterWithSubRegs<"R10W", [R10B]>, DwarfRegNum<[10, -2, -2]>;
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def R11W : RegisterWithSubRegs<"R11W", [R11B]>, DwarfRegNum<[11, -2, -2]>;
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def R12W : RegisterWithSubRegs<"R12W", [R12B]>, DwarfRegNum<[12, -2, -2]>;
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def R13W : RegisterWithSubRegs<"R13W", [R13B]>, DwarfRegNum<[13, -2, -2]>;
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def R14W : RegisterWithSubRegs<"R14W", [R14B]>, DwarfRegNum<[14, -2, -2]>;
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def R15W : RegisterWithSubRegs<"R15W", [R15B]>, DwarfRegNum<[15, -2, -2]>;
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def R8W : RegisterWithSubRegs<"r8w", [R8B]>, DwarfRegNum<[8, -2, -2]>;
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def R9W : RegisterWithSubRegs<"r9w", [R9B]>, DwarfRegNum<[9, -2, -2]>;
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def R10W : RegisterWithSubRegs<"r10w", [R10B]>, DwarfRegNum<[10, -2, -2]>;
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def R11W : RegisterWithSubRegs<"r11w", [R11B]>, DwarfRegNum<[11, -2, -2]>;
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def R12W : RegisterWithSubRegs<"r12w", [R12B]>, DwarfRegNum<[12, -2, -2]>;
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def R13W : RegisterWithSubRegs<"r13w", [R13B]>, DwarfRegNum<[13, -2, -2]>;
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def R14W : RegisterWithSubRegs<"r14w", [R14B]>, DwarfRegNum<[14, -2, -2]>;
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def R15W : RegisterWithSubRegs<"r15w", [R15B]>, DwarfRegNum<[15, -2, -2]>;
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// 32-bit registers
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def EAX : RegisterWithSubRegs<"EAX", [AX]>, DwarfRegNum<[0, 0, 0]>;
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def EDX : RegisterWithSubRegs<"EDX", [DX]>, DwarfRegNum<[1, 2, 2]>;
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def ECX : RegisterWithSubRegs<"ECX", [CX]>, DwarfRegNum<[2, 1, 1]>;
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def EBX : RegisterWithSubRegs<"EBX", [BX]>, DwarfRegNum<[3, 3, 3]>;
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def ESI : RegisterWithSubRegs<"ESI", [SI]>, DwarfRegNum<[4, 6, 6]>;
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def EDI : RegisterWithSubRegs<"EDI", [DI]>, DwarfRegNum<[5, 7, 7]>;
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def EBP : RegisterWithSubRegs<"EBP", [BP]>, DwarfRegNum<[6, 4, 5]>;
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def ESP : RegisterWithSubRegs<"ESP", [SP]>, DwarfRegNum<[7, 5, 4]>;
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def EIP : RegisterWithSubRegs<"EIP", [IP]>, DwarfRegNum<[16, 8, 8]>;
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def EAX : RegisterWithSubRegs<"eax", [AX]>, DwarfRegNum<[0, 0, 0]>;
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def EDX : RegisterWithSubRegs<"edx", [DX]>, DwarfRegNum<[1, 2, 2]>;
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def ECX : RegisterWithSubRegs<"ecx", [CX]>, DwarfRegNum<[2, 1, 1]>;
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def EBX : RegisterWithSubRegs<"ebx", [BX]>, DwarfRegNum<[3, 3, 3]>;
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def ESI : RegisterWithSubRegs<"esi", [SI]>, DwarfRegNum<[4, 6, 6]>;
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def EDI : RegisterWithSubRegs<"edi", [DI]>, DwarfRegNum<[5, 7, 7]>;
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def EBP : RegisterWithSubRegs<"ebp", [BP]>, DwarfRegNum<[6, 4, 5]>;
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def ESP : RegisterWithSubRegs<"esp", [SP]>, DwarfRegNum<[7, 5, 4]>;
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def EIP : RegisterWithSubRegs<"eip", [IP]>, DwarfRegNum<[16, 8, 8]>;
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// X86-64 only
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def R8D : RegisterWithSubRegs<"R8D", [R8W]>, DwarfRegNum<[8, -2, -2]>;
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def R9D : RegisterWithSubRegs<"R9D", [R9W]>, DwarfRegNum<[9, -2, -2]>;
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def R10D : RegisterWithSubRegs<"R10D", [R10W]>, DwarfRegNum<[10, -2, -2]>;
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def R11D : RegisterWithSubRegs<"R11D", [R11W]>, DwarfRegNum<[11, -2, -2]>;
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def R12D : RegisterWithSubRegs<"R12D", [R12W]>, DwarfRegNum<[12, -2, -2]>;
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def R13D : RegisterWithSubRegs<"R13D", [R13W]>, DwarfRegNum<[13, -2, -2]>;
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def R14D : RegisterWithSubRegs<"R14D", [R14W]>, DwarfRegNum<[14, -2, -2]>;
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def R15D : RegisterWithSubRegs<"R15D", [R15W]>, DwarfRegNum<[15, -2, -2]>;
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def R8D : RegisterWithSubRegs<"r8d", [R8W]>, DwarfRegNum<[8, -2, -2]>;
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def R9D : RegisterWithSubRegs<"r9d", [R9W]>, DwarfRegNum<[9, -2, -2]>;
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def R10D : RegisterWithSubRegs<"r10d", [R10W]>, DwarfRegNum<[10, -2, -2]>;
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def R11D : RegisterWithSubRegs<"r11d", [R11W]>, DwarfRegNum<[11, -2, -2]>;
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def R12D : RegisterWithSubRegs<"r12d", [R12W]>, DwarfRegNum<[12, -2, -2]>;
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def R13D : RegisterWithSubRegs<"r13d", [R13W]>, DwarfRegNum<[13, -2, -2]>;
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def R14D : RegisterWithSubRegs<"r14d", [R14W]>, DwarfRegNum<[14, -2, -2]>;
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def R15D : RegisterWithSubRegs<"r15d", [R15W]>, DwarfRegNum<[15, -2, -2]>;
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// 64-bit registers, X86-64 only
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def RAX : RegisterWithSubRegs<"RAX", [EAX]>, DwarfRegNum<[0, -2, -2]>;
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def RDX : RegisterWithSubRegs<"RDX", [EDX]>, DwarfRegNum<[1, -2, -2]>;
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def RCX : RegisterWithSubRegs<"RCX", [ECX]>, DwarfRegNum<[2, -2, -2]>;
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def RBX : RegisterWithSubRegs<"RBX", [EBX]>, DwarfRegNum<[3, -2, -2]>;
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def RSI : RegisterWithSubRegs<"RSI", [ESI]>, DwarfRegNum<[4, -2, -2]>;
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def RDI : RegisterWithSubRegs<"RDI", [EDI]>, DwarfRegNum<[5, -2, -2]>;
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def RBP : RegisterWithSubRegs<"RBP", [EBP]>, DwarfRegNum<[6, -2, -2]>;
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def RSP : RegisterWithSubRegs<"RSP", [ESP]>, DwarfRegNum<[7, -2, -2]>;
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def RAX : RegisterWithSubRegs<"rax", [EAX]>, DwarfRegNum<[0, -2, -2]>;
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def RDX : RegisterWithSubRegs<"rdx", [EDX]>, DwarfRegNum<[1, -2, -2]>;
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def RCX : RegisterWithSubRegs<"rcx", [ECX]>, DwarfRegNum<[2, -2, -2]>;
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def RBX : RegisterWithSubRegs<"rbx", [EBX]>, DwarfRegNum<[3, -2, -2]>;
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def RSI : RegisterWithSubRegs<"rsi", [ESI]>, DwarfRegNum<[4, -2, -2]>;
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def RDI : RegisterWithSubRegs<"rdi", [EDI]>, DwarfRegNum<[5, -2, -2]>;
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def RBP : RegisterWithSubRegs<"rbp", [EBP]>, DwarfRegNum<[6, -2, -2]>;
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def RSP : RegisterWithSubRegs<"rsp", [ESP]>, DwarfRegNum<[7, -2, -2]>;
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def R8 : RegisterWithSubRegs<"R8", [R8D]>, DwarfRegNum<[8, -2, -2]>;
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def R9 : RegisterWithSubRegs<"R9", [R9D]>, DwarfRegNum<[9, -2, -2]>;
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def R10 : RegisterWithSubRegs<"R10", [R10D]>, DwarfRegNum<[10, -2, -2]>;
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def R11 : RegisterWithSubRegs<"R11", [R11D]>, DwarfRegNum<[11, -2, -2]>;
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def R12 : RegisterWithSubRegs<"R12", [R12D]>, DwarfRegNum<[12, -2, -2]>;
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def R13 : RegisterWithSubRegs<"R13", [R13D]>, DwarfRegNum<[13, -2, -2]>;
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def R14 : RegisterWithSubRegs<"R14", [R14D]>, DwarfRegNum<[14, -2, -2]>;
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def R15 : RegisterWithSubRegs<"R15", [R15D]>, DwarfRegNum<[15, -2, -2]>;
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def RIP : RegisterWithSubRegs<"RIP", [EIP]>, DwarfRegNum<[16, -2, -2]>;
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def R8 : RegisterWithSubRegs<"r8", [R8D]>, DwarfRegNum<[8, -2, -2]>;
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def R9 : RegisterWithSubRegs<"r9", [R9D]>, DwarfRegNum<[9, -2, -2]>;
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def R10 : RegisterWithSubRegs<"r10", [R10D]>, DwarfRegNum<[10, -2, -2]>;
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def R11 : RegisterWithSubRegs<"r11", [R11D]>, DwarfRegNum<[11, -2, -2]>;
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def R12 : RegisterWithSubRegs<"r12", [R12D]>, DwarfRegNum<[12, -2, -2]>;
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def R13 : RegisterWithSubRegs<"r13", [R13D]>, DwarfRegNum<[13, -2, -2]>;
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def R14 : RegisterWithSubRegs<"r14", [R14D]>, DwarfRegNum<[14, -2, -2]>;
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def R15 : RegisterWithSubRegs<"r15", [R15D]>, DwarfRegNum<[15, -2, -2]>;
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def RIP : RegisterWithSubRegs<"rip", [EIP]>, DwarfRegNum<[16, -2, -2]>;
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// MMX Registers. These are actually aliased to ST0 .. ST7
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def MM0 : Register<"MM0">, DwarfRegNum<[41, 29, 29]>;
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def MM1 : Register<"MM1">, DwarfRegNum<[42, 30, 30]>;
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def MM2 : Register<"MM2">, DwarfRegNum<[43, 31, 31]>;
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def MM3 : Register<"MM3">, DwarfRegNum<[44, 32, 32]>;
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def MM4 : Register<"MM4">, DwarfRegNum<[45, 33, 33]>;
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def MM5 : Register<"MM5">, DwarfRegNum<[46, 34, 34]>;
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def MM6 : Register<"MM6">, DwarfRegNum<[47, 35, 35]>;
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def MM7 : Register<"MM7">, DwarfRegNum<[48, 36, 36]>;
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def MM0 : Register<"mm0">, DwarfRegNum<[41, 29, 29]>;
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def MM1 : Register<"mm1">, DwarfRegNum<[42, 30, 30]>;
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def MM2 : Register<"mm2">, DwarfRegNum<[43, 31, 31]>;
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def MM3 : Register<"mm3">, DwarfRegNum<[44, 32, 32]>;
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def MM4 : Register<"mm4">, DwarfRegNum<[45, 33, 33]>;
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def MM5 : Register<"mm5">, DwarfRegNum<[46, 34, 34]>;
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def MM6 : Register<"mm6">, DwarfRegNum<[47, 35, 35]>;
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def MM7 : Register<"mm7">, DwarfRegNum<[48, 36, 36]>;
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// Pseudo Floating Point registers
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def FP0 : Register<"FP0">;
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def FP1 : Register<"FP1">;
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def FP2 : Register<"FP2">;
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def FP3 : Register<"FP3">;
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def FP4 : Register<"FP4">;
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def FP5 : Register<"FP5">;
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def FP6 : Register<"FP6">;
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def FP0 : Register<"fp0">;
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def FP1 : Register<"fp1">;
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def FP2 : Register<"fp2">;
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def FP3 : Register<"fp3">;
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def FP4 : Register<"fp4">;
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def FP5 : Register<"fp5">;
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def FP6 : Register<"fp6">;
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// XMM Registers, used by the various SSE instruction set extensions
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def XMM0: Register<"XMM0">, DwarfRegNum<[17, 21, 21]>;
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def XMM1: Register<"XMM1">, DwarfRegNum<[18, 22, 22]>;
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def XMM2: Register<"XMM2">, DwarfRegNum<[19, 23, 23]>;
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def XMM3: Register<"XMM3">, DwarfRegNum<[20, 24, 24]>;
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def XMM4: Register<"XMM4">, DwarfRegNum<[21, 25, 25]>;
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def XMM5: Register<"XMM5">, DwarfRegNum<[22, 26, 26]>;
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def XMM6: Register<"XMM6">, DwarfRegNum<[23, 27, 27]>;
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def XMM7: Register<"XMM7">, DwarfRegNum<[24, 28, 28]>;
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def XMM0: Register<"xmm0">, DwarfRegNum<[17, 21, 21]>;
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def XMM1: Register<"xmm1">, DwarfRegNum<[18, 22, 22]>;
|
||||
def XMM2: Register<"xmm2">, DwarfRegNum<[19, 23, 23]>;
|
||||
def XMM3: Register<"xmm3">, DwarfRegNum<[20, 24, 24]>;
|
||||
def XMM4: Register<"xmm4">, DwarfRegNum<[21, 25, 25]>;
|
||||
def XMM5: Register<"xmm5">, DwarfRegNum<[22, 26, 26]>;
|
||||
def XMM6: Register<"xmm6">, DwarfRegNum<[23, 27, 27]>;
|
||||
def XMM7: Register<"xmm7">, DwarfRegNum<[24, 28, 28]>;
|
||||
|
||||
// X86-64 only
|
||||
def XMM8: Register<"XMM8">, DwarfRegNum<[25, -2, -2]>;
|
||||
def XMM9: Register<"XMM9">, DwarfRegNum<[26, -2, -2]>;
|
||||
def XMM10: Register<"XMM10">, DwarfRegNum<[27, -2, -2]>;
|
||||
def XMM11: Register<"XMM11">, DwarfRegNum<[28, -2, -2]>;
|
||||
def XMM12: Register<"XMM12">, DwarfRegNum<[29, -2, -2]>;
|
||||
def XMM13: Register<"XMM13">, DwarfRegNum<[30, -2, -2]>;
|
||||
def XMM14: Register<"XMM14">, DwarfRegNum<[31, -2, -2]>;
|
||||
def XMM15: Register<"XMM15">, DwarfRegNum<[32, -2, -2]>;
|
||||
def XMM8: Register<"xmm8">, DwarfRegNum<[25, -2, -2]>;
|
||||
def XMM9: Register<"xmm9">, DwarfRegNum<[26, -2, -2]>;
|
||||
def XMM10: Register<"xmm10">, DwarfRegNum<[27, -2, -2]>;
|
||||
def XMM11: Register<"xmm11">, DwarfRegNum<[28, -2, -2]>;
|
||||
def XMM12: Register<"xmm12">, DwarfRegNum<[29, -2, -2]>;
|
||||
def XMM13: Register<"xmm13">, DwarfRegNum<[30, -2, -2]>;
|
||||
def XMM14: Register<"xmm14">, DwarfRegNum<[31, -2, -2]>;
|
||||
def XMM15: Register<"xmm15">, DwarfRegNum<[32, -2, -2]>;
|
||||
|
||||
// Floating point stack registers
|
||||
def ST0 : Register<"ST(0)">, DwarfRegNum<[33, 12, 11]>;
|
||||
def ST1 : Register<"ST(1)">, DwarfRegNum<[34, 13, 12]>;
|
||||
def ST2 : Register<"ST(2)">, DwarfRegNum<[35, 14, 13]>;
|
||||
def ST3 : Register<"ST(3)">, DwarfRegNum<[36, 15, 14]>;
|
||||
def ST4 : Register<"ST(4)">, DwarfRegNum<[37, 16, 15]>;
|
||||
def ST5 : Register<"ST(5)">, DwarfRegNum<[38, 17, 16]>;
|
||||
def ST6 : Register<"ST(6)">, DwarfRegNum<[39, 18, 17]>;
|
||||
def ST7 : Register<"ST(7)">, DwarfRegNum<[40, 19, 18]>;
|
||||
def ST0 : Register<"st(0)">, DwarfRegNum<[33, 12, 11]>;
|
||||
def ST1 : Register<"st(1)">, DwarfRegNum<[34, 13, 12]>;
|
||||
def ST2 : Register<"st(2)">, DwarfRegNum<[35, 14, 13]>;
|
||||
def ST3 : Register<"st(3)">, DwarfRegNum<[36, 15, 14]>;
|
||||
def ST4 : Register<"st(4)">, DwarfRegNum<[37, 16, 15]>;
|
||||
def ST5 : Register<"st(5)">, DwarfRegNum<[38, 17, 16]>;
|
||||
def ST6 : Register<"st(6)">, DwarfRegNum<[39, 18, 17]>;
|
||||
def ST7 : Register<"st(7)">, DwarfRegNum<[40, 19, 18]>;
|
||||
|
||||
// Status flags register
|
||||
def EFLAGS : Register<"EFLAGS">;
|
||||
def EFLAGS : Register<"eflags">;
|
||||
}
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user