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[ARM] Improve build attributes emission.

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llvm-svn: 192111
This commit is contained in:
Amara Emerson 2013-10-07 16:55:23 +00:00
parent 128d9134e7
commit 688cdc2151
9 changed files with 212 additions and 63 deletions
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3
lib/Target/ARM/ARM.td
View File

@ -294,7 +294,8 @@ def : ProcessorModel<"cortex-a15", CortexA9Model,
def : ProcessorModel<"cortex-r5", CortexA8Model,
[ProcR5, HasV7Ops, FeatureDB,
FeatureVFP3, FeatureDSPThumb2,
FeatureHasRAS, FeatureRClass]>;
FeatureHasRAS, FeatureVFPOnlySP,
FeatureRClass]>;
// V7M Processors.
def : ProcNoItin<"cortex-m3", [HasV7Ops,

130
lib/Target/ARM/ARMAsmPrinter.cpp
View File

@ -740,6 +740,33 @@ void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
// to appear in the .ARM.attributes section in ELF.
// Instead of subclassing the MCELFStreamer, we do the work here.
static ARMBuildAttrs::CPUArch getArchForCPU(StringRef CPU,
const ARMSubtarget *Subtarget) {
if (CPU == "xscale")
return ARMBuildAttrs::v5TEJ;
if (Subtarget->hasV8Ops())
return ARMBuildAttrs::v8;
else if (Subtarget->hasV7Ops()) {
if (Subtarget->isMClass() && Subtarget->hasThumb2DSP())
return ARMBuildAttrs::v7E_M;
return ARMBuildAttrs::v7;
} else if (Subtarget->hasV6T2Ops())
return ARMBuildAttrs::v6T2;
else if (Subtarget->hasV6MOps())
return ARMBuildAttrs::v6S_M;
else if (Subtarget->hasV6Ops())
return ARMBuildAttrs::v6;
else if (Subtarget->hasV5TEOps())
return ARMBuildAttrs::v5TE;
else if (Subtarget->hasV5TOps())
return ARMBuildAttrs::v5T;
else if (Subtarget->hasV4TOps())
return ARMBuildAttrs::v4T;
else
return ARMBuildAttrs::v4;
}
void ARMAsmPrinter::emitAttributes() {
emitARMAttributeSection();
@ -759,53 +786,44 @@ void ARMAsmPrinter::emitAttributes() {
std::string CPUString = Subtarget->getCPUString();
if (CPUString == "cortex-a8" ||
Subtarget->isCortexA8()) {
AttrEmitter->EmitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a8");
AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
if (CPUString != "generic")
AttrEmitter->EmitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch,
getArchForCPU(CPUString, Subtarget));
if (Subtarget->isAClass()) {
AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile,
ARMBuildAttrs::ApplicationProfile);
AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
ARMBuildAttrs::Allowed);
AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
ARMBuildAttrs::AllowThumb32);
// Fixme: figure out when this is emitted.
//AttrEmitter->EmitAttribute(ARMBuildAttrs::WMMX_arch,
// ARMBuildAttrs::AllowWMMXv1);
//
} else if (Subtarget->isRClass()) {
AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile,
ARMBuildAttrs::RealTimeProfile);
} else if (Subtarget->isMClass()){
AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile,
ARMBuildAttrs::MicroControllerProfile);
}
/// ADD additional Else-cases here!
} else if (CPUString == "xscale") {
AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5TEJ);
AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
ARMBuildAttrs::Allowed);
AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use, Subtarget->hasARMOps() ?
ARMBuildAttrs::Allowed : ARMBuildAttrs::Not_Allowed);
if (Subtarget->isThumb1Only()) {
AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
ARMBuildAttrs::Allowed);
} else if (Subtarget->hasV8Ops())
AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v8);
else if (Subtarget->hasV7Ops()) {
AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
} else if (Subtarget->hasThumb2()) {
AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
ARMBuildAttrs::AllowThumb32);
} else if (Subtarget->hasV6T2Ops())
AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v6T2);
else if (Subtarget->hasV6Ops())
AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v6);
else if (Subtarget->hasV5TEOps())
AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5TE);
else if (Subtarget->hasV5TOps())
AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5T);
else if (Subtarget->hasV4TOps())
AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
else
AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4);
}
if (Subtarget->hasNEON() && emitFPU) {
/* NEON is not exactly a VFP architecture, but GAS emit one of
* neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
if (Subtarget->hasFPARMv8())
AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
"neon-fp-armv8");
if (Subtarget->hasFPARMv8()) {
if (Subtarget->hasCrypto())
AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
"crypto-neon-fp-armv8");
else
AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
"neon-fp-armv8");
}
else if (Subtarget->hasVFP4())
AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
"neon-vfpv4");
@ -825,14 +843,16 @@ void ARMAsmPrinter::emitAttributes() {
/* VFPv4 + .fpu */
} else if (Subtarget->hasVFP4()) {
AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
ARMBuildAttrs::AllowFPv4A);
Subtarget->isFPOnlySP() ? ARMBuildAttrs::AllowFPv4B :
ARMBuildAttrs::AllowFPv4A);
if (emitFPU)
AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv4");
/* VFPv3 + .fpu */
} else if (Subtarget->hasVFP3()) {
AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
ARMBuildAttrs::AllowFPv3A);
Subtarget->isFPOnlySP() ? ARMBuildAttrs::AllowFPv3B :
ARMBuildAttrs::AllowFPv3A);
if (emitFPU)
AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv3");
@ -856,19 +876,21 @@ void ARMAsmPrinter::emitAttributes() {
}
// Signal various FP modes.
if (!TM.Options.UnsafeFPMath) {
AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal,
ARMBuildAttrs::Allowed);
AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
ARMBuildAttrs::Allowed);
}
if (Subtarget->hasVFP2()) {
if (!TM.Options.UnsafeFPMath) {
AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal,
ARMBuildAttrs::Allowed);
AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
ARMBuildAttrs::Allowed);
}
if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
ARMBuildAttrs::Allowed);
else
AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
ARMBuildAttrs::AllowIEE754);
if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
ARMBuildAttrs::Allowed);
else
AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
ARMBuildAttrs::AllowIEE754);
}
// FIXME: add more flags to ARMBuildAttrs.h
// 8-bytes alignment stuff.
@ -882,8 +904,12 @@ void ARMAsmPrinter::emitAttributes() {
}
// FIXME: Should we signal R9 usage?
if (Subtarget->hasDivide())
AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
if (Subtarget->hasDivide()) {
// Check if hardware divide is only available in thumb2 or ARM as well.
AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use,
Subtarget->hasDivideInARMMode() ? ARMBuildAttrs::AllowDIVExt :
ARMBuildAttrs::AllowDIVIfExists);
}
AttrEmitter->Finish();
delete AttrEmitter;

8
lib/Target/ARM/ARMBuildAttrs.h
View File

@ -128,7 +128,13 @@ namespace ARMBuildAttrs {
// Tag_ABI_FP_number_model, (=23), uleb128
AllowRTABI = 2, // numbers, infinities, and one quiet NaN (see [RTABI])
AllowIEE754 = 3 // this code to use all the IEEE 754-defined FP encodings
AllowIEE754 = 3, // this code to use all the IEEE 754-defined FP encodings
// Tag_DIV_use, (=44), uleb128
AllowDIVIfExists = 0, // Allow hardware divide if available in arch, or no info exists.
DisallowDIV = 1, // Hardware divide explicitly disallowed
AllowDIVExt = 2 // Allow hardware divide as optional architecture extension above
// the base arch specified by Tag_CPU_arch and Tag_CPU_arch_profile.
};
}

3
lib/Target/ARM/ARMSubtarget.cpp
View File

@ -76,6 +76,7 @@ void ARMSubtarget::initializeEnvironment() {
HasV5TOps = false;
HasV5TEOps = false;
HasV6Ops = false;
HasV6MOps = false;
HasV6T2Ops = false;
HasV7Ops = false;
HasV8Ops = false;
@ -158,7 +159,7 @@ void ARMSubtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) {
// Thumb2 implies at least V6T2. FIXME: Fix tests to explicitly specify a
// ARM version or CPU and then remove this.
if (!HasV6T2Ops && hasThumb2())
HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true;
HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6MOps = HasV6T2Ops = true;
// Keep a pointer to static instruction cost data for the specified CPU.
SchedModel = getSchedModelForCPU(CPUString);

1
lib/Target/ARM/ARMSubtarget.h
View File

@ -234,6 +234,7 @@ public:
bool hasV5TOps() const { return HasV5TOps; }
bool hasV5TEOps() const { return HasV5TEOps; }
bool hasV6Ops() const { return HasV6Ops; }
bool hasV6MOps() const { return HasV6MOps; }
bool hasV6T2Ops() const { return HasV6T2Ops; }
bool hasV7Ops() const { return HasV7Ops; }
bool hasV8Ops() const { return HasV8Ops; }

2
lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
View File

@ -149,7 +149,7 @@ std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) {
isThumb = true;
if (NoCPU)
// v6m: FeatureNoARM, FeatureMClass
ARMArchFeature = "+v6,+noarm,+mclass";
ARMArchFeature = "+v6m,+noarm,+mclass";
else
ARMArchFeature = "+v6";
} else

115
test/CodeGen/ARM/2010-09-29-mc-asm-header-test.ll
View File

@ -1,11 +1,55 @@
; RUN: llc < %s -mtriple=armv6-linux-gnueabi | FileCheck %s --check-prefix=V6
; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi | FileCheck %s --check-prefix=V6M
; RUN: llc < %s -mtriple=armv6-linux-gnueabi -mcpu=arm1156t2f-s | FileCheck %s --check-prefix=ARM1156T2F-S
; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi | FileCheck %s --check-prefix=V7M
; RUN: llc < %s -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=V7
; RUN: llc < %s -mtriple=armv8-linux-gnueabi | FileCheck %s --check-prefix=V8
; RUN: llc < %s -mtriple=thumbv8-linux-gnueabi | FileCheck %s --check-prefix=Vt8
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=+fp-armv8 | FileCheck %s --check-prefix=V8-FPARMv8
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=+neon | FileCheck %s --check-prefix=V8-NEON
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=+fp-armv8 -mattr=+neon | FileCheck %s --check-prefix=V8-FPARMv8-NEON
; This tests that MC/asm header conversion is smooth
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=+fp-armv8,+neon,+crypto | FileCheck %s --check-prefix=V8-FPARMv8-NEON-CRYPTO
; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mattr=-neon,-vfp2 | FileCheck %s --check-prefix=NOFP
; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 | FileCheck %s --check-prefix=CORTEX-A9
; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0 | FileCheck %s --check-prefix=CORTEX-M0
; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 | FileCheck %s --check-prefix=CORTEX-M4
; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r5 | FileCheck %s --check-prefix=CORTEX-R5
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a53 | FileCheck %s --check-prefix=CORTEX-A53
; This tests that MC/asm header conversion is smooth and that build attributes are correct
;
; V6: .eabi_attribute 6, 6
; V6: .eabi_attribute 8, 1
; V6: .eabi_attribute 24, 1
; V6: .eabi_attribute 25, 1
; V6M: .eabi_attribute 6, 12
; V6M: .eabi_attribute 7, 77
; V6M: .eabi_attribute 8, 0
; V6M: .eabi_attribute 9, 1
; V6M: .eabi_attribute 24, 1
; V6M: .eabi_attribute 25, 1
; ARM1156T2F-S: .cpu arm1156t2f-s
; ARM1156T2F-S: .eabi_attribute 6, 8
; ARM1156T2F-S: .eabi_attribute 8, 1
; ARM1156T2F-S: .eabi_attribute 9, 2
; ARM1156T2F-S: .eabi_attribute 10, 2
; ARM1156T2F-S: .fpu vfpv2
; ARM1156T2F-S: .eabi_attribute 20, 1
; ARM1156T2F-S: .eabi_attribute 21, 1
; ARM1156T2F-S: .eabi_attribute 23, 3
; ARM1156T2F-S: .eabi_attribute 24, 1
; ARM1156T2F-S: .eabi_attribute 25, 1
; V7M: .eabi_attribute 6, 10
; V7M: .eabi_attribute 7, 77
; V7M: .eabi_attribute 8, 0
; V7M: .eabi_attribute 9, 2
; V7M: .eabi_attribute 24, 1
; V7M: .eabi_attribute 25, 1
; V7M: .eabi_attribute 44, 0
; V7: .syntax unified
; V7: .eabi_attribute 6, 10
; V7: .eabi_attribute 20, 1
@ -34,6 +78,75 @@
; V8-FPARMv8-NEON: .eabi_attribute 6, 14
; V8-FPARMv8-NEON: .fpu neon-fp-armv8
; V8-FPARMv8-NEON: .eabi_attribute 10, 7
; V8-FPARMv8-NEON: .eabi_attribute 12, 3
; V8-FPARMv8-NEON-CRYPTO: .syntax unified
; V8-FPARMv8-NEON-CRYPTO: .eabi_attribute 6, 14
; V8-FPARMv8-NEON-CRYPTO: .fpu crypto-neon-fp-armv8
; V8-FPARMv8-NEON-CRYPTO: .eabi_attribute 10, 7
; V8-FPARMv8-NEON-CRYPTO: .eabi_attribute 12, 3
; NOFP-NOT: .eabi_attribute 20
; NOFP-NOT: .eabi_attribute 21
; NOFP-NOT: .eabi_attribute 23
; CORTEX-A9: .cpu cortex-a9
; CORTEX-A9: .eabi_attribute 6, 10
; CORTEX-A9: .eabi_attribute 7, 65
; CORTEX-A9: .eabi_attribute 8, 1
; CORTEX-A9: .eabi_attribute 9, 2
; CORTEX-A9: .fpu neon
; CORTEX-A9: .eabi_attribute 10, 3
; CORTEX-A9: .eabi_attribute 12, 1
; CORTEX-A9: .eabi_attribute 20, 1
; CORTEX-A9: .eabi_attribute 21, 1
; CORTEX-A9: .eabi_attribute 23, 3
; CORTEX-A9: .eabi_attribute 24, 1
; CORTEX-A9: .eabi_attribute 25, 1
; CORTEX-M0: .cpu cortex-m0
; CORTEX-M0: .eabi_attribute 6, 12
; CORTEX-M0: .eabi_attribute 7, 77
; CORTEX-M0: .eabi_attribute 8, 0
; CORTEX-M0: .eabi_attribute 9, 1
; CORTEX-M0: .eabi_attribute 24, 1
; CORTEX-M0: .eabi_attribute 25, 1
; CORTEX-M4: .cpu cortex-m4
; CORTEX-M4: .eabi_attribute 6, 13
; CORTEX-M4: .eabi_attribute 7, 77
; CORTEX-M4: .eabi_attribute 8, 0
; CORTEX-M4: .eabi_attribute 9, 2
; CORTEX-M4: .eabi_attribute 10, 6
; CORTEX-M4: .fpu vfpv4
; CORTEX-M4: .eabi_attribute 20, 1
; CORTEX-M4: .eabi_attribute 21, 1
; CORTEX-M4: .eabi_attribute 23, 3
; CORTEX-M4: .eabi_attribute 24, 1
; CORTEX-M4: .eabi_attribute 25, 1
; CORTEX-M4: .eabi_attribute 44, 0
; CORTEX-R5: .cpu cortex-r5
; CORTEX-R5: .eabi_attribute 6, 10
; CORTEX-R5: .eabi_attribute 7, 82
; CORTEX-R5: .eabi_attribute 8, 1
; CORTEX-R5: .eabi_attribute 9, 2
; CORTEX-R5: .eabi_attribute 10, 4
; CORTEX-R5: .fpu vfpv3
; CORTEX-R5: .eabi_attribute 20, 1
; CORTEX-R5: .eabi_attribute 21, 1
; CORTEX-R5: .eabi_attribute 23, 3
; CORTEX-R5: .eabi_attribute 24, 1
; CORTEX-R5: .eabi_attribute 25, 1
; CORTEX-R5: .eabi_attribute 44, 2
; CORTEX-A53: .cpu cortex-a53
; CORTEX-A53: .eabi_attribute 6, 14
; CORTEX-A53: .eabi_attribute 7, 65
; CORTEX-A53: .eabi_attribute 8, 1
; CORTEX-A53: .eabi_attribute 9, 2
; CORTEX-A53: .eabi_attribute 24, 1
; CORTEX-A53: .eabi_attribute 25, 1
define i32 @f(i64 %z) {
ret i32 0

6
test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll
View File

@ -15,14 +15,14 @@
; BASIC-NEXT: ]
; BASIC-NEXT: Address: 0x0
; BASIC-NEXT: Offset: 0x3C
; BASIC-NEXT: Size: 28
; BASIC-NEXT: Size: 24
; BASIC-NEXT: Link: 0
; BASIC-NEXT: Info: 0
; BASIC-NEXT: AddressAlignment: 1
; BASIC-NEXT: EntrySize: 0
; BASIC-NEXT: SectionData (
; BASIC-NEXT: 0000: 411B0000 00616561 62690001 11000000
; BASIC-NEXT: 0010: 06011401 15011703 18011901
; BASIC-NEXT: 0000: 41170000 00616561 62690001 0D000000
; BASIC-NEXT: 0010: 06010801 18011901
; BASIC-NEXT: )
; CORTEXA8: Name: .ARM.attributes

7
test/MC/ARM/xscale-attributes.ll
View File

@ -26,13 +26,14 @@ entry:
; OBJ-NEXT: ]
; OBJ-NEXT: Address: 0x0
; OBJ-NEXT: Offset: 0x38
; OBJ-NEXT: Size: 32
; OBJ-NEXT: Size: 34
; OBJ-NEXT: Link: 0
; OBJ-NEXT: Info: 0
; OBJ-NEXT: AddressAlignment: 1
; OBJ-NEXT: EntrySize: 0
; OBJ-NEXT: SectionData (
; OBJ-NEXT: 0000: 411F0000 00616561 62690001 15000000
; OBJ-NEXT: 0010: 06050801 09011401 15011703 18011901
; OBJ-NEXT: 0000: 41210000 00616561 62690001 17000000
; OBJ-NEXT: 0010: 05585343 414C4500 06050801 09011801
; OBJ-NEXT: 0020: 1901
; OBJ-NEXT: )
; OBJ-NEXT: }