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llvm can't correctly support 'H', 'Q' and 'R' modifiers. Just mark it an error.

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llvm-svn: 104891
This commit is contained in:
Evan Cheng 2010-05-27 22:08:38 +00:00
parent 999057d413
commit 68be5ab54e
2 changed files with 2 additions and 26 deletions
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20
lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
View File

@ -1064,27 +1064,11 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
printOperand(MI, OpNum, O); printOperand(MI, OpNum, O);
return false; return false;
case 'Q': case 'Q':
// Print the least significant half of a register pair.
if (TM.getTargetData()->isBigEndian())
break;
printOperand(MI, OpNum, O);
return false;
case 'R': case 'R':
// Print the most significant half of a register pair.
if (TM.getTargetData()->isLittleEndian())
break;
printOperand(MI, OpNum, O);
return false;
case 'H': case 'H':
break; llvm_unreachable("llvm does not support 'Q', 'R', and 'H' modifiers!");
}
// Print the second half of a register pair (for 'Q', 'R' or 'H').
// Verify that this operand has two consecutive registers.
if (!MI->getOperand(OpNum).isReg() ||
OpNum+1 == MI->getNumOperands() ||
!MI->getOperand(OpNum+1).isReg())
return true; return true;
++OpNum; }
} }
printOperand(MI, OpNum, O); printOperand(MI, OpNum, O);

8
test/CodeGen/ARM/inlineasm.ll
View File

@ -6,14 +6,6 @@ define i32 @test1(i32 %tmp54) {
} }
define void @test2() { define void @test2() {
%tmp1 = call i64 asm "ldmia $1!, {$0, ${0:H}}", "=r,=*r,1"( i32** null, i32* null ) ; <i64> [#uses=2]
%tmp2 = lshr i64 %tmp1, 32 ; <i64> [#uses=1]
%tmp3 = trunc i64 %tmp2 to i32 ; <i32> [#uses=1]
%tmp4 = call i32 asm "pkhbt $0, $1, $2, lsl #16", "=r,r,r"( i32 0, i32 %tmp3 ) ; <i32> [#uses=0]
ret void
}
define void @test3() {
tail call void asm sideeffect "/* number: ${0:c} */", "i"( i32 1 ) tail call void asm sideeffect "/* number: ${0:c} */", "i"( i32 1 )
ret void ret void
} }