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SelectionDAG: Expand i64 = FP_TO_SINT i32

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llvm-svn: 211108
This commit is contained in:
Tom Stellard 2014-06-17 16:53:07 +00:00
parent 1513f160dc
commit 6987d06184
3 changed files with 72 additions and 0 deletions
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59
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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@ -3152,6 +3152,65 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
Node->getOperand(0), Node->getValueType(0), dl);
Results.push_back(Tmp1);
break;
case ISD::FP_TO_SINT: {
EVT VT = Node->getOperand(0).getValueType();
EVT NVT = Node->getValueType(0);
// FIXME: Only f32 to i64 conversions are supported.
if (VT != MVT::f32 || NVT != MVT::i64)
break;
// Expand f32 -> i64 conversion
// This algorithm comes from compiler-rt's implementation of fixsfdi:
// https://github.com/llvm-mirror/compiler-rt/blob/master/lib/builtins/fixsfdi.c
EVT IntVT = EVT::getIntegerVT(*DAG.getContext(),
VT.getSizeInBits());
SDValue ExponentMask = DAG.getConstant(0x7F800000, IntVT);
SDValue ExponentLoBit = DAG.getConstant(23, IntVT);
SDValue Bias = DAG.getConstant(127, IntVT);
SDValue SignMask = DAG.getConstant(APInt::getSignBit(VT.getSizeInBits()),
IntVT);
SDValue SignLowBit = DAG.getConstant(VT.getSizeInBits() - 1, IntVT);
SDValue MantissaMask = DAG.getConstant(0x007FFFFF, IntVT);
SDValue Bits = DAG.getNode(ISD::BITCAST, dl, IntVT, Node->getOperand(0));
SDValue ExponentBits = DAG.getNode(ISD::SRL, dl, IntVT,
DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask),
DAG.getZExtOrTrunc(ExponentLoBit, dl, TLI.getShiftAmountTy(IntVT)));
SDValue Exponent = DAG.getNode(ISD::SUB, dl, IntVT, ExponentBits, Bias);
SDValue Sign = DAG.getNode(ISD::SRA, dl, IntVT,
DAG.getNode(ISD::AND, dl, IntVT, Bits, SignMask),
DAG.getZExtOrTrunc(SignLowBit, dl, TLI.getShiftAmountTy(IntVT)));
Sign = DAG.getSExtOrTrunc(Sign, dl, NVT);
SDValue R = DAG.getNode(ISD::OR, dl, IntVT,
DAG.getNode(ISD::AND, dl, IntVT, Bits, MantissaMask),
DAG.getConstant(0x00800000, IntVT));
R = DAG.getZExtOrTrunc(R, dl, NVT);
R = DAG.getSelectCC(dl, Exponent, ExponentLoBit,
DAG.getNode(ISD::SHL, dl, NVT, R,
DAG.getZExtOrTrunc(
DAG.getNode(ISD::SUB, dl, IntVT, Exponent, ExponentLoBit),
dl, TLI.getShiftAmountTy(IntVT))),
DAG.getNode(ISD::SRL, dl, NVT, R,
DAG.getZExtOrTrunc(
DAG.getNode(ISD::SUB, dl, IntVT, ExponentLoBit, Exponent),
dl, TLI.getShiftAmountTy(IntVT))),
ISD::SETGT);
SDValue Ret = DAG.getNode(ISD::SUB, dl, NVT,
DAG.getNode(ISD::XOR, dl, NVT, R, Sign),
Sign);
Results.push_back(DAG.getSelectCC(dl, Exponent, DAG.getConstant(0, IntVT),
DAG.getConstant(0, NVT), Ret, ISD::SETLT));
break;
}
case ISD::FP_TO_UINT: {
SDValue True, False;
EVT VT = Node->getOperand(0).getValueType();

1
lib/Target/R600/AMDGPUISelLowering.cpp
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@ -253,6 +253,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
setOperationAction(ISD::ROTL, MVT::i64, Expand);
setOperationAction(ISD::ROTR, MVT::i64, Expand);
setOperationAction(ISD::FP_TO_SINT, MVT::i64, Expand);
setOperationAction(ISD::MUL, MVT::i64, Expand);
setOperationAction(ISD::MULHU, MVT::i64, Expand);
setOperationAction(ISD::MULHS, MVT::i64, Expand);

12
test/CodeGen/R600/fp_to_sint_i64.ll Normal file
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@ -0,0 +1,12 @@
; FIXME: Merge into fp_to_sint.ll when EG/NI supports 64-bit types
; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI %s
; SI-LABEL: @fp_to_sint_i64
; Check that the compiler doesn't crash with a "cannot select" error
; SI: S_ENDPGM
define void @fp_to_sint_i64 (i64 addrspace(1)* %out, float %in) {
entry:
%0 = fptosi float %in to i64
store i64 %0, i64 addrspace(1)* %out
ret void
}