[AArch64][GlobalISel] Select all fptruncs.

We already support these in tablegen, but we're matching the wrong
operator (libm ftrunc).  Fix that.

While there, drop the c++ code, support COPYs of FPR16, and add tests
for the other types.

llvm-svn: 313073

include/llvm/Target/GlobalISel/SelectionDAGCompat.td

@@ -51,7 +51,7 @@ def : GINodeEquiv<G_ASHR, sra>;
 def : GINodeEquiv<G_SELECT, select>;
 def : GINodeEquiv<G_FNEG, fneg>;
 def : GINodeEquiv<G_FPEXT, fpextend>;
-def : GINodeEquiv<G_FPTRUNC, ftrunc>;
+def : GINodeEquiv<G_FPTRUNC, fpround>;
 def : GINodeEquiv<G_FPTOSI, fp_to_sint>;
 def : GINodeEquiv<G_FPTOUI, fp_to_uint>;
 def : GINodeEquiv<G_SITOFP, sint_to_fp>;

lib/Target/AArch64/AArch64InstructionSelector.cpp

@@ -317,7 +317,9 @@ static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,
   const TargetRegisterClass *RC = nullptr;
 
   if (RegBank.getID() == AArch64::FPRRegBankID) {
-    if (DstSize <= 32)
+    if (DstSize <= 16)
+      RC = &AArch64::FPR16RegClass;
+    else if (DstSize <= 32)
       RC = &AArch64::FPR32RegClass;
     else if (DstSize <= 64)
       RC = &AArch64::FPR64RegClass;
@@ -1205,33 +1207,6 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const {
     return true;
   }
 
-  case TargetOpcode::G_FPTRUNC: {
-    if (MRI.getType(I.getOperand(0).getReg()) != LLT::scalar(32)) {
-      DEBUG(dbgs() << "G_FPTRUNC to type " << Ty
-                   << ", expected: " << LLT::scalar(32) << '\n');
-      return false;
-    }
-
-    if (MRI.getType(I.getOperand(1).getReg()) != LLT::scalar(64)) {
-      DEBUG(dbgs() << "G_FPTRUNC from type " << Ty
-                   << ", expected: " << LLT::scalar(64) << '\n');
-      return false;
-    }
-
-    const unsigned DefReg = I.getOperand(0).getReg();
-    const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI);
-
-    if (RB.getID() != AArch64::FPRRegBankID) {
-      DEBUG(dbgs() << "G_FPTRUNC on bank: " << RB << ", expected: FPR\n");
-      return false;
-    }
-
-    I.setDesc(TII.get(AArch64::FCVTSDr));
-    constrainSelectedInstRegOperands(I, TII, TRI, RBI);
-
-    return true;
-  }
-
   case TargetOpcode::G_SELECT: {
     if (MRI.getType(I.getOperand(1).getReg()) != LLT::scalar(1)) {
       DEBUG(dbgs() << "G_SELECT cond has type: " << Ty

test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir

@@ -3,7 +3,10 @@
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
 
-  define void @fptrunc() { ret void }
+  define void @fptrunc_s16_s32_fpr() { ret void }
+  define void @fptrunc_s16_s64_fpr() { ret void }
+  define void @fptrunc_s32_s64_fpr() { ret void }
+
   define void @fpext() { ret void }
 
   define void @sitofp_s32_s32_fpr() { ret void }
@@ -28,8 +31,58 @@
 ...
 
 ---
-# CHECK-LABEL: name: fptrunc
+# CHECK-LABEL: name: fptrunc_s16_s32_fpr
-name:            fptrunc
+name:            fptrunc_s16_s32_fpr
+legalized:       true
+regBankSelected: true
+
+# CHECK:      registers:
+# CHECK: - { id: 0, class: fpr32, preferred-register: '' }
+# CHECK: - { id: 1, class: fpr16, preferred-register: '' }
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+
+# CHECK:  body:
+# CHECK:    %0 = COPY %s0
+# CHECK:    %1 = FCVTHSr %0
+body:             |
+  bb.0:
+    liveins: %s0
+
+    %0(s32) = COPY %s0
+    %1(s16) = G_FPTRUNC %0
+    %h0 = COPY %1(s16)
+...
+
+---
+# CHECK-LABEL: name: fptrunc_s16_s64_fpr
+name:            fptrunc_s16_s64_fpr
+legalized:       true
+regBankSelected: true
+
+# CHECK:      registers:
+# CHECK: - { id: 0, class: fpr64, preferred-register: '' }
+# CHECK: - { id: 1, class: fpr16, preferred-register: '' }
+registers:
+  - { id: 0, class: fpr }
+  - { id: 1, class: fpr }
+
+# CHECK:  body:
+# CHECK:    %0 = COPY %d0
+# CHECK:    %1 = FCVTHDr %0
+body:             |
+  bb.0:
+    liveins: %d0
+
+    %0(s64) = COPY %d0
+    %1(s16) = G_FPTRUNC %0
+    %h0 = COPY %1(s16)
+...
+
+---
+# CHECK-LABEL: name: fptrunc_s32_s64_fpr
+name:            fptrunc_s32_s64_fpr
 legalized:       true
 regBankSelected: true