mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-22 18:54:02 +01:00
Fix some comment typos.
llvm-svn: 244402
This commit is contained in:
Benjamin Kramer
parent
d34b4538b5
commit
69a3fdb314
@ -42,7 +42,7 @@ class PreservedAnalyses;
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///
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/// This class constructs tables that hold the target library information and
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/// make it available. However, it is somewhat expensive to compute and only
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/// depends on the triple. So users typicaly interact with the \c
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/// depends on the triple. So users typically interact with the \c
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/// TargetLibraryInfo wrapper below.
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class TargetLibraryInfoImpl {
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friend class TargetLibraryInfo;
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@ -37,7 +37,7 @@ struct EVT;
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/// Given an LLVM IR aggregate type and a sequence of insertvalue or
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/// extractvalue indices that identify a member, return the linearized index of
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/// the start of the member, i.e the number of element in memory before the
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/// seeked one. This is disconnected from the number of bytes.
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/// sought one. This is disconnected from the number of bytes.
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///
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/// \param Ty is the type indexed by \p Indices.
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/// \param Indices is an optional pointer in the indices list to the current
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@ -134,7 +134,7 @@ inline hash_code hash_value(const AllowedRegVector &OptRegs) {
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hash_combine_range(OStart, OEnd));
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}
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/// \brief Holds graph-level metadata relevent to PBQP RA problems.
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/// \brief Holds graph-level metadata relevant to PBQP RA problems.
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class GraphMetadata {
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private:
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typedef ValuePool<AllowedRegVector> AllowedRegVecPool;
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@ -1389,7 +1389,7 @@ public:
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void replaceFunction(std::nullptr_t) { replaceOperandWith(7, nullptr); }
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/// @}
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/// \brief Check if this subprogram decribes the given function.
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/// \brief Check if this subprogram describes the given function.
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///
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/// FIXME: Should this be looking through bitcasts?
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bool describes(const Function *F) const;
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@ -1943,7 +1943,7 @@ public:
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/// \brief Check that a location is valid for this variable.
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///
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/// Check that \c DL exists, is in the same subprogram, and has the same
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/// inlined-at location as \c this. (Otherwise, it's not a valid attachemnt
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/// inlined-at location as \c this. (Otherwise, it's not a valid attachment
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/// to a \a DbgInfoIntrinsic.)
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bool isValidLocationForIntrinsic(const DILocation *DL) const {
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return DL && getScope()->getSubprogram() == DL->getScope()->getSubprogram();
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@ -104,7 +104,7 @@ struct CounterExpression {
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};
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/// \brief A Counter expression builder is used to construct the
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/// counter expressions. It avoids unecessary duplication
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/// counter expressions. It avoids unnecessary duplication
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/// and simplifies algebraic expressions.
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class CounterExpressionBuilder {
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/// \brief A list of all the counter expressions
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@ -443,7 +443,7 @@ public:
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/// \brief Get the list of function instantiations in the file.
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///
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/// Fucntions that are instantiated more than once, such as C++ template
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/// Functions that are instantiated more than once, such as C++ template
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/// specializations, have distinct coverage records for each instantiation.
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std::vector<const FunctionRecord *> getInstantiations(StringRef Filename);
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@ -71,7 +71,7 @@ private:
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/// \param Key unique key for option
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/// \param O option to map to \p Key
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///
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/// Allocated cl::Options are owened by the OptionRegistry and are deallocated
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/// Allocated cl::Options are owned by the OptionRegistry and are deallocated
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/// on destruction or removal
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void addOption(void *Key, cl::Option *O);
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@ -91,7 +91,7 @@ public:
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/// Options are keyed off the template parameters to generate unique static
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/// characters. The template parameters are (1) the type of the data the
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/// option stores (\p ValT), the class that will read the option (\p Base),
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/// and the memeber that the class will store the data into (\p Mem).
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/// and the member that the class will store the data into (\p Mem).
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template <typename ValT, typename Base, ValT(Base::*Mem)>
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static void registerOption(const char *ArgStr, const char *Desc,
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const ValT &InitValue) {
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@ -282,7 +282,7 @@ int compare(DigitsT LDigits, int16_t LScale, DigitsT RDigits, int16_t RScale) {
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///
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/// As a convenience, returns the matching scale. If the output value of one
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/// number is zero, returns the scale of the other. If both are zero, which
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/// scale is returned is unspecifed.
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/// scale is returned is unspecified.
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template <class DigitsT>
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int16_t matchScales(DigitsT &LDigits, int16_t &LScale, DigitsT &RDigits,
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int16_t &RScale) {
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@ -334,7 +334,7 @@ std::pair<DigitsT, int16_t> getSum(DigitsT LDigits, int16_t LScale,
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DigitsT RDigits, int16_t RScale) {
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static_assert(!std::numeric_limits<DigitsT>::is_signed, "expected unsigned");
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// Check inputs up front. This is only relevent if addition overflows, but
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// Check inputs up front. This is only relevant if addition overflows, but
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// testing here should catch more bugs.
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assert(LScale < INT16_MAX && "scale too large");
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assert(RScale < INT16_MAX && "scale too large");
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@ -246,7 +246,7 @@ public:
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/// outputting colored text, or before program exit.
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virtual raw_ostream &resetColor() { return *this; }
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/// Reverses the forground and background colors.
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/// Reverses the foreground and background colors.
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virtual raw_ostream &reverseColor() { return *this; }
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/// This function determines if this stream is connected to a "tty" or
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@ -316,7 +316,7 @@ private:
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};
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/// An abstract base class for streams implementations that also support a
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/// pwrite operation. This is usefull for code that can mostly stream out data,
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/// pwrite operation. This is useful for code that can mostly stream out data,
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/// but needs to patch in a header that needs to know the output size.
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class raw_pwrite_stream : public raw_ostream {
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virtual void pwrite_impl(const char *Ptr, size_t Size, uint64_t Offset) = 0;
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@ -126,7 +126,7 @@ enum {
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/// Loading instruction that may page fault, bundled with associated
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/// information on how to handle such a page fault. It is intended to support
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/// "zero cost" null checks in managed languages by allowing LLVM to fold
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/// comparisions into existing memory operations.
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/// comparisons into existing memory operations.
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FAULTING_LOAD_OP = 22,
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};
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} // end namespace TargetOpcode
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@ -125,7 +125,7 @@ public:
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static InstDesc isRecurrenceInstr(Instruction *I, RecurrenceKind Kind,
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InstDesc &Prev, bool HasFunNoNaNAttr);
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/// Returns true if instuction I has multiple uses in Insts
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/// Returns true if instruction I has multiple uses in Insts
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static bool hasMultipleUsesOf(Instruction *I,
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SmallPtrSetImpl<Instruction *> &Insts);
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@ -253,7 +253,7 @@ bool promoteLoopAccessesToScalars(AliasSet &, SmallVectorImpl<BasicBlock*> &,
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LICMSafetyInfo *);
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/// \brief Computes safety information for a loop
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/// checks loop body & header for the possiblity of may throw
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/// checks loop body & header for the possibility of may throw
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/// exception, it takes LICMSafetyInfo and loop as argument.
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/// Updates safety information in LICMSafetyInfo argument.
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void computeLICMSafetyInfo(LICMSafetyInfo *, Loop *);
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@ -622,7 +622,7 @@ public:
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// ----- Various Edge iterators for the graph ----- //
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// \brief Iterator for edges. Because this graph is bidirected, we don't
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// allow modificaiton of the edges using this iterator. Additionally, the
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// allow modification of the edges using this iterator. Additionally, the
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// iterator becomes invalid if you add edges to or from the node you're
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// getting the edges of.
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struct EdgeIterator : public std::iterator<std::forward_iterator_tag,
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@ -823,7 +823,7 @@ static bool hasUsefulEdges(Instruction *Inst) {
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}
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static bool hasUsefulEdges(ConstantExpr *CE) {
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// ConstantExpr doens't have terminators, invokes, or fences, so only needs
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// ConstantExpr doesn't have terminators, invokes, or fences, so only needs
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// to check for compares.
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return CE->getOpcode() != Instruction::ICmp &&
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CE->getOpcode() != Instruction::FCmp;
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@ -1002,7 +1002,7 @@ static void hoistBeforePos(DominatorTree *DT, Instruction *InstToHoist,
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}
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/// \brief Check whether we can cheaply express the requested SCEV in terms of
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/// the available PHI SCEV by truncation and/or invertion of the step.
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/// the available PHI SCEV by truncation and/or inversion of the step.
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static bool canBeCheaplyTransformed(ScalarEvolution &SE,
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const SCEVAddRecExpr *Phi,
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const SCEVAddRecExpr *Requested,
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@ -1836,7 +1836,7 @@ bool SCEVExpander::isHighCostExpansionHelper(
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if (auto *UDivExpr = dyn_cast<SCEVUDivExpr>(S)) {
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// If the divisor is a power of two and the SCEV type fits in a native
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// integer, consider the divison cheap irrespective of whether it occurs in
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// integer, consider the division cheap irrespective of whether it occurs in
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// the user code since it can be lowered into a right shift.
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if (auto *SC = dyn_cast<SCEVConstant>(UDivExpr->getRHS()))
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if (SC->getValue()->getValue().isPowerOf2()) {
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@ -43,7 +43,7 @@ const unsigned MaxDepth = 6;
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/// Enable an experimental feature to leverage information about dominating
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/// conditions to compute known bits. The individual options below control how
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/// hard we search. The defaults are choosen to be fairly aggressive. If you
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/// hard we search. The defaults are chosen to be fairly aggressive. If you
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/// run into compile time problems when testing, scale them back and report
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/// your findings.
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static cl::opt<bool> EnableDomConditions("value-tracking-dom-conditions",
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@ -2545,7 +2545,7 @@ Value *llvm::FindInsertedValue(Value *V, ArrayRef<unsigned> idx_range,
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}
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// This insert value inserts something else than what we are looking for.
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// See if the (aggregrate) value inserted into has the value we are
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// See if the (aggregate) value inserted into has the value we are
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// looking for, then.
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if (*req_idx != *i)
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return FindInsertedValue(I->getAggregateOperand(), idx_range,
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@ -2560,7 +2560,7 @@ Value *llvm::FindInsertedValue(Value *V, ArrayRef<unsigned> idx_range,
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}
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if (ExtractValueInst *I = dyn_cast<ExtractValueInst>(V)) {
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// If we're extracting a value from an aggregrate that was extracted from
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// If we're extracting a value from an aggregate that was extracted from
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// something else, we can extract from that something else directly instead.
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// However, we will need to chain I's indices with the requested indices.
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@ -253,7 +253,7 @@ void WinCodeViewLineTables::emitDebugInfoForFunction(const Function *GV) {
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}
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FilenameSegmentLengths[LastSegmentEnd] = FI.Instrs.size() - LastSegmentEnd;
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// Emit a line table subsection, requred to do PC-to-file:line lookup.
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// Emit a line table subsection, required to do PC-to-file:line lookup.
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Asm->OutStreamer->AddComment("Line table subsection for " + Twine(FuncName));
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Asm->EmitInt32(COFF::DEBUG_LINE_TABLE_SUBSECTION);
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MCSymbol *LineTableBegin = Asm->MMI->getContext().createTempSymbol(),
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@ -1089,7 +1089,7 @@ static bool OptimizeExtractBits(BinaryOperator *ShiftI, ConstantInt *CI,
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// ScalarizeMaskedLoad() translates masked load intrinsic, like
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// <16 x i32 > @llvm.masked.load( <16 x i32>* %addr, i32 align,
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// <16 x i1> %mask, <16 x i32> %passthru)
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// to a chain of basic blocks, whith loading element one-by-one if
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// to a chain of basic blocks, with loading element one-by-one if
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// the appropriate mask bit is set
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//
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// %1 = bitcast i8* %addr to i32*
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@ -4135,7 +4135,7 @@ class VectorPromoteHelper {
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/// \brief Generate a constant vector with \p Val with the same
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/// number of elements as the transition.
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/// \p UseSplat defines whether or not \p Val should be replicated
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/// accross the whole vector.
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/// across the whole vector.
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/// In other words, if UseSplat == true, we generate <Val, Val, ..., Val>,
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/// otherwise we generate a vector with as many undef as possible:
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/// <undef, ..., undef, Val, undef, ..., undef> where \p Val is only
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@ -211,7 +211,7 @@ bool GlobalMerge::doMerge(SmallVectorImpl<GlobalVariable*> &Globals,
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// If we want to be smarter, look at all uses of each global, to try to
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// discover all sets of globals used together, and how many times each of
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// these sets occured.
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// these sets occurred.
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//
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// Keep this reasonably efficient, by having an append-only list of all sets
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// discovered so far (UsedGlobalSet), and mapping each "together-ness" unit of
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@ -327,7 +327,7 @@ namespace {
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/// \brief Following the use-def chain, get the next available source
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/// for the tracked value.
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/// \return A ValueTrackerResult containing the a set of registers
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/// \return A ValueTrackerResult containing a set of registers
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/// and sub registers with tracked values. A ValueTrackerResult with
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/// an empty set of registers means no source was found.
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ValueTrackerResult getNextSource();
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@ -1567,7 +1567,7 @@ ValueTrackerResult ValueTracker::getNextSource() {
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Res.setInst(Def);
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// If we can still move up in the use-def chain, move to the next
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// defintion.
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// definition.
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if (!TargetRegisterInfo::isPhysicalRegister(Reg) && OneRegSrc) {
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Def = MRI.getVRegDef(Reg);
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DefIdx = MRI.def_begin(Reg).getOperandNo();
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@ -1822,7 +1822,7 @@ public:
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/// Removes subranges starting at copies that get removed. This sometimes
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/// happens when undefined subranges are copied around. These ranges contain
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/// no usefull information and can be removed.
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/// no useful information and can be removed.
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void pruneSubRegValues(LiveInterval &LI, unsigned &ShrinkMask);
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/// Erase any machine instructions that have been coalesced away.
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@ -2410,7 +2410,7 @@ void JoinVals::pruneSubRegValues(LiveInterval &LI, unsigned &ShrinkMask)
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continue;
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}
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// If a subrange ends at the copy, then a value was copied but only
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// partially used later. Shrink the subregister range apropriately.
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// partially used later. Shrink the subregister range appropriately.
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if (Q.valueIn() != nullptr && Q.valueOut() == nullptr) {
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DEBUG(dbgs() << "\t\tDead uses at sublane "
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<< format("%04X", S.LaneMask) << " at " << Def << "\n");
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@ -2799,7 +2799,7 @@ bool RegisterCoalescer::applyTerminalRule(const MachineInstr &Copy) const {
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!isTerminalReg(DstReg, Copy, MRI))
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return false;
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// DstReg is a terminal node. Check if it inteferes with any other
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// DstReg is a terminal node. Check if it interferes with any other
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// copy involving SrcReg.
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const MachineBasicBlock *OrigBB = Copy.getParent();
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const LiveInterval &DstLI = LIS->getInterval(DstReg);
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@ -966,7 +966,7 @@ void RegPressureTracker::bumpDownwardPressure(const MachineInstr *MI) {
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/// This is expensive for an on-the-fly query because it calls
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/// bumpDownwardPressure to recompute the pressure sets based on current
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/// liveness. We don't yet have a fast version of downward pressure tracking
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/// analagous to getUpwardPressureDelta.
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/// analogous to getUpwardPressureDelta.
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void RegPressureTracker::
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getMaxDownwardPressureDelta(const MachineInstr *MI, RegPressureDelta &Delta,
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ArrayRef<PressureChange> CriticalPSets,
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@ -508,7 +508,7 @@ static inline bool isUnsafeMemoryObject(MachineInstr *MI,
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return false;
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}
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/// This returns true if the two MIs need a chain edge betwee them.
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/// This returns true if the two MIs need a chain edge between them.
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/// If these are not even memory operations, we still may need
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/// chain deps between them. The question really is - could
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/// these two MIs be reordered during scheduling from memory dependency
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@ -670,7 +670,7 @@ static inline void addChainDependency(AliasAnalysis *AA,
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unsigned TrueMemOrderLatency = 0,
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bool isNormalMemory = false) {
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// If this is a false dependency,
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// do not add the edge, but rememeber the rejected node.
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// do not add the edge, but remember the rejected node.
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if (MIsNeedChainEdge(AA, MFI, DL, SUa->getInstr(), SUb->getInstr())) {
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SDep Dep(SUa, isNormalMemory ? SDep::MayAliasMem : SDep::Barrier);
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Dep.setLatency(TrueMemOrderLatency);
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@ -685,7 +685,7 @@ static inline void addChainDependency(AliasAnalysis *AA,
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}
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}
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/// Create an SUnit for each real instruction, numbered in top-down toplological
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/// Create an SUnit for each real instruction, numbered in top-down topological
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/// order. The instruction order A < B, implies that no edge exists from B to A.
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///
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/// Map each real instruction to its SUnit.
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@ -766,7 +766,7 @@ void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
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// We build scheduling units by walking a block's instruction list from bottom
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// to top.
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// Remember where a generic side-effecting instruction is as we procede.
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// Remember where a generic side-effecting instruction is as we proceed.
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SUnit *BarrierChain = nullptr, *AliasChain = nullptr;
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// Memory references to specific known memory locations are tracked
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@ -49,7 +49,7 @@ ResourcePriorityQueue::ResourcePriorityQueue(SelectionDAGISel *IS)
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TII = STI.getInstrInfo();
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ResourcesModel.reset(TII->CreateTargetScheduleState(STI));
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// This hard requirement could be relaxed, but for now
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// do not let it procede.
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// do not let it proceed.
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assert(ResourcesModel && "Unimplemented CreateTargetScheduleState.");
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unsigned NumRC = TRI->getNumRegClasses();
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@ -269,12 +269,12 @@ bool ResourcePriorityQueue::isResourceAvailable(SUnit *SU) {
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}
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// Now see if there are no other dependencies
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// to instructions alredy in the packet.
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// to instructions already in the packet.
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for (unsigned i = 0, e = Packet.size(); i != e; ++i)
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for (SUnit::const_succ_iterator I = Packet[i]->Succs.begin(),
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E = Packet[i]->Succs.end(); I != E; ++I) {
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// Since we do not add pseudos to packets, might as well
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// ignor order deps.
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// ignore order deps.
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if (I->isCtrl())
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continue;
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@ -2677,7 +2677,7 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{
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const int rIndex = Items - 1 -
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cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
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// If the sign portion ends in our element the substraction gives correct
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// If the sign portion ends in our element the subtraction gives correct
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// result. Otherwise it gives either negative or > bitwidth result
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return std::max(std::min(KnownSign - rIndex * BitWidth, BitWidth), 0);
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}
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@ -3069,7 +3069,7 @@ void SelectionDAGBuilder::visitStore(const StoreInst &I) {
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void SelectionDAGBuilder::visitMaskedStore(const CallInst &I) {
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SDLoc sdl = getCurSDLoc();
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// llvm.masked.store.*(Src0, Ptr, alignemt, Mask)
|
||||
// llvm.masked.store.*(Src0, Ptr, alignment, Mask)
|
||||
Value *PtrOperand = I.getArgOperand(1);
|
||||
SDValue Ptr = getValue(PtrOperand);
|
||||
SDValue Src0 = getValue(I.getArgOperand(0));
|
||||
@ -3094,13 +3094,13 @@ void SelectionDAGBuilder::visitMaskedStore(const CallInst &I) {
|
||||
}
|
||||
|
||||
// Gather/scatter receive a vector of pointers.
|
||||
// This vector of pointers may be represented as a base pointer + vector of
|
||||
// indices, it depends on GEP and instruction preceeding GEP
|
||||
// This vector of pointers may be represented as a base pointer + vector of
|
||||
// indices, it depends on GEP and instruction preceding GEP
|
||||
// that calculates indices
|
||||
static bool getUniformBase(Value *& Ptr, SDValue& Base, SDValue& Index,
|
||||
SelectionDAGBuilder* SDB) {
|
||||
|
||||
assert (Ptr->getType()->isVectorTy() && "Uexpected pointer type");
|
||||
assert(Ptr->getType()->isVectorTy() && "Unexpected pointer type");
|
||||
GetElementPtrInst *Gep = dyn_cast<GetElementPtrInst>(Ptr);
|
||||
if (!Gep || Gep->getNumOperands() > 2)
|
||||
return false;
|
||||
|
||||
@ -105,8 +105,8 @@ StatepointLoweringState::allocateStackSlot(EVT ValueType,
|
||||
return Builder.DAG.getFrameIndex(FI, ValueType);
|
||||
}
|
||||
// Note: We deliberately choose to advance this only on the failing path.
|
||||
// Doing so on the suceeding path involes a bit of complexity that caused a
|
||||
// minor bug previously. Unless performance shows this matters, please
|
||||
// Doing so on the succeeding path involves a bit of complexity that caused
|
||||
// a minor bug previously. Unless performance shows this matters, please
|
||||
// keep this code as simple as possible.
|
||||
NextSlotToAllocate++;
|
||||
}
|
||||
@ -119,7 +119,7 @@ StatepointLoweringState::allocateStackSlot(EVT ValueType,
|
||||
static Optional<int> findPreviousSpillSlot(const Value *Val,
|
||||
SelectionDAGBuilder &Builder,
|
||||
int LookUpDepth) {
|
||||
// Can not look any futher - give up now
|
||||
// Can not look any further - give up now
|
||||
if (LookUpDepth <= 0)
|
||||
return Optional<int>();
|
||||
|
||||
@ -196,7 +196,7 @@ static Optional<int> findPreviousSpillSlot(const Value *Val,
|
||||
/// Try to find existing copies of the incoming values in stack slots used for
|
||||
/// statepoint spilling. If we can find a spill slot for the incoming value,
|
||||
/// mark that slot as allocated, and reuse the same slot for this safepoint.
|
||||
/// This helps to avoid series of loads and stores that only serve to resuffle
|
||||
/// This helps to avoid series of loads and stores that only serve to reshuffle
|
||||
/// values on the stack between calls.
|
||||
static void reservePreviousStackSlotForValue(const Value *IncomingValue,
|
||||
SelectionDAGBuilder &Builder) {
|
||||
@ -255,7 +255,7 @@ static void removeDuplicatesGCPtrs(SmallVectorImpl<const Value *> &Bases,
|
||||
SmallVectorImpl<const Value *> &Relocs,
|
||||
SelectionDAGBuilder &Builder) {
|
||||
|
||||
// This is horribly ineffecient, but I don't care right now
|
||||
// This is horribly inefficient, but I don't care right now
|
||||
SmallSet<SDValue, 64> Seen;
|
||||
|
||||
SmallVector<const Value *, 64> NewBases, NewPtrs, NewRelocs;
|
||||
@ -347,11 +347,11 @@ lowerCallFromStatepoint(ImmutableStatepoint ISP, MachineBasicBlock *LandingPad,
|
||||
if (CS.isInvoke()) {
|
||||
// Result value will be used in different basic block for invokes
|
||||
// so we need to export it now. But statepoint call has a different type
|
||||
// than the actuall call. It means that standart exporting mechanism will
|
||||
// than the actual call. It means that standard exporting mechanism will
|
||||
// create register of the wrong type. So instead we need to create
|
||||
// register with correct type and save value into it manually.
|
||||
// TODO: To eliminate this problem we can remove gc.result intrinsics
|
||||
// completelly and make statepoint call to return a tuple.
|
||||
// completely and make statepoint call to return a tuple.
|
||||
unsigned Reg = Builder.FuncInfo.CreateRegs(ISP.getActualReturnType());
|
||||
RegsForValue RFV(
|
||||
*Builder.DAG.getContext(), Builder.DAG.getTargetLoweringInfo(),
|
||||
@ -597,16 +597,17 @@ static void lowerStatepointMetaArgs(SmallVectorImpl<SDValue> &Ops,
|
||||
SpillMap[V] = cast<FrameIndexSDNode>(Loc)->getIndex();
|
||||
} else {
|
||||
// Record value as visited, but not spilled. This is case for allocas
|
||||
// and constants. For this values we can avoid emiting spill load while
|
||||
// and constants. For this values we can avoid emitting spill load while
|
||||
// visiting corresponding gc_relocate.
|
||||
// Actually we do not need to record them in this map at all.
|
||||
// We do this only to check that we are not relocating any unvisited value.
|
||||
// We do this only to check that we are not relocating any unvisited
|
||||
// value.
|
||||
SpillMap[V] = None;
|
||||
|
||||
// Default llvm mechanisms for exporting values which are used in
|
||||
// different basic blocks does not work for gc relocates.
|
||||
// Note that it would be incorrect to teach llvm that all relocates are
|
||||
// uses of the corresponging values so that it would automatically
|
||||
// uses of the corresponding values so that it would automatically
|
||||
// export them. Relocates of the spilled values does not use original
|
||||
// value.
|
||||
if (StatepointSite.getCallSite().isInvoke())
|
||||
@ -806,7 +807,7 @@ void SelectionDAGBuilder::LowerStatepoint(
|
||||
|
||||
// Replace original call
|
||||
DAG.ReplaceAllUsesWith(CallNode, SinkNode); // This may update Root
|
||||
// Remove originall call node
|
||||
// Remove original call node
|
||||
DAG.DeleteNode(CallNode);
|
||||
|
||||
// DON'T set the root - under the assumption that it's already set past the
|
||||
@ -878,7 +879,7 @@ void SelectionDAGBuilder::visitGCRelocate(const CallInst &CI) {
|
||||
|
||||
// Be conservative: flush all pending loads
|
||||
// TODO: Probably we can be less restrictive on this,
|
||||
// it may allow more scheduling opprtunities
|
||||
// it may allow more scheduling opportunities.
|
||||
SDValue Chain = getRoot();
|
||||
|
||||
SDValue SpillLoad =
|
||||
|
||||
@ -705,7 +705,7 @@ MCSymbol *TargetLoweringObjectFileMachO::getCFIPersonalitySymbol(
|
||||
const MCExpr *TargetLoweringObjectFileMachO::getIndirectSymViaGOTPCRel(
|
||||
const MCSymbol *Sym, const MCValue &MV, int64_t Offset,
|
||||
MachineModuleInfo *MMI, MCStreamer &Streamer) const {
|
||||
// Although MachO 32-bit targets do not explictly have a GOTPCREL relocation
|
||||
// Although MachO 32-bit targets do not explicitly have a GOTPCREL relocation
|
||||
// as 64-bit do, we replace the GOT equivalent by accessing the final symbol
|
||||
// through a non_lazy_ptr stub instead. One advantage is that it allows the
|
||||
// computation of deltas to final external symbols. Example:
|
||||
|
||||
@ -2146,7 +2146,7 @@ void WinEHPrepare::mapLandingPadBlocks(LandingPadInst *LPad,
|
||||
// Under some circumstances optimized IR will flow unconditionally into a
|
||||
// handler block without checking the selector. This can only happen if
|
||||
// the landing pad has a catch-all handler and the handler for the
|
||||
// preceeding catch clause is identical to the catch-call handler
|
||||
// preceding catch clause is identical to the catch-call handler
|
||||
// (typically an empty catch). In this case, the handler must be shared
|
||||
// by all remaining clauses.
|
||||
if (isa<ConstantPointerNull>(
|
||||
|
||||
@ -705,8 +705,8 @@ DWARFContextInMemory::DWARFContextInMemory(const object::ObjectFile &Obj,
|
||||
// (Address of Section in File) +
|
||||
// (Load Address of Section)
|
||||
if (L != nullptr && RSec != Obj.section_end()) {
|
||||
// RSec is now either the section being targetted or the section
|
||||
// containing the symbol being targetted. In either case,
|
||||
// RSec is now either the section being targeted or the section
|
||||
// containing the symbol being targeted. In either case,
|
||||
// we need to perform the same computation.
|
||||
StringRef SecName;
|
||||
RSec->getName(SecName);
|
||||
|
||||
@ -1476,11 +1476,11 @@ relocation_iterator RuntimeDyldELF::processRelocationRef(
|
||||
// These relocations are supposed to subtract the TOC address from
|
||||
// the final value. This does not fit cleanly into the RuntimeDyld
|
||||
// scheme, since there may be *two* sections involved in determining
|
||||
// the relocation value (the section of the symbol refered to by the
|
||||
// the relocation value (the section of the symbol referred to by the
|
||||
// relocation, and the TOC section associated with the current module).
|
||||
//
|
||||
// Fortunately, these relocations are currently only ever generated
|
||||
// refering to symbols that themselves reside in the TOC, which means
|
||||
// referring to symbols that themselves reside in the TOC, which means
|
||||
// that the two sections are actually the same. Thus they cancel out
|
||||
// and we can immediately resolve the relocation right now.
|
||||
switch (RelType) {
|
||||
|
||||
@ -3327,7 +3327,7 @@ void Value::print(raw_ostream &ROS, ModuleSlotTracker &MST) const {
|
||||
|
||||
/// Print without a type, skipping the TypePrinting object.
|
||||
///
|
||||
/// \return \c true iff printing was succesful.
|
||||
/// \return \c true iff printing was successful.
|
||||
static bool printWithoutType(const Value &V, raw_ostream &O,
|
||||
SlotTracker *Machine, const Module *M) {
|
||||
if (V.hasName() || isa<GlobalValue>(V) ||
|
||||
|
||||
@ -134,7 +134,7 @@ void MCELFStreamer::EmitAssemblerFlag(MCAssemblerFlag Flag) {
|
||||
llvm_unreachable("invalid assembler flag!");
|
||||
}
|
||||
|
||||
// If bundle aligment is used and there are any instructions in the section, it
|
||||
// If bundle alignment is used and there are any instructions in the section, it
|
||||
// needs to be aligned to at least the bundle size.
|
||||
static void setSectionAlignmentForBundling(const MCAssembler &Assembler,
|
||||
MCSection *Section) {
|
||||
@ -603,7 +603,7 @@ void MCELFStreamer::EmitBundleUnlock() {
|
||||
report_fatal_error("Empty bundle-locked group is forbidden");
|
||||
|
||||
// When the -mc-relax-all flag is used, we emit instructions to fragments
|
||||
// stored on a stack. When the bundle unlock is emited, we pop a fragment
|
||||
// stored on a stack. When the bundle unlock is emitted, we pop a fragment
|
||||
// from the stack a merge it to the one below.
|
||||
if (getAssembler().getRelaxAll()) {
|
||||
assert(!BundleGroups.empty() && "There are no bundle groups");
|
||||
|
||||
@ -216,8 +216,8 @@ AArch64A53Fix835769::runOnBasicBlock(MachineBasicBlock &MBB) {
|
||||
++Idx;
|
||||
}
|
||||
|
||||
DEBUG(dbgs() << "Scan complete, "<< Sequences.size()
|
||||
<< " occurences of pattern found.\n");
|
||||
DEBUG(dbgs() << "Scan complete, " << Sequences.size()
|
||||
<< " occurrences of pattern found.\n");
|
||||
|
||||
// Then update the basic block, inserting nops between the detected sequences.
|
||||
for (auto &MI : Sequences) {
|
||||
|
||||
@ -969,7 +969,7 @@ bool AArch64FastISel::simplifyAddress(Address &Addr, MVT VT) {
|
||||
|
||||
// Cannot encode an offset register and an immediate offset in the same
|
||||
// instruction. Fold the immediate offset into the load/store instruction and
|
||||
// emit an additonal add to take care of the offset register.
|
||||
// emit an additional add to take care of the offset register.
|
||||
if (!ImmediateOffsetNeedsLowering && Addr.getOffset() && Addr.getOffsetReg())
|
||||
RegisterOffsetNeedsLowering = true;
|
||||
|
||||
|
||||
@ -72,9 +72,9 @@
|
||||
//
|
||||
// For most functions, some of the frame areas are empty. For those functions,
|
||||
// it may not be necessary to set up fp or bp:
|
||||
// * A base pointer is definitly needed when there are both VLAs and local
|
||||
// * A base pointer is definitely needed when there are both VLAs and local
|
||||
// variables with more-than-default alignment requirements.
|
||||
// * A frame pointer is definitly needed when there are local variables with
|
||||
// * A frame pointer is definitely needed when there are local variables with
|
||||
// more-than-default alignment requirements.
|
||||
//
|
||||
// In some cases when a base pointer is not strictly needed, it is generated
|
||||
|
||||
@ -1466,7 +1466,7 @@ static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
|
||||
// cmn w0, #1
|
||||
// Fundamental, we're relying on the property that (zext LHS) == (zext RHS)
|
||||
// if and only if (sext LHS) == (sext RHS). The checks are in place to
|
||||
// ensure both the LHS and RHS are truely zero extended and to make sure the
|
||||
// ensure both the LHS and RHS are truly zero extended and to make sure the
|
||||
// transformation is profitable.
|
||||
if ((RHSC->getZExtValue() >> 16 == 0) && isa<LoadSDNode>(LHS) &&
|
||||
cast<LoadSDNode>(LHS)->getExtensionType() == ISD::ZEXTLOAD &&
|
||||
@ -8385,7 +8385,7 @@ static SDValue replaceSplatVectorStore(SelectionDAG &DAG, StoreSDNode *St) {
|
||||
unsigned Alignment = std::min(OrigAlignment, EltOffset);
|
||||
|
||||
// Create scalar stores. This is at least as good as the code sequence for a
|
||||
// split unaligned store wich is a dup.s, ext.b, and two stores.
|
||||
// split unaligned store which is a dup.s, ext.b, and two stores.
|
||||
// Most of the time the three stores should be replaced by store pair
|
||||
// instructions (stp).
|
||||
SDLoc DL(St);
|
||||
|
||||
@ -42,7 +42,7 @@
|
||||
/// ENDIF
|
||||
/// %use
|
||||
///
|
||||
/// Adding this use will make the def live thoughout the IF branch, which is
|
||||
/// Adding this use will make the def live throughout the IF branch, which is
|
||||
/// what we want.
|
||||
|
||||
#include "AMDGPU.h"
|
||||
@ -138,7 +138,7 @@ bool SIFixSGPRLiveRanges::runOnMachineFunction(MachineFunction &MF) {
|
||||
if (MBB.succ_size() < 2)
|
||||
continue;
|
||||
|
||||
// We have structured control flow, so number of succesors should be two.
|
||||
// We have structured control flow, so number of successors should be two.
|
||||
assert(MBB.succ_size() == 2);
|
||||
MachineBasicBlock *SuccA = *MBB.succ_begin();
|
||||
MachineBasicBlock *SuccB = *(++MBB.succ_begin());
|
||||
|
||||
@ -548,7 +548,7 @@ SDValue SITargetLowering::LowerFormalArguments(
|
||||
assert((PSInputNum <= 15) && "Too many PS inputs!");
|
||||
|
||||
if (!Arg.Used) {
|
||||
// We can savely skip PS inputs
|
||||
// We can safely skip PS inputs
|
||||
Skipped.set(i);
|
||||
++PSInputNum;
|
||||
continue;
|
||||
@ -565,7 +565,7 @@ SDValue SITargetLowering::LowerFormalArguments(
|
||||
|
||||
// We REALLY want the ORIGINAL number of vertex elements here, e.g. a
|
||||
// three or five element vertex only needs three or five registers,
|
||||
// NOT four or eigth.
|
||||
// NOT four or eight.
|
||||
Type *ParamType = FType->getParamType(Arg.getOrigArgIndex());
|
||||
unsigned NumElements = ParamType->getVectorNumElements();
|
||||
|
||||
@ -2248,9 +2248,9 @@ MachineSDNode *SITargetLowering::wrapAddr64Rsrc(SelectionDAG &DAG,
|
||||
}
|
||||
|
||||
/// \brief Return a resource descriptor with the 'Add TID' bit enabled
|
||||
/// The TID (Thread ID) is multipled by the stride value (bits [61:48]
|
||||
/// of the resource descriptor) to create an offset, which is added to the
|
||||
/// resource ponter.
|
||||
/// The TID (Thread ID) is multiplied by the stride value (bits [61:48]
|
||||
/// of the resource descriptor) to create an offset, which is added to
|
||||
/// the resource pointer.
|
||||
MachineSDNode *SITargetLowering::buildRSRC(SelectionDAG &DAG,
|
||||
SDLoc DL,
|
||||
SDValue Ptr,
|
||||
|
||||
@ -261,7 +261,7 @@ void SIInsertWaits::pushInstruction(MachineBasicBlock &MBB,
|
||||
|
||||
if (MBB.getParent()->getSubtarget<AMDGPUSubtarget>().getGeneration() >=
|
||||
AMDGPUSubtarget::VOLCANIC_ISLANDS) {
|
||||
// Any occurence of consecutive VMEM or SMEM instructions forms a VMEM
|
||||
// Any occurrence of consecutive VMEM or SMEM instructions forms a VMEM
|
||||
// or SMEM clause, respectively.
|
||||
//
|
||||
// The temporary workaround is to break the clauses with S_NOP.
|
||||
|
||||
@ -1088,7 +1088,7 @@ bool SIInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa,
|
||||
|
||||
// TODO: Should we check the address space from the MachineMemOperand? That
|
||||
// would allow us to distinguish objects we know don't alias based on the
|
||||
// underlying addres space, even if it was lowered to a different one,
|
||||
// underlying address space, even if it was lowered to a different one,
|
||||
// e.g. private accesses lowered to use MUBUF instructions on a scratch
|
||||
// buffer.
|
||||
if (isDS(Opc0)) {
|
||||
|
||||
@ -2058,7 +2058,7 @@ bool ARMConstantIslands::preserveBaseRegister(MachineInstr *JumpMI,
|
||||
/// \brief Returns whether CPEMI is the first instruction in the block
|
||||
/// immediately following JTMI (assumed to be a TBB or TBH terminator). If so,
|
||||
/// we can switch the first register to PC and usually remove the address
|
||||
/// calculation that preceeded it.
|
||||
/// calculation that preceded it.
|
||||
static bool jumpTableFollowsTB(MachineInstr *JTMI, MachineInstr *CPEMI) {
|
||||
MachineFunction::iterator MBB = JTMI->getParent();
|
||||
MachineFunction *MF = MBB->getParent();
|
||||
|
||||
@ -609,7 +609,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
|
||||
setTargetDAGCombine(ISD::ADDC);
|
||||
|
||||
if (Subtarget->isFPOnlySP()) {
|
||||
// When targetting a floating-point unit with only single-precision
|
||||
// When targeting a floating-point unit with only single-precision
|
||||
// operations, f64 is legal for the few double-precision instructions which
|
||||
// are present However, no double-precision operations other than moves,
|
||||
// loads and stores are provided by the hardware.
|
||||
@ -11597,7 +11597,7 @@ bool ARMTargetLowering::canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
|
||||
return false;
|
||||
|
||||
// Floating point values and vector values map to the same register file.
|
||||
// Therefore, althought we could do a store extract of a vector type, this is
|
||||
// Therefore, although we could do a store extract of a vector type, this is
|
||||
// better to leave at float as we have more freedom in the addressing mode for
|
||||
// those.
|
||||
if (VectorTy->isFPOrFPVectorTy())
|
||||
|
||||
@ -250,7 +250,7 @@ Register HexagonGenPredicate::getPredRegFor(const Register &Reg) {
|
||||
unsigned NewPR = MRI->createVirtualRegister(PredRC);
|
||||
|
||||
// For convertible instructions, do not modify them, so that they can
|
||||
// be coverted later. Generate a copy from Reg to NewPR.
|
||||
// be converted later. Generate a copy from Reg to NewPR.
|
||||
if (isConvertibleToPredForm(DefI)) {
|
||||
MachineBasicBlock::iterator DefIt = DefI;
|
||||
BuildMI(B, std::next(DefIt), DL, TII->get(TargetOpcode::COPY), NewPR)
|
||||
|
||||
@ -727,9 +727,9 @@ CountValue *HexagonHardwareLoops::computeCount(MachineLoop *Loop,
|
||||
// Phis that may feed into the loop.
|
||||
LoopFeederMap LoopFeederPhi;
|
||||
|
||||
// Check if the inital value may be zero and can be decremented in the first
|
||||
// Check if the initial value may be zero and can be decremented in the first
|
||||
// iteration. If the value is zero, the endloop instruction will not decrement
|
||||
// the loop counter, so we shoudn't generate a hardware loop in this case.
|
||||
// the loop counter, so we shouldn't generate a hardware loop in this case.
|
||||
if (loopCountMayWrapOrUnderFlow(Start, End, Loop->getLoopPreheader(), Loop,
|
||||
LoopFeederPhi))
|
||||
return nullptr;
|
||||
@ -1440,7 +1440,7 @@ bool HexagonHardwareLoops::loopCountMayWrapOrUnderFlow(
|
||||
if (Comparison::isSigned(Cmp))
|
||||
return false;
|
||||
|
||||
// Check if there is a comparison of the inital value. If the initial value
|
||||
// Check if there is a comparison of the initial value. If the initial value
|
||||
// is greater than or not equal to another value, then assume this is a
|
||||
// range check.
|
||||
if ((Cmp & Comparison::G) || Cmp == Comparison::NE)
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
//===-- MSP430MachineFucntionInfo.cpp - MSP430 machine function info ------===//
|
||||
//===-- MSP430MachineFunctionInfo.cpp - MSP430 machine function info ------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
||||
@ -3023,7 +3023,7 @@ MipsTargetLowering::LowerFormalArguments(SDValue Chain,
|
||||
// We ought to be able to use LocVT directly but O32 sets it to i32
|
||||
// when allocating floating point values to integer registers.
|
||||
// This shouldn't influence how we load the value into registers unless
|
||||
// we are targetting softfloat.
|
||||
// we are targeting softfloat.
|
||||
if (VA.getValVT().isFloatingPoint() && !Subtarget.useSoftFloat())
|
||||
LocVT = VA.getValVT();
|
||||
}
|
||||
|
||||
@ -98,7 +98,7 @@ private:
|
||||
/// This reordering exposes to optimizeMemoryInstruction more
|
||||
/// optimization opportunities on loads and stores.
|
||||
///
|
||||
/// If this function succesfully hoists an eliminable addrspacecast or V is
|
||||
/// If this function successfully hoists an eliminable addrspacecast or V is
|
||||
/// already such an addrspacecast, it returns the transformed value (which is
|
||||
/// guaranteed to be an addrspacecast); otherwise, it returns nullptr.
|
||||
Value *hoistAddrSpaceCastFrom(Value *V, int Depth = 0);
|
||||
|
||||
@ -81,7 +81,7 @@ bool NVPTXLowerAlloca::runOnBasicBlock(BasicBlock &BB) {
|
||||
// Check Load, Store, GEP, and BitCast Uses on alloca and make them
|
||||
// use the converted generic address, in order to expose non-generic
|
||||
// addrspacecast to NVPTXFavorNonGenericAddrSpace. For other types
|
||||
// of instructions this is unecessary and may introduce redudant
|
||||
// of instructions this is unnecessary and may introduce redundant
|
||||
// address cast.
|
||||
const auto &AllocaUse = *UI++;
|
||||
auto LI = dyn_cast<LoadInst>(AllocaUse.getUser());
|
||||
|
||||
@ -138,7 +138,7 @@ INITIALIZE_PASS(NVPTXLowerKernelArgs, "nvptx-lower-kernel-args",
|
||||
//
|
||||
// The above code allocates some space in the stack and copies the incoming
|
||||
// struct from param space to local space.
|
||||
// Then replace all occurences of %d by %temp.
|
||||
// Then replace all occurrences of %d by %temp.
|
||||
// =============================================================================
|
||||
void NVPTXLowerKernelArgs::handleByValParam(Argument *Arg) {
|
||||
Function *Func = Arg->getParent();
|
||||
|
||||
@ -1028,7 +1028,7 @@ class BitPermutationSelector {
|
||||
BitGroups[BitGroups.size()-1].EndIdx == Bits.size()-1 &&
|
||||
BitGroups[0].V == BitGroups[BitGroups.size()-1].V &&
|
||||
BitGroups[0].RLAmt == BitGroups[BitGroups.size()-1].RLAmt) {
|
||||
DEBUG(dbgs() << "\tcombining final bit group with inital one\n");
|
||||
DEBUG(dbgs() << "\tcombining final bit group with initial one\n");
|
||||
BitGroups[BitGroups.size()-1].EndIdx = BitGroups[0].EndIdx;
|
||||
BitGroups.erase(BitGroups.begin());
|
||||
}
|
||||
|
||||
@ -15308,11 +15308,11 @@ static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
|
||||
|
||||
/// \brief Creates an SDNode for a predicated scalar operation.
|
||||
/// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
|
||||
/// The mask is comming as MVT::i8 and it should be truncated
|
||||
/// The mask is coming as MVT::i8 and it should be truncated
|
||||
/// to MVT::i1 while lowering masking intrinsics.
|
||||
/// The main difference between ScalarMaskingNode and VectorMaskingNode is using
|
||||
/// "X86select" instead of "vselect". We just can't create the "vselect" node for
|
||||
/// a scalar instruction.
|
||||
/// "X86select" instead of "vselect". We just can't create the "vselect" node
|
||||
/// for a scalar instruction.
|
||||
static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
|
||||
SDValue PreservedSrc,
|
||||
const X86Subtarget *Subtarget,
|
||||
@ -15454,7 +15454,7 @@ static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget
|
||||
SDValue Src0 = Op.getOperand(3);
|
||||
SDValue Mask = Op.getOperand(4);
|
||||
// There are 2 kinds of intrinsics in this group:
|
||||
// (1) With supress-all-exceptions (sae) or rounding mode- 6 operands
|
||||
// (1) With suppress-all-exceptions (sae) or rounding mode- 6 operands
|
||||
// (2) With rounding mode and sae - 7 operands.
|
||||
if (Op.getNumOperands() == 6) {
|
||||
SDValue Sae = Op.getOperand(5);
|
||||
@ -18069,7 +18069,7 @@ X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
|
||||
// lowered to just a load without a fence. A mfence flushes the store buffer,
|
||||
// making the optimization clearly correct.
|
||||
// FIXME: it is required if isAtLeastRelease(Order) but it is not clear
|
||||
// otherwise, we might be able to be more agressive on relaxed idempotent
|
||||
// otherwise, we might be able to be more aggressive on relaxed idempotent
|
||||
// rmw. In practice, they do not look useful, so we don't try to be
|
||||
// especially clever.
|
||||
if (SynchScope == SingleThread)
|
||||
@ -25690,7 +25690,7 @@ static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
|
||||
}
|
||||
|
||||
// Check if we can bypass extracting and re-inserting an element of an input
|
||||
// vector. Essentialy:
|
||||
// vector. Essentially:
|
||||
// (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
|
||||
if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
|
||||
V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
|
||||
|
||||
@ -519,7 +519,7 @@ static Value *tryFactorization(InstCombiner::BuilderTy *Builder,
|
||||
if (isa<OverflowingBinaryOperator>(Op1))
|
||||
HasNSW &= Op1->hasNoSignedWrap();
|
||||
|
||||
// We can propogate 'nsw' if we know that
|
||||
// We can propagate 'nsw' if we know that
|
||||
// %Y = mul nsw i16 %X, C
|
||||
// %Z = add nsw i16 %Y, %X
|
||||
// =>
|
||||
|
||||
@ -482,7 +482,7 @@ namespace {
|
||||
/// A flag indicating whether this optimization pass should run.
|
||||
bool Run;
|
||||
|
||||
/// Flags which determine whether each of the interesting runtine functions
|
||||
/// Flags which determine whether each of the interesting runtime functions
|
||||
/// is in fact used in the current function.
|
||||
unsigned UsedInThisFunction;
|
||||
|
||||
@ -1264,7 +1264,7 @@ ObjCARCOpt::VisitInstructionTopDown(Instruction *Inst,
|
||||
Arg = GetArgRCIdentityRoot(Inst);
|
||||
TopDownPtrState &S = MyStates.getPtrTopDownState(Arg);
|
||||
NestingDetected |= S.InitTopDown(Class, Inst);
|
||||
// A retain can be a potential use; procede to the generic checking
|
||||
// A retain can be a potential use; proceed to the generic checking
|
||||
// code below.
|
||||
break;
|
||||
}
|
||||
|
||||
@ -96,7 +96,7 @@ struct RRInfo {
|
||||
};
|
||||
|
||||
/// \brief This class summarizes several per-pointer runtime properties which
|
||||
/// are propogated through the flow graph.
|
||||
/// are propagated through the flow graph.
|
||||
class PtrState {
|
||||
protected:
|
||||
/// True if the reference count is known to be incremented.
|
||||
@ -172,7 +172,7 @@ struct BottomUpPtrState : PtrState {
|
||||
bool InitBottomUp(ARCMDKindCache &Cache, Instruction *I);
|
||||
|
||||
/// Return true if this set of releases can be paired with a release. Modifies
|
||||
/// state appropriately to reflect that the matching occured if it is
|
||||
/// state appropriately to reflect that the matching occurred if it is
|
||||
/// successful.
|
||||
///
|
||||
/// It is assumed that one has already checked that the RCIdentity of the
|
||||
@ -194,7 +194,7 @@ struct TopDownPtrState : PtrState {
|
||||
|
||||
/// Return true if this set of retains can be paired with the given
|
||||
/// release. Modifies state appropriately to reflect that the matching
|
||||
/// occured.
|
||||
/// occurred.
|
||||
bool MatchWithRelease(ARCMDKindCache &Cache, Instruction *Release);
|
||||
|
||||
void HandlePotentialUse(Instruction *Inst, const Value *Ptr,
|
||||
|
||||
@ -1771,7 +1771,7 @@ static void patchReplacementInstruction(Instruction *I, Value *Repl) {
|
||||
if (Instruction *ReplInst = dyn_cast<Instruction>(Repl)) {
|
||||
// FIXME: If both the original and replacement value are part of the
|
||||
// same control-flow region (meaning that the execution of one
|
||||
// guarentees the executation of the other), then we can combine the
|
||||
// guarantees the execution of the other), then we can combine the
|
||||
// noalias scopes here and do better than the general conservative
|
||||
// answer used in combineMetadata().
|
||||
|
||||
@ -2766,7 +2766,7 @@ void GVN::addDeadBlock(BasicBlock *BB) {
|
||||
// R be the target of the dead out-coming edge.
|
||||
// 1) Identify the set of dead blocks implied by the branch's dead outcoming
|
||||
// edge. The result of this step will be {X| X is dominated by R}
|
||||
// 2) Identify those blocks which haves at least one dead prodecessor. The
|
||||
// 2) Identify those blocks which haves at least one dead predecessor. The
|
||||
// result of this step will be dominance-frontier(R).
|
||||
// 3) Update the PHIs in DF(R) by replacing the operands corresponding to
|
||||
// dead blocks with "UndefVal" in an hope these PHIs will optimized away.
|
||||
|
||||
@ -402,7 +402,7 @@ bool llvm::hoistRegion(DomTreeNode *N, AliasAnalysis *AA, LoopInfo *LI,
|
||||
}
|
||||
|
||||
/// Computes loop safety information, checks loop body & header
|
||||
/// for the possiblity of may throw exception.
|
||||
/// for the possibility of may throw exception.
|
||||
///
|
||||
void llvm::computeLICMSafetyInfo(LICMSafetyInfo * SafetyInfo, Loop * CurLoop) {
|
||||
assert(CurLoop != nullptr && "CurLoop cant be null");
|
||||
@ -410,7 +410,7 @@ void llvm::computeLICMSafetyInfo(LICMSafetyInfo * SafetyInfo, Loop * CurLoop) {
|
||||
// Setting default safety values.
|
||||
SafetyInfo->MayThrow = false;
|
||||
SafetyInfo->HeaderMayThrow = false;
|
||||
// Iterate over header and compute dafety info.
|
||||
// Iterate over header and compute safety info.
|
||||
for (BasicBlock::iterator I = Header->begin(), E = Header->end();
|
||||
(I != E) && !SafetyInfo->HeaderMayThrow; ++I)
|
||||
SafetyInfo->HeaderMayThrow |= I->mayThrow();
|
||||
|
||||
@ -489,7 +489,7 @@ struct LoopInterchange : public FunctionPass {
|
||||
|
||||
unsigned selectLoopForInterchange(LoopVector LoopList) {
|
||||
// TODO: Add a better heuristic to select the loop to be interchanged based
|
||||
// on the dependece matrix. Currently we select the innermost loop.
|
||||
// on the dependence matrix. Currently we select the innermost loop.
|
||||
return LoopList.size() - 1;
|
||||
}
|
||||
|
||||
@ -544,7 +544,7 @@ struct LoopInterchange : public FunctionPass {
|
||||
}
|
||||
|
||||
unsigned SelecLoopId = selectLoopForInterchange(LoopList);
|
||||
// Move the selected loop outwards to the best posible position.
|
||||
// Move the selected loop outwards to the best possible position.
|
||||
for (unsigned i = SelecLoopId; i > 0; i--) {
|
||||
bool Interchanged =
|
||||
processLoop(LoopList, i, i - 1, LoopNestExit, DependencyMatrix);
|
||||
@ -655,7 +655,7 @@ bool LoopInterchangeLegality::tightlyNested(Loop *OuterLoop, Loop *InnerLoop) {
|
||||
|
||||
DEBUG(dbgs() << "Checking instructions in Loop header and Loop latch \n");
|
||||
// We do not have any basic block in between now make sure the outer header
|
||||
// and outer loop latch doesnt contain any unsafe instructions.
|
||||
// and outer loop latch doesn't contain any unsafe instructions.
|
||||
if (containsUnsafeInstructionsInHeader(OuterLoopHeader) ||
|
||||
containsUnsafeInstructionsInLatch(OuterLoopLatch))
|
||||
return false;
|
||||
@ -836,7 +836,7 @@ bool LoopInterchangeLegality::currentLimitations() {
|
||||
else
|
||||
FoundInduction = true;
|
||||
}
|
||||
// The loop latch ended and we didnt find the induction variable return as
|
||||
// The loop latch ended and we didn't find the induction variable return as
|
||||
// current limitation.
|
||||
if (!FoundInduction)
|
||||
return true;
|
||||
@ -966,7 +966,7 @@ bool LoopInterchangeProfitability::isProfitable(unsigned InnerLoopId,
|
||||
unsigned OuterLoopId,
|
||||
CharMatrix &DepMatrix) {
|
||||
|
||||
// TODO: Add Better Profitibility checks.
|
||||
// TODO: Add better profitability checks.
|
||||
// e.g
|
||||
// 1) Construct dependency matrix and move the one with no loop carried dep
|
||||
// inside to enable vectorization.
|
||||
@ -980,7 +980,7 @@ bool LoopInterchangeProfitability::isProfitable(unsigned InnerLoopId,
|
||||
if (Cost < 0)
|
||||
return true;
|
||||
|
||||
// It is not profitable as per current cache profitibility model. But check if
|
||||
// It is not profitable as per current cache profitability model. But check if
|
||||
// we can move this loop outside to improve parallelism.
|
||||
bool ImprovesPar =
|
||||
isProfitabileForVectorization(InnerLoopId, OuterLoopId, DepMatrix);
|
||||
@ -1045,7 +1045,7 @@ bool LoopInterchangeTransform::transform() {
|
||||
splitInnerLoopLatch(InnerIndexVar);
|
||||
DEBUG(dbgs() << "splitInnerLoopLatch Done\n");
|
||||
|
||||
// Splits the inner loops phi nodes out into a seperate basic block.
|
||||
// Splits the inner loops phi nodes out into a separate basic block.
|
||||
splitInnerLoopHeader();
|
||||
DEBUG(dbgs() << "splitInnerLoopHeader Done\n");
|
||||
}
|
||||
@ -1181,8 +1181,8 @@ bool LoopInterchangeTransform::adjustLoopBranches() {
|
||||
|
||||
if (!OuterLoopPredecessorBI || !InnerLoopLatchPredecessorBI)
|
||||
return false;
|
||||
BasicBlock *InnerLoopHeaderSucessor = InnerLoopHeader->getUniqueSuccessor();
|
||||
if (!InnerLoopHeaderSucessor)
|
||||
BasicBlock *InnerLoopHeaderSuccessor = InnerLoopHeader->getUniqueSuccessor();
|
||||
if (!InnerLoopHeaderSuccessor)
|
||||
return false;
|
||||
|
||||
// Adjust Loop Preheader and headers
|
||||
@ -1198,11 +1198,11 @@ bool LoopInterchangeTransform::adjustLoopBranches() {
|
||||
if (OuterLoopHeaderBI->getSuccessor(i) == OuterLoopLatch)
|
||||
OuterLoopHeaderBI->setSuccessor(i, LoopExit);
|
||||
else if (OuterLoopHeaderBI->getSuccessor(i) == InnerLoopPreHeader)
|
||||
OuterLoopHeaderBI->setSuccessor(i, InnerLoopHeaderSucessor);
|
||||
OuterLoopHeaderBI->setSuccessor(i, InnerLoopHeaderSuccessor);
|
||||
}
|
||||
|
||||
// Adjust reduction PHI's now that the incoming block has changed.
|
||||
updateIncomingBlock(InnerLoopHeaderSucessor, InnerLoopHeader,
|
||||
updateIncomingBlock(InnerLoopHeaderSuccessor, InnerLoopHeader,
|
||||
OuterLoopHeader);
|
||||
|
||||
BranchInst::Create(OuterLoopPreHeader, InnerLoopHeaderBI);
|
||||
|
||||
@ -373,7 +373,7 @@ private:
|
||||
|
||||
/// Try to simplify binary operator I.
|
||||
///
|
||||
/// TODO: Probaly it's worth to hoist the code for estimating the
|
||||
/// TODO: Probably it's worth to hoist the code for estimating the
|
||||
/// simplifications effects to a separate class, since we have a very similar
|
||||
/// code in InlineCost already.
|
||||
bool visitBinaryOperator(BinaryOperator &I) {
|
||||
@ -851,7 +851,7 @@ unsigned LoopUnroll::selectUnrollCount(
|
||||
unsigned Count = UserCount ? CurrentCount : 0;
|
||||
|
||||
// If there is no user-specified count, unroll pragmas have the next
|
||||
// highest precendence.
|
||||
// highest precedence.
|
||||
if (Count == 0) {
|
||||
if (PragmaCount) {
|
||||
Count = PragmaCount;
|
||||
|
||||
@ -27,7 +27,7 @@
|
||||
// well defined state for inspection by the collector. In the current
|
||||
// implementation, this is done via the insertion of poll sites at method entry
|
||||
// and the backedge of most loops. We try to avoid inserting more polls than
|
||||
// are neccessary to ensure a finite period between poll sites. This is not
|
||||
// are necessary to ensure a finite period between poll sites. This is not
|
||||
// because the poll itself is expensive in the generated code; it's not. Polls
|
||||
// do tend to impact the optimizer itself in negative ways; we'd like to avoid
|
||||
// perturbing the optimization of the method as much as we can.
|
||||
@ -91,7 +91,7 @@ STATISTIC(FiniteExecution, "Number of loops w/o safepoints finite execution");
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
// Ignore oppurtunities to avoid placing safepoints on backedges, useful for
|
||||
// Ignore opportunities to avoid placing safepoints on backedges, useful for
|
||||
// validation
|
||||
static cl::opt<bool> AllBackedges("spp-all-backedges", cl::Hidden,
|
||||
cl::init(false));
|
||||
@ -121,7 +121,7 @@ struct PlaceBackedgeSafepointsImpl : public FunctionPass {
|
||||
std::vector<TerminatorInst *> PollLocations;
|
||||
|
||||
/// True unless we're running spp-no-calls in which case we need to disable
|
||||
/// the call dependend placement opts.
|
||||
/// the call-dependent placement opts.
|
||||
bool CallSafepointsEnabled;
|
||||
|
||||
ScalarEvolution *SE = nullptr;
|
||||
@ -220,7 +220,7 @@ static bool containsUnconditionalCallSafepoint(Loop *L, BasicBlock *Header,
|
||||
// For the moment, we look only for the 'cuts' that consist of a single call
|
||||
// instruction in a block which is dominated by the Header and dominates the
|
||||
// loop latch (Pred) block. Somewhat surprisingly, walking the entire chain
|
||||
// of such dominating blocks gets substaintially more occurences than just
|
||||
// of such dominating blocks gets substantially more occurrences than just
|
||||
// checking the Pred and Header blocks themselves. This may be due to the
|
||||
// density of loop exit conditions caused by range and null checks.
|
||||
// TODO: structure this as an analysis pass, cache the result for subloops,
|
||||
@ -765,7 +765,7 @@ static bool isGCLeafFunction(const CallSite &CS) {
|
||||
// Most LLVM intrinsics are things which can never take a safepoint.
|
||||
// As a result, we don't need to have the stack parsable at the
|
||||
// callsite. This is a highly useful optimization since intrinsic
|
||||
// calls are fairly prevelent, particularly in debug builds.
|
||||
// calls are fairly prevalent, particularly in debug builds.
|
||||
return true;
|
||||
}
|
||||
|
||||
@ -933,7 +933,7 @@ static Value *ReplaceWithStatepoint(const CallSite &CS, /* to replace */
|
||||
|
||||
Token = Call;
|
||||
|
||||
// Put the following gc_result and gc_relocate calls immediately after the
|
||||
// Put the following gc_result and gc_relocate calls immediately after
|
||||
// the old call (which we're about to delete).
|
||||
assert(ToReplace->getNextNode() && "not a terminator, must have next");
|
||||
Builder.SetInsertPoint(ToReplace->getNextNode());
|
||||
@ -962,7 +962,7 @@ static Value *ReplaceWithStatepoint(const CallSite &CS, /* to replace */
|
||||
// We'll insert the gc.result into the normal block
|
||||
BasicBlock *NormalDest = ToReplace->getNormalDest();
|
||||
// Can not insert gc.result in case of phi nodes preset.
|
||||
// Should have removed this cases prior to runnning this function
|
||||
// Should have removed this cases prior to running this function
|
||||
assert(!isa<PHINode>(NormalDest->begin()));
|
||||
Instruction *IP = &*(NormalDest->getFirstInsertionPt());
|
||||
Builder.SetInsertPoint(IP);
|
||||
|
||||
@ -164,7 +164,7 @@ typedef DenseSet<llvm::Value *> StatepointLiveSetTy;
|
||||
typedef DenseMap<Instruction *, Value *> RematerializedValueMapTy;
|
||||
|
||||
struct PartiallyConstructedSafepointRecord {
|
||||
/// The set of values known to be live accross this safepoint
|
||||
/// The set of values known to be live across this safepoint
|
||||
StatepointLiveSetTy liveset;
|
||||
|
||||
/// Mapping from live pointers to a base-defining-value
|
||||
@ -274,7 +274,7 @@ static void analyzeParsePointLiveness(
|
||||
|
||||
if (PrintLiveSet) {
|
||||
// Note: This output is used by several of the test cases
|
||||
// The order of elemtns in a set is not stable, put them in a vec and sort
|
||||
// The order of elements in a set is not stable, put them in a vec and sort
|
||||
// by name
|
||||
SmallVector<Value *, 64> temp;
|
||||
temp.insert(temp.end(), liveset.begin(), liveset.end());
|
||||
@ -509,7 +509,7 @@ static Value *findBaseDefiningValue(Value *I) {
|
||||
return I;
|
||||
|
||||
// I have absolutely no idea how to implement this part yet. It's not
|
||||
// neccessarily hard, I just haven't really looked at it yet.
|
||||
// necessarily hard, I just haven't really looked at it yet.
|
||||
assert(!isa<LandingPadInst>(I) && "Landing Pad is unimplemented");
|
||||
|
||||
if (isa<AtomicCmpXchgInst>(I))
|
||||
@ -533,7 +533,7 @@ static Value *findBaseDefiningValue(Value *I) {
|
||||
"Base pointer for a struct is meaningless");
|
||||
|
||||
// The last two cases here don't return a base pointer. Instead, they
|
||||
// return a value which dynamically selects from amoung several base
|
||||
// return a value which dynamically selects from among several base
|
||||
// derived pointers (each with it's own base potentially). It's the job of
|
||||
// the caller to resolve these.
|
||||
assert((isa<SelectInst>(I) || isa<PHINode>(I)) &&
|
||||
@ -717,7 +717,7 @@ static Value *findBasePointer(Value *I, DefiningValueMapTy &cache) {
|
||||
//
|
||||
// Note: A simpler form of this would be to add the conflict form of all
|
||||
// PHIs without running the optimistic algorithm. This would be
|
||||
// analougous to pessimistic data flow and would likely lead to an
|
||||
// analogous to pessimistic data flow and would likely lead to an
|
||||
// overall worse solution.
|
||||
|
||||
#ifndef NDEBUG
|
||||
@ -915,7 +915,7 @@ static Value *findBasePointer(Value *I, DefiningValueMapTy &cache) {
|
||||
assert(base != nullptr && "unknown BDVState!");
|
||||
}
|
||||
|
||||
// In essense this assert states: the only way two
|
||||
// In essence this assert states: the only way two
|
||||
// values incoming from the same basic block may be
|
||||
// different is by being different bitcasts of the same
|
||||
// value. A cleanup that remains TODO is changing
|
||||
@ -1043,7 +1043,7 @@ findBasePointers(const StatepointLiveSetTy &live,
|
||||
|
||||
// If you see this trip and like to live really dangerously, the code should
|
||||
// be correct, just with idioms the verifier can't handle. You can try
|
||||
// disabling the verifier at your own substaintial risk.
|
||||
// disabling the verifier at your own substantial risk.
|
||||
assert(!isa<ConstantPointerNull>(base) &&
|
||||
"the relocation code needs adjustment to handle the relocation of "
|
||||
"a null pointer constant without causing false positives in the "
|
||||
@ -1089,7 +1089,7 @@ static void recomputeLiveInValues(
|
||||
Function &F, DominatorTree &DT, Pass *P, ArrayRef<CallSite> toUpdate,
|
||||
MutableArrayRef<struct PartiallyConstructedSafepointRecord> records) {
|
||||
// TODO-PERF: reuse the original liveness, then simply run the dataflow
|
||||
// again. The old values are still live and will help it stablize quickly.
|
||||
// again. The old values are still live and will help it stabilize quickly.
|
||||
GCPtrLivenessData RevisedLivenessData;
|
||||
computeLiveInValues(DT, F, RevisedLivenessData);
|
||||
for (size_t i = 0; i < records.size(); i++) {
|
||||
@ -1131,7 +1131,7 @@ static int find_index(ArrayRef<Value *> livevec, Value *val) {
|
||||
return index;
|
||||
}
|
||||
|
||||
// Create new attribute set containing only attributes which can be transfered
|
||||
// Create new attribute set containing only attributes which can be transferred
|
||||
// from original call to the safepoint.
|
||||
static AttributeSet legalizeCallAttributes(AttributeSet AS) {
|
||||
AttributeSet ret;
|
||||
@ -1263,7 +1263,7 @@ makeStatepointExplicitImpl(const CallSite &CS, /* to replace */
|
||||
// Currently we will fail on parameter attributes and on certain
|
||||
// function attributes.
|
||||
AttributeSet new_attrs = legalizeCallAttributes(toReplace->getAttributes());
|
||||
// In case if we can handle this set of sttributes - set up function attrs
|
||||
// In case if we can handle this set of attributes - set up function attrs
|
||||
// directly on statepoint and return attrs later for gc_result intrinsic.
|
||||
call->setAttributes(new_attrs.getFnAttributes());
|
||||
return_attributes = new_attrs.getRetAttributes();
|
||||
@ -1293,7 +1293,7 @@ makeStatepointExplicitImpl(const CallSite &CS, /* to replace */
|
||||
// Currently we will fail on parameter attributes and on certain
|
||||
// function attributes.
|
||||
AttributeSet new_attrs = legalizeCallAttributes(toReplace->getAttributes());
|
||||
// In case if we can handle this set of sttributes - set up function attrs
|
||||
// In case if we can handle this set of attributes - set up function attrs
|
||||
// directly on statepoint and return attrs later for gc_result intrinsic.
|
||||
invoke->setAttributes(new_attrs.getFnAttributes());
|
||||
return_attributes = new_attrs.getRetAttributes();
|
||||
@ -1571,7 +1571,7 @@ static void relocationViaAlloca(
|
||||
VisitedLiveValues);
|
||||
|
||||
if (ClobberNonLive) {
|
||||
// As a debuging aid, pretend that an unrelocated pointer becomes null at
|
||||
// As a debugging aid, pretend that an unrelocated pointer becomes null at
|
||||
// the gc.statepoint. This will turn some subtle GC problems into
|
||||
// slightly easier to debug SEGVs. Note that on large IR files with
|
||||
// lots of gc.statepoints this is extremely costly both memory and time
|
||||
@ -1742,10 +1742,10 @@ static void findLiveReferences(
|
||||
|
||||
/// Remove any vector of pointers from the liveset by scalarizing them over the
|
||||
/// statepoint instruction. Adds the scalarized pieces to the liveset. It
|
||||
/// would be preferrable to include the vector in the statepoint itself, but
|
||||
/// would be preferable to include the vector in the statepoint itself, but
|
||||
/// the lowering code currently does not handle that. Extending it would be
|
||||
/// slightly non-trivial since it requires a format change. Given how rare
|
||||
/// such cases are (for the moment?) scalarizing is an acceptable comprimise.
|
||||
/// such cases are (for the moment?) scalarizing is an acceptable compromise.
|
||||
static void splitVectorValues(Instruction *StatepointInst,
|
||||
StatepointLiveSetTy &LiveSet,
|
||||
DenseMap<Value *, Value *>& PointerToBase,
|
||||
@ -1876,7 +1876,7 @@ static void splitVectorValues(Instruction *StatepointInst,
|
||||
// Helper function for the "rematerializeLiveValues". It walks use chain
|
||||
// starting from the "CurrentValue" until it meets "BaseValue". Only "simple"
|
||||
// values are visited (currently it is GEP's and casts). Returns true if it
|
||||
// sucessfully reached "BaseValue" and false otherwise.
|
||||
// successfully reached "BaseValue" and false otherwise.
|
||||
// Fills "ChainToBase" array with all visited values. "BaseValue" is not
|
||||
// recorded.
|
||||
static bool findRematerializableChainToBasePointer(
|
||||
@ -2128,7 +2128,7 @@ static bool insertParsePoints(Function &F, DominatorTree &DT, Pass *P,
|
||||
}
|
||||
assert(records.size() == toUpdate.size());
|
||||
|
||||
// A) Identify all gc pointers which are staticly live at the given call
|
||||
// A) Identify all gc pointers which are statically live at the given call
|
||||
// site.
|
||||
findLiveReferences(F, DT, P, toUpdate, records);
|
||||
|
||||
@ -2205,7 +2205,7 @@ static bool insertParsePoints(Function &F, DominatorTree &DT, Pass *P,
|
||||
}
|
||||
|
||||
// In order to reduce live set of statepoint we might choose to rematerialize
|
||||
// some values instead of relocating them. This is purelly an optimization and
|
||||
// some values instead of relocating them. This is purely an optimization and
|
||||
// does not influence correctness.
|
||||
TargetTransformInfo &TTI =
|
||||
P->getAnalysis<TargetTransformInfoWrapperPass>().getTTI(F);
|
||||
@ -2450,7 +2450,7 @@ static void computeLiveInValues(BasicBlock::reverse_iterator rbegin,
|
||||
"support for FCA unimplemented");
|
||||
if (isHandledGCPointerType(V->getType()) && !isa<Constant>(V)) {
|
||||
// The choice to exclude all things constant here is slightly subtle.
|
||||
// There are two idependent reasons:
|
||||
// There are two independent reasons:
|
||||
// - We assume that things which are constant (from LLVM's definition)
|
||||
// do not move at runtime. For example, the address of a global
|
||||
// variable is fixed, even though it's contents may not be.
|
||||
@ -2588,7 +2588,7 @@ static void computeLiveInValues(DominatorTree &DT, Function &F,
|
||||
} // while( !worklist.empty() )
|
||||
|
||||
#ifndef NDEBUG
|
||||
// Sanity check our ouput against SSA properties. This helps catch any
|
||||
// Sanity check our output against SSA properties. This helps catch any
|
||||
// missing kills during the above iteration.
|
||||
for (BasicBlock &BB : F) {
|
||||
checkBasicSSA(DT, Data, BB);
|
||||
|
||||
@ -270,7 +270,8 @@ public:
|
||||
friend class AllocaSlices;
|
||||
friend class AllocaSlices::partition_iterator;
|
||||
|
||||
/// \brief The begining and ending offsets of the alloca for this partition.
|
||||
/// \brief The beginning and ending offsets of the alloca for this
|
||||
/// partition.
|
||||
uint64_t BeginOffset, EndOffset;
|
||||
|
||||
/// \brief The start end end iterators of this partition.
|
||||
@ -439,7 +440,7 @@ public:
|
||||
|
||||
// OK, we need to consume new slices. Set the end offset based on the
|
||||
// current slice, and step SJ past it. The beginning offset of the
|
||||
// parttion is the beginning offset of the next slice unless we have
|
||||
// partition is the beginning offset of the next slice unless we have
|
||||
// pre-existing split slices that are continuing, in which case we begin
|
||||
// at the prior end offset.
|
||||
P.BeginOffset = P.SplitTails.empty() ? P.SI->beginOffset() : P.EndOffset;
|
||||
@ -493,7 +494,7 @@ public:
|
||||
"End iterators don't match between compared partition iterators!");
|
||||
|
||||
// The observed positions of partitions is marked by the P.SI iterator and
|
||||
// the emptyness of the split slices. The latter is only relevant when
|
||||
// the emptiness of the split slices. The latter is only relevant when
|
||||
// P.SI == SE, as the end iterator will additionally have an empty split
|
||||
// slices list, but the prior may have the same P.SI and a tail of split
|
||||
// slices.
|
||||
@ -1934,7 +1935,7 @@ static Value *convertValue(const DataLayout &DL, IRBuilderTy &IRB, Value *V,
|
||||
|
||||
/// \brief Test whether the given slice use can be promoted to a vector.
|
||||
///
|
||||
/// This function is called to test each entry in a partioning which is slated
|
||||
/// This function is called to test each entry in a partition which is slated
|
||||
/// for a single slice.
|
||||
static bool isVectorPromotionViableForSlice(AllocaSlices::Partition &P,
|
||||
const Slice &S, VectorType *Ty,
|
||||
@ -2130,7 +2131,7 @@ static bool isIntegerWideningViableForSlice(const Slice &S,
|
||||
uint64_t RelEnd = S.endOffset() - AllocBeginOffset;
|
||||
|
||||
// We can't reasonably handle cases where the load or store extends past
|
||||
// the end of the aloca's type and into its padding.
|
||||
// the end of the alloca's type and into its padding.
|
||||
if (RelEnd > Size)
|
||||
return false;
|
||||
|
||||
@ -3711,7 +3712,7 @@ bool SROA::presplitLoadsAndStores(AllocaInst &AI, AllocaSlices &AS) {
|
||||
return true;
|
||||
}),
|
||||
Stores.end());
|
||||
// Now we have to go *back* through all te stores, because a later store may
|
||||
// Now we have to go *back* through all the stores, because a later store may
|
||||
// have caused an earlier store's load to become unsplittable and if it is
|
||||
// unsplittable for the later store, then we can't rely on it being split in
|
||||
// the earlier store either.
|
||||
@ -3972,7 +3973,7 @@ bool SROA::presplitLoadsAndStores(AllocaInst &AI, AllocaSlices &AS) {
|
||||
|
||||
// Mark the original store as dead now that we've split it up and kill its
|
||||
// slice. Note that we leave the original load in place unless this store
|
||||
// was its ownly use. It may in turn be split up if it is an alloca load
|
||||
// was its only use. It may in turn be split up if it is an alloca load
|
||||
// for some other alloca, but it may be a normal load. This may introduce
|
||||
// redundant loads, but where those can be merged the rest of the optimizer
|
||||
// should handle the merging, and this uncovers SSA splits which is more
|
||||
@ -4230,7 +4231,7 @@ bool SROA::splitAlloca(AllocaInst &AI, AllocaSlices &AS) {
|
||||
std::max<unsigned>(NumPartitions, MaxPartitionsPerAlloca);
|
||||
|
||||
// Migrate debug information from the old alloca to the new alloca(s)
|
||||
// and the individial partitions.
|
||||
// and the individual partitions.
|
||||
if (DbgDeclareInst *DbgDecl = FindAllocaDbgDeclare(&AI)) {
|
||||
auto *Var = DbgDecl->getVariable();
|
||||
auto *Expr = DbgDecl->getExpression();
|
||||
|
||||
@ -484,7 +484,7 @@ void llvm::CloneAndPruneIntoFromInst(Function *NewFunc, const Function *OldFunc,
|
||||
}
|
||||
|
||||
#ifndef NDEBUG
|
||||
// If the cloning starts at the begining of the function, verify that
|
||||
// If the cloning starts at the beginning of the function, verify that
|
||||
// the function arguments are mapped.
|
||||
if (!StartingInst)
|
||||
for (Function::const_arg_iterator II = OldFunc->arg_begin(),
|
||||
|
||||
@ -163,7 +163,7 @@ static void fixPhis(BasicBlock *SuccBB, BasicBlock *OrigBB, BasicBlock *NewBB,
|
||||
I != IE; ++I) {
|
||||
PHINode *PN = cast<PHINode>(I);
|
||||
|
||||
// Only update the first occurence.
|
||||
// Only update the first occurrence.
|
||||
unsigned Idx = 0, E = PN->getNumIncomingValues();
|
||||
unsigned LocalNumMergedCases = NumMergedCases;
|
||||
for (; Idx != E; ++Idx) {
|
||||
@ -173,7 +173,7 @@ static void fixPhis(BasicBlock *SuccBB, BasicBlock *OrigBB, BasicBlock *NewBB,
|
||||
}
|
||||
}
|
||||
|
||||
// Remove additional occurences coming from condensed cases and keep the
|
||||
// Remove additional occurrences coming from condensed cases and keep the
|
||||
// number of incoming values equal to the number of branches to SuccBB.
|
||||
SmallVector<unsigned, 8> Indices;
|
||||
for (++Idx; LocalNumMergedCases > 0 && Idx < E; ++Idx)
|
||||
@ -424,7 +424,7 @@ void LowerSwitch::processSwitchInst(SwitchInst *SI) {
|
||||
std::vector<IntRange> UnreachableRanges;
|
||||
|
||||
if (isa<UnreachableInst>(Default->getFirstNonPHIOrDbg())) {
|
||||
// Make the bounds tightly fitted around the case value range, becase we
|
||||
// Make the bounds tightly fitted around the case value range, because we
|
||||
// know that the value passed to the switch must be exactly one of the case
|
||||
// values.
|
||||
assert(!Cases.empty());
|
||||
|
||||
@ -63,7 +63,7 @@ namespace {
|
||||
|
||||
/// Iteratively perform simplification on a worklist of users of the
|
||||
/// specified induction variable. This is the top-level driver that applies
|
||||
/// all simplicitions to users of an IV.
|
||||
/// all simplifications to users of an IV.
|
||||
void simplifyUsers(PHINode *CurrIV, IVVisitor *V = nullptr);
|
||||
|
||||
Value *foldIVUser(Instruction *UseInst, Instruction *IVOperand);
|
||||
@ -184,7 +184,7 @@ void SimplifyIndvar::eliminateIVComparison(ICmpInst *ICmp, Value *IVOperand) {
|
||||
InvariantPredicate, InvariantLHS,
|
||||
InvariantRHS)) {
|
||||
|
||||
// Rewrite the comparision to a loop invariant comparision if it can be done
|
||||
// Rewrite the comparison to a loop invariant comparison if it can be done
|
||||
// cheaply, where cheaply means "we don't need to emit any new
|
||||
// instructions".
|
||||
|
||||
@ -482,8 +482,8 @@ static bool isSimpleIVUser(Instruction *I, const Loop *L, ScalarEvolution *SE) {
|
||||
/// This algorithm does not require IVUsers analysis. Instead, it simplifies
|
||||
/// instructions in-place during analysis. Rather than rewriting induction
|
||||
/// variables bottom-up from their users, it transforms a chain of IVUsers
|
||||
/// top-down, updating the IR only when it encouters a clear optimization
|
||||
/// opportunitiy.
|
||||
/// top-down, updating the IR only when it encounters a clear optimization
|
||||
/// opportunity.
|
||||
///
|
||||
/// Once DisableIVRewrite is default, LSR will be the only client of IVUsers.
|
||||
///
|
||||
|
||||
@ -162,7 +162,7 @@ static bool canCombineAsAltInst(unsigned Op) {
|
||||
return false;
|
||||
}
|
||||
|
||||
/// \returns ShuffleVector instruction if intructions in \p VL have
|
||||
/// \returns ShuffleVector instruction if instructions in \p VL have
|
||||
/// alternate fadd,fsub / fsub,fadd/add,sub/sub,add sequence.
|
||||
/// (i.e. e.g. opcodes of fadd,fsub,fadd,fsub...)
|
||||
static unsigned isAltInst(ArrayRef<Value *> VL) {
|
||||
@ -393,7 +393,7 @@ public:
|
||||
/// \brief Perform LICM and CSE on the newly generated gather sequences.
|
||||
void optimizeGatherSequence();
|
||||
|
||||
/// \returns true if it is benefitial to reverse the vector order.
|
||||
/// \returns true if it is beneficial to reverse the vector order.
|
||||
bool shouldReorder() const {
|
||||
return NumLoadsWantToChangeOrder > NumLoadsWantToKeepOrder;
|
||||
}
|
||||
@ -441,7 +441,7 @@ private:
|
||||
/// \returns a vector from a collection of scalars in \p VL.
|
||||
Value *Gather(ArrayRef<Value *> VL, VectorType *Ty);
|
||||
|
||||
/// \returns whether the VectorizableTree is fully vectoriable and will
|
||||
/// \returns whether the VectorizableTree is fully vectorizable and will
|
||||
/// be beneficial even the tree height is tiny.
|
||||
bool isFullyVectorizableTinyTree();
|
||||
|
||||
@ -2898,8 +2898,8 @@ void BoUpSLP::BlockScheduling::calculateDependencies(ScheduleData *SD,
|
||||
}
|
||||
} else {
|
||||
// I'm not sure if this can ever happen. But we need to be safe.
|
||||
// This lets the instruction/bundle never be scheduled and eventally
|
||||
// disable vectorization.
|
||||
// This lets the instruction/bundle never be scheduled and
|
||||
// eventually disable vectorization.
|
||||
BundleMember->Dependencies++;
|
||||
BundleMember->incrementUnscheduledDeps(1);
|
||||
}
|
||||
@ -3005,7 +3005,7 @@ void BoUpSLP::scheduleBlock(BlockScheduling *BS) {
|
||||
};
|
||||
std::set<ScheduleData *, ScheduleDataCompare> ReadyInsts;
|
||||
|
||||
// Ensure that all depencency data is updated and fill the ready-list with
|
||||
// Ensure that all dependency data is updated and fill the ready-list with
|
||||
// initial instructions.
|
||||
int Idx = 0;
|
||||
int NumToSchedule = 0;
|
||||
@ -3732,7 +3732,7 @@ public:
|
||||
|
||||
private:
|
||||
|
||||
/// \brief Calcuate the cost of a reduction.
|
||||
/// \brief Calculate the cost of a reduction.
|
||||
int getReductionCost(TargetTransformInfo *TTI, Value *FirstReducedVal) {
|
||||
Type *ScalarTy = FirstReducedVal->getType();
|
||||
Type *VecTy = VectorType::get(ScalarTy, ReduxWidth);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user