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[AArch64][GlobalISel] Promote scalar G_SHL constant shift amounts to s64.

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This was supposed to be done in the first place as is currently the case for
G_ASHR and G_LSHR but was forgotten when the original shift legalization
overhaul was done last year.

This was exposed because we started falling back on s32 = s32, s64 SHLs
due to a recent combiner change.

Gives a very minor (0.1%) code size -O0 improvement on consumer-typeset.
This commit is contained in:
Amara Emerson 2020-09-27 01:45:09 -07:00
parent a2179f553d
commit 69a45b21be
5 changed files with 16 additions and 11 deletions
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7
lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
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@ -98,8 +98,15 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.moreElementsToNextPow2(0); .moreElementsToNextPow2(0);
getActionDefinitionsBuilder(G_SHL) getActionDefinitionsBuilder(G_SHL)
.customIf([=](const LegalityQuery &Query) {
const auto &SrcTy = Query.Types[0];
const auto &AmtTy = Query.Types[1];
return !SrcTy.isVector() && SrcTy.getSizeInBits() == 32 &&
AmtTy.getSizeInBits() == 32;
})
.legalFor({ .legalFor({
{s32, s32}, {s32, s32},
{s32, s64},
{s64, s64}, {s64, s64},
{v16s8, v16s8}, {v16s8, v16s8},
{v4s16, v4s16}, {v4s16, v4s16},

5
test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir
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@ -6,11 +6,12 @@ name: test_merge_s4
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: test_merge_s4 ; CHECK-LABEL: name: test_merge_s4
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 4
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[C2]], [[C1]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[C2]], [[C1]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C]](s32) ; CHECK: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C3]](s64)
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C2]](s32) ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SHL]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)

7
test/CodeGen/AArch64/GlobalISel/legalize-non-pow2-load-store.mir
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@ -28,12 +28,11 @@ body: |
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C1]](s64) ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C1]](s64)
; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load 1 from %ir.ptr + 2, align 4) ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load 1 from %ir.ptr + 2, align 4)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C2]](s32) ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C2]](s64)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]] ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[OR]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
; CHECK: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY2]], [[C2]](s64)
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY2]], [[C3]](s64)
; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C1]](s64) ; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C1]](s64)
; CHECK: G_STORE [[COPY2]](s32), [[COPY1]](p0) :: (store 2 into %ir.ptr2, align 4) ; CHECK: G_STORE [[COPY2]](s32), [[COPY1]](p0) :: (store 2 into %ir.ptr2, align 4)
; CHECK: G_STORE [[LSHR]](s32), [[PTR_ADD1]](p0) :: (store 1 into %ir.ptr2 + 2, align 4) ; CHECK: G_STORE [[LSHR]](s32), [[PTR_ADD1]](p0) :: (store 1 into %ir.ptr2 + 2, align 4)

4
test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
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@ -235,8 +235,8 @@ body: |
; CHECK-LABEL: name: shl_cimm_32 ; CHECK-LABEL: name: shl_cimm_32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32) ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s64)
; CHECK: $w0 = COPY [[SHL]](s32) ; CHECK: $w0 = COPY [[SHL]](s32)
; CHECK: RET_ReallyLR implicit $w0 ; CHECK: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0 %0:_(s32) = COPY $w0

4
test/CodeGen/AArch64/arm64-clrsb.ll
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@ -21,10 +21,8 @@ entry:
; CHECK-LABEL: clrsb32 ; CHECK-LABEL: clrsb32
; CHECK: cls [[TEMP:w[0-9]+]], [[TEMP]] ; CHECK: cls [[TEMP:w[0-9]+]], [[TEMP]]
; FIXME: We should produce the same result here to save some code size. After
; that, we can remove the GISEL special casing.
; GISEL-LABEL: clrsb32 ; GISEL-LABEL: clrsb32
; GISEL: clz ; GISEL: cls [[TEMP:w[0-9]+]], [[TEMP]]
} }
; Function Attrs: nounwind ssp ; Function Attrs: nounwind ssp