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Tests: Add branch weights to non-layout tests.

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Add branch weights to a few tests that aren't testing layout to make them less
sensitive to changes in the layout algorithm.

llvm-svn: 277186
This commit is contained in:
Kyle Butt 2016-07-29 18:09:25 +00:00
parent ca6435867c
commit 69c0840f56
4 changed files with 20 additions and 12 deletions
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5
test/CodeGen/AArch64/arm64-andCmpBrToTBZ.ll
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@ -13,7 +13,7 @@ entry:
if.end: ; preds = %entry
%and.i.i.i = and i32 %int1, 4
%tobool.i.i.i = icmp eq i32 %and.i.i.i, 0
br i1 %tobool.i.i.i, label %if.end12, label %land.rhs.i
br i1 %tobool.i.i.i, label %if.end12, label %land.rhs.i, !prof !1
land.rhs.i: ; preds = %if.end
%cmp.i.i.i = icmp eq i8* %str12, %str13
@ -36,7 +36,7 @@ if.then3: ; preds = %_ZNK7WebCore4Node10
if.end5: ; preds = %_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit, %lor.rhs.i.i.i
; CHECK: %if.end5
; CHECK: tbz
br i1 %tobool.i.i.i, label %if.end12, label %land.rhs.i19
br i1 %tobool.i.i.i, label %if.end12, label %land.rhs.i19, !prof !1
land.rhs.i19: ; preds = %if.end5
%cmp.i.i.i18 = icmp eq i8* %str6, %str7
@ -69,3 +69,4 @@ return: ; preds = %if.end12, %if.then9
}
attributes #0 = { nounwind ssp }
!1 = !{!"branch_weights", i32 3, i32 5}

11
test/CodeGen/AArch64/compare-branch.ll
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@ -8,25 +8,25 @@ define void @foo() {
%val1 = load volatile i32, i32* @var32
%tst1 = icmp eq i32 %val1, 0
br i1 %tst1, label %end, label %test2
br i1 %tst1, label %end, label %test2, !prof !1
; CHECK: cbz {{w[0-9]+}}, .LBB
test2:
%val2 = load volatile i32, i32* @var32
%tst2 = icmp ne i32 %val2, 0
br i1 %tst2, label %end, label %test3
br i1 %tst2, label %end, label %test3, !prof !1
; CHECK: cbnz {{w[0-9]+}}, .LBB
test3:
%val3 = load volatile i64, i64* @var64
%tst3 = icmp eq i64 %val3, 0
br i1 %tst3, label %end, label %test4
br i1 %tst3, label %end, label %test4, !prof !1
; CHECK: cbz {{x[0-9]+}}, .LBB
test4:
%val4 = load volatile i64, i64* @var64
%tst4 = icmp ne i64 %val4, 0
br i1 %tst4, label %end, label %test5
br i1 %tst4, label %end, label %test5, !prof !1
; CHECK: cbnz {{x[0-9]+}}, .LBB
test5:
@ -36,3 +36,6 @@ test5:
end:
ret void
}
!1 = !{!"branch_weights", i32 1, i32 1}

8
test/CodeGen/AArch64/logical_shifted_reg.ll
View File

@ -198,7 +198,7 @@ define void @flag_setting() {
; CHECK: b.gt .L
%simple_and = and i64 %val1, %val2
%tst1 = icmp sgt i64 %simple_and, 0
br i1 %tst1, label %ret, label %test2
br i1 %tst1, label %ret, label %test2, !prof !1
test2:
; CHECK: tst {{x[0-9]+}}, {{x[0-9]+}}, lsl #63
@ -206,7 +206,7 @@ test2:
%shifted_op = shl i64 %val2, 63
%shifted_and = and i64 %val1, %shifted_op
%tst2 = icmp slt i64 %shifted_and, 0
br i1 %tst2, label %ret, label %test3
br i1 %tst2, label %ret, label %test3, !prof !1
test3:
; CHECK: tst {{x[0-9]+}}, {{x[0-9]+}}, asr #12
@ -214,7 +214,7 @@ test3:
%asr_op = ashr i64 %val2, 12
%asr_and = and i64 %asr_op, %val1
%tst3 = icmp sgt i64 %asr_and, 0
br i1 %tst3, label %ret, label %other_exit
br i1 %tst3, label %ret, label %other_exit, !prof !1
other_exit:
store volatile i64 %val1, i64* @var1_64
@ -222,3 +222,5 @@ other_exit:
ret:
ret void
}
!1 = !{!"branch_weights", i32 1, i32 1}

8
test/CodeGen/SystemZ/tdc-06.ll
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@ -14,14 +14,14 @@ entry:
; CHECK: ltdbr %f0, %f0
; CHECK: je [[RET:.L.*]]
%testeq = fcmp oeq double %x, 0.000000e+00
br i1 %testeq, label %ret, label %nonzero
br i1 %testeq, label %ret, label %nonzero, !prof !1
nonzero:
; CHECK: lhi %r2, 1
; CHECK: cdbr %f0, %f0
; CHECK: jo [[RET]]
%testnan = fcmp uno double %x, 0.000000e+00
br i1 %testnan, label %ret, label %nonzeroord
br i1 %testnan, label %ret, label %nonzeroord, !prof !1
nonzeroord:
; CHECK: lhi %r2, 2
@ -29,7 +29,7 @@ nonzeroord:
; CHECK: jl [[RET]]
%abs = tail call double @llvm.fabs.f64(double %x)
%testinf = fcmp oeq double %abs, 0x7FF0000000000000
br i1 %testinf, label %ret, label %finite
br i1 %testinf, label %ret, label %finite, !prof !1
finite:
; CHECK: lhi %r2, 3
@ -46,3 +46,5 @@ ret:
%res = phi i32 [ 5, %entry ], [ 1, %nonzero ], [ 2, %nonzeroord ], [ %finres, %finite ]
ret i32 %res
}
!1 = !{!"branch_weights", i32 1, i32 1}