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AMDGPU/SI: Don't fix a PHI under uniform branch in SIFixSGPRCopies only when sources and destination are all sgprs
Summary: If a PHI has at lease one VGPR operand, we have to fix the PHI in SIFixSGPRCopies. Reviewer: Matt Differential Revision: http://reviews.llvm.org/D34727 llvm-svn: 309959
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@ -604,7 +604,8 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) {
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// We don't need to fix the PHI if the common dominator of the
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// two incoming blocks terminates with a uniform branch.
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if (MI.getNumExplicitOperands() == 5) {
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bool HasVGPROperand = phiHasVGPROperands(MI, MRI, TRI, TII);
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if (MI.getNumExplicitOperands() == 5 && !HasVGPROperand) {
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MachineBasicBlock *MBB0 = MI.getOperand(2).getMBB();
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MachineBasicBlock *MBB1 = MI.getOperand(4).getMBB();
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@ -649,8 +650,7 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) {
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// is no chance for values to be over-written.
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SmallSet<unsigned, 8> Visited;
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if (phiHasVGPROperands(MI, MRI, TRI, TII) ||
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!phiHasBreakDef(MI, MRI, Visited)) {
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if (HasVGPROperand || !phiHasBreakDef(MI, MRI, Visited)) {
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DEBUG(dbgs() << "Fixing PHI: " << MI);
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TII->moveToVALU(MI);
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}
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@ -557,6 +557,28 @@ done:
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ret void
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}
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; GCN-LABEL: {{^}}move_to_valu_vgpr_operand_phi:
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; GCN: v_add_i32_e32
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; GCN: ds_write_b32
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define void @move_to_valu_vgpr_operand_phi(i32 addrspace(3)* %out) {
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bb0:
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br label %bb1
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bb1: ; preds = %bb3, %bb0
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%tmp0 = phi i32 [ 8, %bb0 ], [ %tmp4, %bb3 ]
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%tmp1 = add nsw i32 %tmp0, -1
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%tmp2 = getelementptr inbounds i32, i32 addrspace(3)* %out, i32 %tmp1
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br i1 undef, label %bb2, label %bb3
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bb2: ; preds = %bb1
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store volatile i32 1, i32 addrspace(3)* %tmp2, align 4
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br label %bb3
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bb3: ; preds = %bb2, %bb1
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%tmp4 = add nsw i32 %tmp0, 2
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br label %bb1
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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attributes #0 = { nounwind readnone }
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