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[AArch64] Avoid selecting XZR inline ASM memory operand

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Restricting register class to PointerRegClass for memory operands.

Also fix the PointerRegClass for AArch64 from GPR64 to GPR64sp, since
XZR cannot hold a memory pointer while SP is.

Fixes PR33134.

Differential Revision: https://reviews.llvm.org/D34999

llvm-svn: 308060
This commit is contained in:
Yi Kong 2017-07-14 21:46:16 +00:00
parent 2bb37a1dab
commit 69f00572a2
3 changed files with 22 additions and 5 deletions
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15
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
View File

@ -239,10 +239,17 @@ bool AArch64DAGToDAGISel::SelectInlineAsmMemoryOperand(
case InlineAsm::Constraint_i:
case InlineAsm::Constraint_m:
case InlineAsm::Constraint_Q:
// Require the address to be in a register. That is safe for all AArch64
// variants and it is hard to do anything much smarter without knowing
// how the operand is used.
OutOps.push_back(Op);
// We need to make sure that this one operand does not end up in XZR, thus
// require the address to be in a PointerRegClass register.
const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
const TargetRegisterClass *TRC = TRI->getPointerRegClass(*MF);
SDLoc dl(Op);
SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i64);
SDValue NewOp =
SDValue(CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
dl, Op.getValueType(),
Op, RC), 0);
OutOps.push_back(NewOp);
return false;
}
return true;

2
lib/Target/AArch64/AArch64RegisterInfo.cpp
View File

@ -167,7 +167,7 @@ bool AArch64RegisterInfo::isConstantPhysReg(unsigned PhysReg) const {
const TargetRegisterClass *
AArch64RegisterInfo::getPointerRegClass(const MachineFunction &MF,
unsigned Kind) const {
return &AArch64::GPR64RegClass;
return &AArch64::GPR64spRegClass;
}
const TargetRegisterClass *

10
test/CodeGen/AArch64/arm64-inline-asm.ll
View File

@ -261,3 +261,13 @@ define void @test_inline_modifier_a(i8* %ptr) nounwind {
; CHECK: prfm pldl1keep, [x0]
ret void
}
; PR33134
define void @test_zero_address() {
entry:
; CHECK-LABEL: test_zero_address
; CHECK: mov {{x[0-9]+}}, xzr
; CHECK: ldr {{x[0-9]+}}, {{[x[0-9]+]}}
tail call i32 asm sideeffect "ldr $0, $1 \0A", "=r,*Q"(i32* null)
ret void
}