RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 11:13:28 +01:00
Code Issues Projects Releases Wiki Activity

[X86] Correct regular expression in Zen scheduler model that was excluding JECXZ instruction.

Browse Source 
The regex was looking for JECXZ_32 or JECXZ_64, but their is just one instruction called JECXZ. They used to exist as separate instructions, but were merged over 3 years ago.

llvm-svn: 327880
This commit is contained in:
Craig Topper 2018-03-19 19:00:29 +00:00
parent 87d6c90ec4
commit 69f36550a3
3 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Target/X86/X86ScheduleZnver1.td
View File

@ -474,7 +474,7 @@ def : InstRW<[ZnWriteDiv64], (instregex "DIV64r", "IDIV64r")>;
// J(E|R)CXZ.
def ZnWriteJCXZ : SchedWriteRes<[ZnALU03]>;
def : InstRW<[ZnWriteJCXZ], (instregex "JCXZ", "JECXZ_(32|64)", "JRCXZ")>;
def : InstRW<[ZnWriteJCXZ], (instrs JCXZ, JECXZ, JRCXZ)>;
// INTO
def : InstRW<[WriteMicrocoded], (instregex "INTO")>;

2
test/CodeGen/X86/schedule-x86_32.ll
View File

@ -1348,7 +1348,7 @@ define void @test_jcxz_jecxz() optsize {
; ZNVER1-NEXT: #APP
; ZNVER1-NEXT: JXTGT:
; ZNVER1-NEXT: jcxz JXTGT # sched: [1:0.50]
; ZNVER1-NEXT: jecxz JXTGT # sched: [1:0.25]
; ZNVER1-NEXT: jecxz JXTGT # sched: [1:0.50]
; ZNVER1-NEXT: #NO_APP
; ZNVER1-NEXT: retl # sched: [1:0.50]
call void asm sideeffect "JXTGT: \0A\09 jcxz JXTGT \0A\09 jecxz JXTGT", ""()

2
test/CodeGen/X86/schedule-x86_64.ll
View File

@ -7279,7 +7279,7 @@ define void @test_jecxz_jrcxz() optsize {
; ZNVER1: # %bb.0:
; ZNVER1-NEXT: #APP
; ZNVER1-NEXT: JXTGT:
; ZNVER1-NEXT: jecxz JXTGT # sched: [1:0.25]
; ZNVER1-NEXT: jecxz JXTGT # sched: [1:0.50]
; ZNVER1-NEXT: jrcxz JXTGT # sched: [1:0.50]
; ZNVER1-NEXT: #NO_APP
; ZNVER1-NEXT: retq # sched: [1:0.50]